1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/msi.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_pci.h> 22 #include <linux/of_platform.h> 23 #include <linux/pci.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 30 #include "../pci.h" 31 32 /* PCIe shared registers */ 33 #define PCIE_SYS_CFG 0x00 34 #define PCIE_INT_ENABLE 0x0c 35 #define PCIE_CFG_ADDR 0x20 36 #define PCIE_CFG_DATA 0x24 37 38 /* PCIe per port registers */ 39 #define PCIE_BAR0_SETUP 0x10 40 #define PCIE_CLASS 0x34 41 #define PCIE_LINK_STATUS 0x50 42 43 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 44 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 45 #define PCIE_PORT_LINKUP BIT(0) 46 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 47 48 #define PCIE_BAR_ENABLE BIT(0) 49 #define PCIE_REVISION_ID BIT(0) 50 #define PCIE_CLASS_CODE (0x60400 << 8) 51 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 52 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 53 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 54 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 55 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 56 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 57 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 58 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 59 60 /* MediaTek specific configuration registers */ 61 #define PCIE_FTS_NUM 0x70c 62 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 63 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) 64 65 #define PCIE_FC_CREDIT 0x73c 66 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 67 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 68 69 /* PCIe V2 share registers */ 70 #define PCIE_SYS_CFG_V2 0x0 71 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 72 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 73 74 /* PCIe V2 per-port registers */ 75 #define PCIE_MSI_VECTOR 0x0c0 76 77 #define PCIE_CONF_VEND_ID 0x100 78 #define PCIE_CONF_DEVICE_ID 0x102 79 #define PCIE_CONF_CLASS_ID 0x106 80 81 #define PCIE_INT_MASK 0x420 82 #define INTX_MASK GENMASK(19, 16) 83 #define INTX_SHIFT 16 84 #define PCIE_INT_STATUS 0x424 85 #define MSI_STATUS BIT(23) 86 #define PCIE_IMSI_STATUS 0x42c 87 #define PCIE_IMSI_ADDR 0x430 88 #define MSI_MASK BIT(23) 89 #define MTK_MSI_IRQS_NUM 32 90 91 #define PCIE_AHB_TRANS_BASE0_L 0x438 92 #define PCIE_AHB_TRANS_BASE0_H 0x43c 93 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 94 #define PCIE_AXI_WINDOW0 0x448 95 #define WIN_ENABLE BIT(7) 96 /* 97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space 98 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM 99 * start from 0x40000000). 100 */ 101 #define PCIE2AHB_SIZE 0x21 102 103 /* PCIe V2 configuration transaction header */ 104 #define PCIE_CFG_HEADER0 0x460 105 #define PCIE_CFG_HEADER1 0x464 106 #define PCIE_CFG_HEADER2 0x468 107 #define PCIE_CFG_WDATA 0x470 108 #define PCIE_APP_TLP_REQ 0x488 109 #define PCIE_CFG_RDATA 0x48c 110 #define APP_CFG_REQ BIT(0) 111 #define APP_CPL_STATUS GENMASK(7, 5) 112 113 #define CFG_WRRD_TYPE_0 4 114 #define CFG_WR_FMT 2 115 #define CFG_RD_FMT 0 116 117 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 118 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 119 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 120 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 121 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 122 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 123 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 124 #define CFG_HEADER_DW0(type, fmt) \ 125 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 126 #define CFG_HEADER_DW1(where, size) \ 127 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 128 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 129 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 130 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 131 132 #define PCIE_RST_CTRL 0x510 133 #define PCIE_PHY_RSTB BIT(0) 134 #define PCIE_PIPE_SRSTB BIT(1) 135 #define PCIE_MAC_SRSTB BIT(2) 136 #define PCIE_CRSTB BIT(3) 137 #define PCIE_PERSTB BIT(8) 138 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 139 #define PCIE_LINK_STATUS_V2 0x804 140 #define PCIE_PORT_LINKUP_V2 BIT(10) 141 142 struct mtk_pcie_port; 143 144 /** 145 * struct mtk_pcie_soc - differentiate between host generations 146 * @need_fix_class_id: whether this host's class ID needed to be fixed or not 147 * @need_fix_device_id: whether this host's device ID needed to be fixed or not 148 * @no_msi: Bridge has no MSI support, and relies on an external block 149 * @device_id: device ID which this host need to be fixed 150 * @ops: pointer to configuration access functions 151 * @startup: pointer to controller setting functions 152 * @setup_irq: pointer to initialize IRQ functions 153 */ 154 struct mtk_pcie_soc { 155 bool need_fix_class_id; 156 bool need_fix_device_id; 157 bool no_msi; 158 unsigned int device_id; 159 struct pci_ops *ops; 160 int (*startup)(struct mtk_pcie_port *port); 161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 162 }; 163 164 /** 165 * struct mtk_pcie_port - PCIe port information 166 * @base: IO mapped register base 167 * @list: port list 168 * @pcie: pointer to PCIe host info 169 * @reset: pointer to port reset control 170 * @sys_ck: pointer to transaction/data link layer clock 171 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 172 * and RC initiated MMIO access 173 * @axi_ck: pointer to application layer MMIO channel operating clock 174 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 175 * when pcie_mac_ck/pcie_pipe_ck is turned off 176 * @obff_ck: pointer to OBFF functional block operating clock 177 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 178 * @phy: pointer to PHY control block 179 * @slot: port slot 180 * @irq: GIC irq 181 * @irq_domain: legacy INTx IRQ domain 182 * @inner_domain: inner IRQ domain 183 * @msi_domain: MSI IRQ domain 184 * @lock: protect the msi_irq_in_use bitmap 185 * @msi_irq_in_use: bit map for assigned MSI IRQ 186 */ 187 struct mtk_pcie_port { 188 void __iomem *base; 189 struct list_head list; 190 struct mtk_pcie *pcie; 191 struct reset_control *reset; 192 struct clk *sys_ck; 193 struct clk *ahb_ck; 194 struct clk *axi_ck; 195 struct clk *aux_ck; 196 struct clk *obff_ck; 197 struct clk *pipe_ck; 198 struct phy *phy; 199 u32 slot; 200 int irq; 201 struct irq_domain *irq_domain; 202 struct irq_domain *inner_domain; 203 struct irq_domain *msi_domain; 204 struct mutex lock; 205 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 206 }; 207 208 /** 209 * struct mtk_pcie - PCIe host information 210 * @dev: pointer to PCIe device 211 * @base: IO mapped register base 212 * @cfg: IO mapped register map for PCIe config 213 * @free_ck: free-run reference clock 214 * @ports: pointer to PCIe port information 215 * @soc: pointer to SoC-dependent operations 216 */ 217 struct mtk_pcie { 218 struct device *dev; 219 void __iomem *base; 220 struct regmap *cfg; 221 struct clk *free_ck; 222 223 struct list_head ports; 224 const struct mtk_pcie_soc *soc; 225 }; 226 227 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 228 { 229 struct device *dev = pcie->dev; 230 231 clk_disable_unprepare(pcie->free_ck); 232 233 pm_runtime_put_sync(dev); 234 pm_runtime_disable(dev); 235 } 236 237 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 238 { 239 struct mtk_pcie *pcie = port->pcie; 240 struct device *dev = pcie->dev; 241 242 devm_iounmap(dev, port->base); 243 list_del(&port->list); 244 devm_kfree(dev, port); 245 } 246 247 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 248 { 249 struct mtk_pcie_port *port, *tmp; 250 251 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 252 phy_power_off(port->phy); 253 phy_exit(port->phy); 254 clk_disable_unprepare(port->pipe_ck); 255 clk_disable_unprepare(port->obff_ck); 256 clk_disable_unprepare(port->axi_ck); 257 clk_disable_unprepare(port->aux_ck); 258 clk_disable_unprepare(port->ahb_ck); 259 clk_disable_unprepare(port->sys_ck); 260 mtk_pcie_port_free(port); 261 } 262 263 mtk_pcie_subsys_powerdown(pcie); 264 } 265 266 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 267 { 268 u32 val; 269 int err; 270 271 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 272 !(val & APP_CFG_REQ), 10, 273 100 * USEC_PER_MSEC); 274 if (err) 275 return PCIBIOS_SET_FAILED; 276 277 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 278 return PCIBIOS_SET_FAILED; 279 280 return PCIBIOS_SUCCESSFUL; 281 } 282 283 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 284 int where, int size, u32 *val) 285 { 286 u32 tmp; 287 288 /* Write PCIe configuration transaction header for Cfgrd */ 289 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT), 290 port->base + PCIE_CFG_HEADER0); 291 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 292 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 293 port->base + PCIE_CFG_HEADER2); 294 295 /* Trigger h/w to transmit Cfgrd TLP */ 296 tmp = readl(port->base + PCIE_APP_TLP_REQ); 297 tmp |= APP_CFG_REQ; 298 writel(tmp, port->base + PCIE_APP_TLP_REQ); 299 300 /* Check completion status */ 301 if (mtk_pcie_check_cfg_cpld(port)) 302 return PCIBIOS_SET_FAILED; 303 304 /* Read cpld payload of Cfgrd */ 305 *val = readl(port->base + PCIE_CFG_RDATA); 306 307 if (size == 1) 308 *val = (*val >> (8 * (where & 3))) & 0xff; 309 else if (size == 2) 310 *val = (*val >> (8 * (where & 3))) & 0xffff; 311 312 return PCIBIOS_SUCCESSFUL; 313 } 314 315 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 316 int where, int size, u32 val) 317 { 318 /* Write PCIe configuration transaction header for Cfgwr */ 319 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT), 320 port->base + PCIE_CFG_HEADER0); 321 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 322 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 323 port->base + PCIE_CFG_HEADER2); 324 325 /* Write Cfgwr data */ 326 val = val << 8 * (where & 3); 327 writel(val, port->base + PCIE_CFG_WDATA); 328 329 /* Trigger h/w to transmit Cfgwr TLP */ 330 val = readl(port->base + PCIE_APP_TLP_REQ); 331 val |= APP_CFG_REQ; 332 writel(val, port->base + PCIE_APP_TLP_REQ); 333 334 /* Check completion status */ 335 return mtk_pcie_check_cfg_cpld(port); 336 } 337 338 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 339 unsigned int devfn) 340 { 341 struct mtk_pcie *pcie = bus->sysdata; 342 struct mtk_pcie_port *port; 343 struct pci_dev *dev = NULL; 344 345 /* 346 * Walk the bus hierarchy to get the devfn value 347 * of the port in the root bus. 348 */ 349 while (bus && bus->number) { 350 dev = bus->self; 351 bus = dev->bus; 352 devfn = dev->devfn; 353 } 354 355 list_for_each_entry(port, &pcie->ports, list) 356 if (port->slot == PCI_SLOT(devfn)) 357 return port; 358 359 return NULL; 360 } 361 362 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 363 int where, int size, u32 *val) 364 { 365 struct mtk_pcie_port *port; 366 u32 bn = bus->number; 367 368 port = mtk_pcie_find_port(bus, devfn); 369 if (!port) 370 return PCIBIOS_DEVICE_NOT_FOUND; 371 372 return mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 373 } 374 375 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 376 int where, int size, u32 val) 377 { 378 struct mtk_pcie_port *port; 379 u32 bn = bus->number; 380 381 port = mtk_pcie_find_port(bus, devfn); 382 if (!port) 383 return PCIBIOS_DEVICE_NOT_FOUND; 384 385 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 386 } 387 388 static struct pci_ops mtk_pcie_ops_v2 = { 389 .read = mtk_pcie_config_read, 390 .write = mtk_pcie_config_write, 391 }; 392 393 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 394 { 395 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 396 phys_addr_t addr; 397 398 /* MT2712/MT7622 only support 32-bit MSI addresses */ 399 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 400 msg->address_hi = 0; 401 msg->address_lo = lower_32_bits(addr); 402 403 msg->data = data->hwirq; 404 405 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 406 (int)data->hwirq, msg->address_hi, msg->address_lo); 407 } 408 409 static void mtk_msi_ack_irq(struct irq_data *data) 410 { 411 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 412 u32 hwirq = data->hwirq; 413 414 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 415 } 416 417 static struct irq_chip mtk_msi_bottom_irq_chip = { 418 .name = "MTK MSI", 419 .irq_compose_msi_msg = mtk_compose_msi_msg, 420 .irq_ack = mtk_msi_ack_irq, 421 }; 422 423 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 424 unsigned int nr_irqs, void *args) 425 { 426 struct mtk_pcie_port *port = domain->host_data; 427 unsigned long bit; 428 429 WARN_ON(nr_irqs != 1); 430 mutex_lock(&port->lock); 431 432 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 433 if (bit >= MTK_MSI_IRQS_NUM) { 434 mutex_unlock(&port->lock); 435 return -ENOSPC; 436 } 437 438 __set_bit(bit, port->msi_irq_in_use); 439 440 mutex_unlock(&port->lock); 441 442 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 443 domain->host_data, handle_edge_irq, 444 NULL, NULL); 445 446 return 0; 447 } 448 449 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 450 unsigned int virq, unsigned int nr_irqs) 451 { 452 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 453 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 454 455 mutex_lock(&port->lock); 456 457 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 458 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 459 d->hwirq); 460 else 461 __clear_bit(d->hwirq, port->msi_irq_in_use); 462 463 mutex_unlock(&port->lock); 464 465 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 466 } 467 468 static const struct irq_domain_ops msi_domain_ops = { 469 .alloc = mtk_pcie_irq_domain_alloc, 470 .free = mtk_pcie_irq_domain_free, 471 }; 472 473 static struct irq_chip mtk_msi_irq_chip = { 474 .name = "MTK PCIe MSI", 475 .irq_ack = irq_chip_ack_parent, 476 .irq_mask = pci_msi_mask_irq, 477 .irq_unmask = pci_msi_unmask_irq, 478 }; 479 480 static struct msi_domain_info mtk_msi_domain_info = { 481 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 482 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX, 483 .chip = &mtk_msi_irq_chip, 484 }; 485 486 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 487 { 488 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); 489 490 mutex_init(&port->lock); 491 492 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, 493 &msi_domain_ops, port); 494 if (!port->inner_domain) { 495 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 496 return -ENOMEM; 497 } 498 499 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, 500 port->inner_domain); 501 if (!port->msi_domain) { 502 dev_err(port->pcie->dev, "failed to create MSI domain\n"); 503 irq_domain_remove(port->inner_domain); 504 return -ENOMEM; 505 } 506 507 return 0; 508 } 509 510 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 511 { 512 u32 val; 513 phys_addr_t msg_addr; 514 515 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 516 val = lower_32_bits(msg_addr); 517 writel(val, port->base + PCIE_IMSI_ADDR); 518 519 val = readl(port->base + PCIE_INT_MASK); 520 val &= ~MSI_MASK; 521 writel(val, port->base + PCIE_INT_MASK); 522 } 523 524 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 525 { 526 struct mtk_pcie_port *port, *tmp; 527 528 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 529 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 530 531 if (port->irq_domain) 532 irq_domain_remove(port->irq_domain); 533 534 if (IS_ENABLED(CONFIG_PCI_MSI)) { 535 if (port->msi_domain) 536 irq_domain_remove(port->msi_domain); 537 if (port->inner_domain) 538 irq_domain_remove(port->inner_domain); 539 } 540 541 irq_dispose_mapping(port->irq); 542 } 543 } 544 545 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 546 irq_hw_number_t hwirq) 547 { 548 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 549 irq_set_chip_data(irq, domain->host_data); 550 551 return 0; 552 } 553 554 static const struct irq_domain_ops intx_domain_ops = { 555 .map = mtk_pcie_intx_map, 556 }; 557 558 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 559 struct device_node *node) 560 { 561 struct device *dev = port->pcie->dev; 562 struct device_node *pcie_intc_node; 563 int ret; 564 565 /* Setup INTx */ 566 pcie_intc_node = of_get_next_child(node, NULL); 567 if (!pcie_intc_node) { 568 dev_err(dev, "no PCIe Intc node found\n"); 569 return -ENODEV; 570 } 571 572 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 573 &intx_domain_ops, port); 574 of_node_put(pcie_intc_node); 575 if (!port->irq_domain) { 576 dev_err(dev, "failed to get INTx IRQ domain\n"); 577 return -ENODEV; 578 } 579 580 if (IS_ENABLED(CONFIG_PCI_MSI)) { 581 ret = mtk_pcie_allocate_msi_domains(port); 582 if (ret) 583 return ret; 584 } 585 586 return 0; 587 } 588 589 static void mtk_pcie_intr_handler(struct irq_desc *desc) 590 { 591 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 592 struct irq_chip *irqchip = irq_desc_get_chip(desc); 593 unsigned long status; 594 u32 bit = INTX_SHIFT; 595 596 chained_irq_enter(irqchip, desc); 597 598 status = readl(port->base + PCIE_INT_STATUS); 599 if (status & INTX_MASK) { 600 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 601 /* Clear the INTx */ 602 writel(1 << bit, port->base + PCIE_INT_STATUS); 603 generic_handle_domain_irq(port->irq_domain, 604 bit - INTX_SHIFT); 605 } 606 } 607 608 if (IS_ENABLED(CONFIG_PCI_MSI)) { 609 if (status & MSI_STATUS){ 610 unsigned long imsi_status; 611 612 /* 613 * The interrupt status can be cleared even if the 614 * MSI status remains pending. As such, given the 615 * edge-triggered interrupt type, its status should 616 * be cleared before being dispatched to the 617 * handler of the underlying device. 618 */ 619 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 620 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 621 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) 622 generic_handle_domain_irq(port->inner_domain, bit); 623 } 624 } 625 } 626 627 chained_irq_exit(irqchip, desc); 628 } 629 630 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 631 struct device_node *node) 632 { 633 struct mtk_pcie *pcie = port->pcie; 634 struct device *dev = pcie->dev; 635 struct platform_device *pdev = to_platform_device(dev); 636 int err; 637 638 err = mtk_pcie_init_irq_domain(port, node); 639 if (err) { 640 dev_err(dev, "failed to init PCIe IRQ domain\n"); 641 return err; 642 } 643 644 if (of_property_present(dev->of_node, "interrupt-names")) 645 port->irq = platform_get_irq_byname(pdev, "pcie_irq"); 646 else 647 port->irq = platform_get_irq(pdev, port->slot); 648 649 if (port->irq < 0) 650 return port->irq; 651 652 irq_set_chained_handler_and_data(port->irq, 653 mtk_pcie_intr_handler, port); 654 655 return 0; 656 } 657 658 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 659 { 660 struct mtk_pcie *pcie = port->pcie; 661 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 662 struct resource *mem = NULL; 663 struct resource_entry *entry; 664 const struct mtk_pcie_soc *soc = port->pcie->soc; 665 u32 val; 666 int err; 667 668 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 669 if (entry) 670 mem = entry->res; 671 if (!mem) 672 return -EINVAL; 673 674 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 675 if (pcie->base) { 676 val = readl(pcie->base + PCIE_SYS_CFG_V2); 677 val |= PCIE_CSR_LTSSM_EN(port->slot) | 678 PCIE_CSR_ASPM_L1_EN(port->slot); 679 writel(val, pcie->base + PCIE_SYS_CFG_V2); 680 } else if (pcie->cfg) { 681 val = PCIE_CSR_LTSSM_EN(port->slot) | 682 PCIE_CSR_ASPM_L1_EN(port->slot); 683 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); 684 } 685 686 /* Assert all reset signals */ 687 writel(0, port->base + PCIE_RST_CTRL); 688 689 /* 690 * Enable PCIe link down reset, if link status changed from link up to 691 * link down, this will reset MAC control registers and configuration 692 * space. 693 */ 694 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 695 696 /* 697 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 698 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should 699 * be delayed 100ms (TPVPERL) for the power and clock to become stable. 700 */ 701 msleep(100); 702 703 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 704 val = readl(port->base + PCIE_RST_CTRL); 705 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 706 PCIE_MAC_SRSTB | PCIE_CRSTB; 707 writel(val, port->base + PCIE_RST_CTRL); 708 709 /* Set up vendor ID and class code */ 710 if (soc->need_fix_class_id) { 711 val = PCI_VENDOR_ID_MEDIATEK; 712 writew(val, port->base + PCIE_CONF_VEND_ID); 713 714 val = PCI_CLASS_BRIDGE_PCI; 715 writew(val, port->base + PCIE_CONF_CLASS_ID); 716 } 717 718 if (soc->need_fix_device_id) 719 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); 720 721 /* 100ms timeout value should be enough for Gen1/2 training */ 722 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 723 !!(val & PCIE_PORT_LINKUP_V2), 20, 724 100 * USEC_PER_MSEC); 725 if (err) 726 return -ETIMEDOUT; 727 728 /* Set INTx mask */ 729 val = readl(port->base + PCIE_INT_MASK); 730 val &= ~INTX_MASK; 731 writel(val, port->base + PCIE_INT_MASK); 732 733 if (IS_ENABLED(CONFIG_PCI_MSI)) 734 mtk_pcie_enable_msi(port); 735 736 /* Set AHB to PCIe translation windows */ 737 val = lower_32_bits(mem->start) | 738 AHB2PCIE_SIZE(fls(resource_size(mem))); 739 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 740 741 val = upper_32_bits(mem->start); 742 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 743 744 /* Set PCIe to AXI translation memory space.*/ 745 val = PCIE2AHB_SIZE | WIN_ENABLE; 746 writel(val, port->base + PCIE_AXI_WINDOW0); 747 748 return 0; 749 } 750 751 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 752 unsigned int devfn, int where) 753 { 754 struct mtk_pcie *pcie = bus->sysdata; 755 756 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 757 bus->number), pcie->base + PCIE_CFG_ADDR); 758 759 return pcie->base + PCIE_CFG_DATA + (where & 3); 760 } 761 762 static struct pci_ops mtk_pcie_ops = { 763 .map_bus = mtk_pcie_map_bus, 764 .read = pci_generic_config_read, 765 .write = pci_generic_config_write, 766 }; 767 768 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 769 { 770 struct mtk_pcie *pcie = port->pcie; 771 u32 func = PCI_FUNC(port->slot); 772 u32 slot = PCI_SLOT(port->slot << 3); 773 u32 val; 774 int err; 775 776 /* assert port PERST_N */ 777 val = readl(pcie->base + PCIE_SYS_CFG); 778 val |= PCIE_PORT_PERST(port->slot); 779 writel(val, pcie->base + PCIE_SYS_CFG); 780 781 /* de-assert port PERST_N */ 782 val = readl(pcie->base + PCIE_SYS_CFG); 783 val &= ~PCIE_PORT_PERST(port->slot); 784 writel(val, pcie->base + PCIE_SYS_CFG); 785 786 /* 100ms timeout value should be enough for Gen1/2 training */ 787 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 788 !!(val & PCIE_PORT_LINKUP), 20, 789 100 * USEC_PER_MSEC); 790 if (err) 791 return -ETIMEDOUT; 792 793 /* enable interrupt */ 794 val = readl(pcie->base + PCIE_INT_ENABLE); 795 val |= PCIE_PORT_INT_EN(port->slot); 796 writel(val, pcie->base + PCIE_INT_ENABLE); 797 798 /* map to all DDR region. We need to set it before cfg operation. */ 799 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 800 port->base + PCIE_BAR0_SETUP); 801 802 /* configure class code and revision ID */ 803 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 804 805 /* configure FC credit */ 806 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 807 pcie->base + PCIE_CFG_ADDR); 808 val = readl(pcie->base + PCIE_CFG_DATA); 809 val &= ~PCIE_FC_CREDIT_MASK; 810 val |= PCIE_FC_CREDIT_VAL(0x806c); 811 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 812 pcie->base + PCIE_CFG_ADDR); 813 writel(val, pcie->base + PCIE_CFG_DATA); 814 815 /* configure RC FTS number to 250 when it leaves L0s */ 816 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 817 pcie->base + PCIE_CFG_ADDR); 818 val = readl(pcie->base + PCIE_CFG_DATA); 819 val &= ~PCIE_FTS_NUM_MASK; 820 val |= PCIE_FTS_NUM_L0(0x50); 821 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 822 pcie->base + PCIE_CFG_ADDR); 823 writel(val, pcie->base + PCIE_CFG_DATA); 824 825 return 0; 826 } 827 828 static void mtk_pcie_enable_port(struct mtk_pcie_port *port) 829 { 830 struct mtk_pcie *pcie = port->pcie; 831 struct device *dev = pcie->dev; 832 int err; 833 834 err = clk_prepare_enable(port->sys_ck); 835 if (err) { 836 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 837 goto err_sys_clk; 838 } 839 840 err = clk_prepare_enable(port->ahb_ck); 841 if (err) { 842 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 843 goto err_ahb_clk; 844 } 845 846 err = clk_prepare_enable(port->aux_ck); 847 if (err) { 848 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 849 goto err_aux_clk; 850 } 851 852 err = clk_prepare_enable(port->axi_ck); 853 if (err) { 854 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 855 goto err_axi_clk; 856 } 857 858 err = clk_prepare_enable(port->obff_ck); 859 if (err) { 860 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 861 goto err_obff_clk; 862 } 863 864 err = clk_prepare_enable(port->pipe_ck); 865 if (err) { 866 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 867 goto err_pipe_clk; 868 } 869 870 reset_control_assert(port->reset); 871 reset_control_deassert(port->reset); 872 873 err = phy_init(port->phy); 874 if (err) { 875 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 876 goto err_phy_init; 877 } 878 879 err = phy_power_on(port->phy); 880 if (err) { 881 dev_err(dev, "failed to power on port%d phy\n", port->slot); 882 goto err_phy_on; 883 } 884 885 if (!pcie->soc->startup(port)) 886 return; 887 888 dev_info(dev, "Port%d link down\n", port->slot); 889 890 phy_power_off(port->phy); 891 err_phy_on: 892 phy_exit(port->phy); 893 err_phy_init: 894 clk_disable_unprepare(port->pipe_ck); 895 err_pipe_clk: 896 clk_disable_unprepare(port->obff_ck); 897 err_obff_clk: 898 clk_disable_unprepare(port->axi_ck); 899 err_axi_clk: 900 clk_disable_unprepare(port->aux_ck); 901 err_aux_clk: 902 clk_disable_unprepare(port->ahb_ck); 903 err_ahb_clk: 904 clk_disable_unprepare(port->sys_ck); 905 err_sys_clk: 906 mtk_pcie_port_free(port); 907 } 908 909 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 910 struct device_node *node, 911 int slot) 912 { 913 struct mtk_pcie_port *port; 914 struct device *dev = pcie->dev; 915 struct platform_device *pdev = to_platform_device(dev); 916 char name[10]; 917 int err; 918 919 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 920 if (!port) 921 return -ENOMEM; 922 923 snprintf(name, sizeof(name), "port%d", slot); 924 port->base = devm_platform_ioremap_resource_byname(pdev, name); 925 if (IS_ERR(port->base)) { 926 dev_err(dev, "failed to map port%d base\n", slot); 927 return PTR_ERR(port->base); 928 } 929 930 snprintf(name, sizeof(name), "sys_ck%d", slot); 931 port->sys_ck = devm_clk_get(dev, name); 932 if (IS_ERR(port->sys_ck)) { 933 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 934 return PTR_ERR(port->sys_ck); 935 } 936 937 /* sys_ck might be divided into the following parts in some chips */ 938 snprintf(name, sizeof(name), "ahb_ck%d", slot); 939 port->ahb_ck = devm_clk_get_optional(dev, name); 940 if (IS_ERR(port->ahb_ck)) 941 return PTR_ERR(port->ahb_ck); 942 943 snprintf(name, sizeof(name), "axi_ck%d", slot); 944 port->axi_ck = devm_clk_get_optional(dev, name); 945 if (IS_ERR(port->axi_ck)) 946 return PTR_ERR(port->axi_ck); 947 948 snprintf(name, sizeof(name), "aux_ck%d", slot); 949 port->aux_ck = devm_clk_get_optional(dev, name); 950 if (IS_ERR(port->aux_ck)) 951 return PTR_ERR(port->aux_ck); 952 953 snprintf(name, sizeof(name), "obff_ck%d", slot); 954 port->obff_ck = devm_clk_get_optional(dev, name); 955 if (IS_ERR(port->obff_ck)) 956 return PTR_ERR(port->obff_ck); 957 958 snprintf(name, sizeof(name), "pipe_ck%d", slot); 959 port->pipe_ck = devm_clk_get_optional(dev, name); 960 if (IS_ERR(port->pipe_ck)) 961 return PTR_ERR(port->pipe_ck); 962 963 snprintf(name, sizeof(name), "pcie-rst%d", slot); 964 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 965 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 966 return PTR_ERR(port->reset); 967 968 /* some platforms may use default PHY setting */ 969 snprintf(name, sizeof(name), "pcie-phy%d", slot); 970 port->phy = devm_phy_optional_get(dev, name); 971 if (IS_ERR(port->phy)) 972 return PTR_ERR(port->phy); 973 974 port->slot = slot; 975 port->pcie = pcie; 976 977 if (pcie->soc->setup_irq) { 978 err = pcie->soc->setup_irq(port, node); 979 if (err) 980 return err; 981 } 982 983 INIT_LIST_HEAD(&port->list); 984 list_add_tail(&port->list, &pcie->ports); 985 986 return 0; 987 } 988 989 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 990 { 991 struct device *dev = pcie->dev; 992 struct platform_device *pdev = to_platform_device(dev); 993 struct resource *regs; 994 struct device_node *cfg_node; 995 int err; 996 997 /* get shared registers, which are optional */ 998 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 999 if (regs) { 1000 pcie->base = devm_ioremap_resource(dev, regs); 1001 if (IS_ERR(pcie->base)) 1002 return PTR_ERR(pcie->base); 1003 } 1004 1005 cfg_node = of_find_compatible_node(NULL, NULL, 1006 "mediatek,generic-pciecfg"); 1007 if (cfg_node) { 1008 pcie->cfg = syscon_node_to_regmap(cfg_node); 1009 of_node_put(cfg_node); 1010 if (IS_ERR(pcie->cfg)) 1011 return PTR_ERR(pcie->cfg); 1012 } 1013 1014 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1015 if (IS_ERR(pcie->free_ck)) { 1016 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1017 return -EPROBE_DEFER; 1018 1019 pcie->free_ck = NULL; 1020 } 1021 1022 pm_runtime_enable(dev); 1023 pm_runtime_get_sync(dev); 1024 1025 /* enable top level clock */ 1026 err = clk_prepare_enable(pcie->free_ck); 1027 if (err) { 1028 dev_err(dev, "failed to enable free_ck\n"); 1029 goto err_free_ck; 1030 } 1031 1032 return 0; 1033 1034 err_free_ck: 1035 pm_runtime_put_sync(dev); 1036 pm_runtime_disable(dev); 1037 1038 return err; 1039 } 1040 1041 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1042 { 1043 struct device *dev = pcie->dev; 1044 struct device_node *node = dev->of_node, *child; 1045 struct mtk_pcie_port *port, *tmp; 1046 int err, slot; 1047 1048 slot = of_get_pci_domain_nr(dev->of_node); 1049 if (slot < 0) { 1050 for_each_available_child_of_node(node, child) { 1051 err = of_pci_get_devfn(child); 1052 if (err < 0) { 1053 dev_err(dev, "failed to get devfn: %d\n", err); 1054 goto error_put_node; 1055 } 1056 1057 slot = PCI_SLOT(err); 1058 1059 err = mtk_pcie_parse_port(pcie, child, slot); 1060 if (err) 1061 goto error_put_node; 1062 } 1063 } else { 1064 err = mtk_pcie_parse_port(pcie, node, slot); 1065 if (err) 1066 return err; 1067 } 1068 1069 err = mtk_pcie_subsys_powerup(pcie); 1070 if (err) 1071 return err; 1072 1073 /* enable each port, and then check link status */ 1074 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1075 mtk_pcie_enable_port(port); 1076 1077 /* power down PCIe subsys if slots are all empty (link down) */ 1078 if (list_empty(&pcie->ports)) 1079 mtk_pcie_subsys_powerdown(pcie); 1080 1081 return 0; 1082 error_put_node: 1083 of_node_put(child); 1084 return err; 1085 } 1086 1087 static int mtk_pcie_probe(struct platform_device *pdev) 1088 { 1089 struct device *dev = &pdev->dev; 1090 struct mtk_pcie *pcie; 1091 struct pci_host_bridge *host; 1092 int err; 1093 1094 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1095 if (!host) 1096 return -ENOMEM; 1097 1098 pcie = pci_host_bridge_priv(host); 1099 1100 pcie->dev = dev; 1101 pcie->soc = of_device_get_match_data(dev); 1102 platform_set_drvdata(pdev, pcie); 1103 INIT_LIST_HEAD(&pcie->ports); 1104 1105 err = mtk_pcie_setup(pcie); 1106 if (err) 1107 return err; 1108 1109 host->ops = pcie->soc->ops; 1110 host->sysdata = pcie; 1111 host->msi_domain = pcie->soc->no_msi; 1112 1113 err = pci_host_probe(host); 1114 if (err) 1115 goto put_resources; 1116 1117 return 0; 1118 1119 put_resources: 1120 if (!list_empty(&pcie->ports)) 1121 mtk_pcie_put_resources(pcie); 1122 1123 return err; 1124 } 1125 1126 1127 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1128 { 1129 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1130 struct list_head *windows = &host->windows; 1131 1132 pci_free_resource_list(windows); 1133 } 1134 1135 static void mtk_pcie_remove(struct platform_device *pdev) 1136 { 1137 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1138 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1139 1140 pci_stop_root_bus(host->bus); 1141 pci_remove_root_bus(host->bus); 1142 mtk_pcie_free_resources(pcie); 1143 1144 mtk_pcie_irq_teardown(pcie); 1145 1146 mtk_pcie_put_resources(pcie); 1147 } 1148 1149 static int mtk_pcie_suspend_noirq(struct device *dev) 1150 { 1151 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1152 struct mtk_pcie_port *port; 1153 1154 if (list_empty(&pcie->ports)) 1155 return 0; 1156 1157 list_for_each_entry(port, &pcie->ports, list) { 1158 clk_disable_unprepare(port->pipe_ck); 1159 clk_disable_unprepare(port->obff_ck); 1160 clk_disable_unprepare(port->axi_ck); 1161 clk_disable_unprepare(port->aux_ck); 1162 clk_disable_unprepare(port->ahb_ck); 1163 clk_disable_unprepare(port->sys_ck); 1164 phy_power_off(port->phy); 1165 phy_exit(port->phy); 1166 } 1167 1168 clk_disable_unprepare(pcie->free_ck); 1169 1170 return 0; 1171 } 1172 1173 static int mtk_pcie_resume_noirq(struct device *dev) 1174 { 1175 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1176 struct mtk_pcie_port *port, *tmp; 1177 1178 if (list_empty(&pcie->ports)) 1179 return 0; 1180 1181 clk_prepare_enable(pcie->free_ck); 1182 1183 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1184 mtk_pcie_enable_port(port); 1185 1186 /* In case of EP was removed while system suspend. */ 1187 if (list_empty(&pcie->ports)) 1188 clk_disable_unprepare(pcie->free_ck); 1189 1190 return 0; 1191 } 1192 1193 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1194 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1195 mtk_pcie_resume_noirq) 1196 }; 1197 1198 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1199 .no_msi = true, 1200 .ops = &mtk_pcie_ops, 1201 .startup = mtk_pcie_startup_port, 1202 }; 1203 1204 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1205 .ops = &mtk_pcie_ops_v2, 1206 .startup = mtk_pcie_startup_port_v2, 1207 .setup_irq = mtk_pcie_setup_irq, 1208 }; 1209 1210 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1211 .need_fix_class_id = true, 1212 .ops = &mtk_pcie_ops_v2, 1213 .startup = mtk_pcie_startup_port_v2, 1214 .setup_irq = mtk_pcie_setup_irq, 1215 }; 1216 1217 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { 1218 .need_fix_class_id = true, 1219 .need_fix_device_id = true, 1220 .device_id = PCI_DEVICE_ID_MEDIATEK_7629, 1221 .ops = &mtk_pcie_ops_v2, 1222 .startup = mtk_pcie_startup_port_v2, 1223 .setup_irq = mtk_pcie_setup_irq, 1224 }; 1225 1226 static const struct of_device_id mtk_pcie_ids[] = { 1227 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1228 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1229 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1230 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1231 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, 1232 {}, 1233 }; 1234 MODULE_DEVICE_TABLE(of, mtk_pcie_ids); 1235 1236 static struct platform_driver mtk_pcie_driver = { 1237 .probe = mtk_pcie_probe, 1238 .remove_new = mtk_pcie_remove, 1239 .driver = { 1240 .name = "mtk-pcie", 1241 .of_match_table = mtk_pcie_ids, 1242 .suppress_bind_attrs = true, 1243 .pm = &mtk_pcie_pm_ops, 1244 }, 1245 }; 1246 module_platform_driver(mtk_pcie_driver); 1247 MODULE_DESCRIPTION("MediaTek PCIe host controller driver"); 1248 MODULE_LICENSE("GPL v2"); 1249