1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/errno.h> 14 #include <linux/iopoll.h> 15 #include <linux/irq.h> 16 #include <linux/irqchip/chained_irq.h> 17 #include <linux/irqchip/irq-msi-lib.h> 18 #include <linux/irqdomain.h> 19 #include <linux/kconfig.h> 20 #include <linux/kernel.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/msi.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of_pci.h> 26 #include <linux/of_platform.h> 27 #include <linux/pci.h> 28 #include <linux/phy/phy.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/regmap.h> 32 #include <linux/reset.h> 33 34 #include "../pci.h" 35 36 /* PCIe shared registers */ 37 #define PCIE_SYS_CFG 0x00 38 #define PCIE_INT_ENABLE 0x0c 39 #define PCIE_CFG_ADDR 0x20 40 #define PCIE_CFG_DATA 0x24 41 42 /* PCIe per port registers */ 43 #define PCIE_BAR0_SETUP 0x10 44 #define PCIE_CLASS 0x34 45 #define PCIE_LINK_STATUS 0x50 46 47 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 48 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 49 #define PCIE_PORT_LINKUP BIT(0) 50 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 51 52 #define PCIE_BAR_ENABLE BIT(0) 53 #define PCIE_REVISION_ID BIT(0) 54 #define PCIE_CLASS_CODE (0x60400 << 8) 55 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 56 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 57 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 58 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 59 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 60 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 61 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 62 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 63 64 /* MediaTek specific configuration registers */ 65 #define PCIE_FTS_NUM 0x70c 66 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 67 #define PCIE_FTS_NUM_L0(x) FIELD_PREP(PCIE_FTS_NUM_MASK, x) 68 69 #define PCIE_FC_CREDIT 0x73c 70 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 71 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 72 73 /* PCIe V2 share registers */ 74 #define PCIE_SYS_CFG_V2 0x0 75 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 76 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 77 78 /* PCIe V2 per-port registers */ 79 #define PCIE_MSI_VECTOR 0x0c0 80 81 #define PCIE_CONF_VEND_ID 0x100 82 #define PCIE_CONF_DEVICE_ID 0x102 83 #define PCIE_CONF_REV_CLASS 0x104 84 #define PCIE_CONF_CLASS_ID 0x106 85 86 #define PCIE_INT_MASK 0x420 87 #define INTX_MASK GENMASK(19, 16) 88 #define INTX_SHIFT 16 89 #define PCIE_INT_STATUS 0x424 90 #define MSI_STATUS BIT(23) 91 #define PCIE_IMSI_STATUS 0x42c 92 #define PCIE_IMSI_ADDR 0x430 93 #define MSI_MASK BIT(23) 94 #define MTK_MSI_IRQS_NUM 32 95 96 #define EN7528_HOST_MODE 0x00804201 97 #define EN7528_LINKUP_REG 0x50 98 #define EN7528_RC0_LINKUP BIT(1) 99 #define EN7528_RC1_LINKUP BIT(2) 100 101 #define PCIE_AHB_TRANS_BASE0_L 0x438 102 #define PCIE_AHB_TRANS_BASE0_H 0x43c 103 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 104 #define PCIE_AXI_WINDOW0 0x448 105 #define WIN_ENABLE BIT(7) 106 /* 107 * Define PCIe to AHB window size as 2^33 to support max 8GB address space 108 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM 109 * start from 0x40000000). 110 */ 111 #define PCIE2AHB_SIZE 0x21 112 113 /* PCIe V2 configuration transaction header */ 114 #define PCIE_CFG_HEADER0 0x460 115 #define PCIE_CFG_HEADER1 0x464 116 #define PCIE_CFG_HEADER2 0x468 117 #define PCIE_CFG_WDATA 0x470 118 #define PCIE_APP_TLP_REQ 0x488 119 #define PCIE_CFG_RDATA 0x48c 120 #define APP_CFG_REQ BIT(0) 121 #define APP_CPL_STATUS GENMASK(7, 5) 122 123 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 124 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 125 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 126 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 127 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 128 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 129 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 130 #define CFG_HEADER_DW0(type, fmt) \ 131 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 132 #define CFG_HEADER_DW1(where, size) \ 133 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 134 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 135 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 136 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 137 138 #define PCIE_RST_CTRL 0x510 139 #define PCIE_PHY_RSTB BIT(0) 140 #define PCIE_PIPE_SRSTB BIT(1) 141 #define PCIE_MAC_SRSTB BIT(2) 142 #define PCIE_CRSTB BIT(3) 143 #define PCIE_PERSTB BIT(8) 144 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 145 #define PCIE_LINK_STATUS_V2 0x804 146 #define PCIE_PORT_LINKUP_V2 BIT(10) 147 148 struct mtk_pcie_port; 149 150 /** 151 * enum mtk_pcie_quirks - MTK PCIe quirks 152 * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed 153 * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed 154 * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block 155 * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe 156 * @MTK_PCIE_RETRAIN: Retrain link to bridge after startup because some 157 * Gen2-capable devices start as Gen1. 158 */ 159 enum mtk_pcie_quirks { 160 MTK_PCIE_FIX_CLASS_ID = BIT(0), 161 MTK_PCIE_FIX_DEVICE_ID = BIT(1), 162 MTK_PCIE_NO_MSI = BIT(2), 163 MTK_PCIE_SKIP_RSTB = BIT(3), 164 MTK_PCIE_RETRAIN = BIT(4), 165 }; 166 167 /** 168 * struct mtk_pcie_soc - differentiate between host generations 169 * @device_id: device ID which this host need to be fixed 170 * @ops: pointer to configuration access functions 171 * @startup: pointer to controller setting functions 172 * @setup_irq: pointer to initialize IRQ functions 173 * @quirks: PCIe device quirks. 174 */ 175 struct mtk_pcie_soc { 176 unsigned int device_id; 177 struct pci_ops *ops; 178 int (*startup)(struct mtk_pcie_port *port); 179 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 180 enum mtk_pcie_quirks quirks; 181 }; 182 183 /** 184 * struct mtk_pcie_port - PCIe port information 185 * @base: IO mapped register base 186 * @phys_base: Physical address of the I/O register base region 187 * @list: port list 188 * @pcie: pointer to PCIe host info 189 * @reset: pointer to port reset control 190 * @sys_ck: pointer to transaction/data link layer clock 191 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 192 * and RC initiated MMIO access 193 * @axi_ck: pointer to application layer MMIO channel operating clock 194 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 195 * when pcie_mac_ck/pcie_pipe_ck is turned off 196 * @obff_ck: pointer to OBFF functional block operating clock 197 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 198 * @phy: pointer to PHY control block 199 * @slot: port slot 200 * @irq: GIC irq 201 * @irq_domain: legacy INTx IRQ domain 202 * @inner_domain: inner IRQ domain 203 * @lock: protect the msi_irq_in_use bitmap 204 * @msi_irq_in_use: bit map for assigned MSI IRQ 205 */ 206 struct mtk_pcie_port { 207 void __iomem *base; 208 phys_addr_t phys_base; 209 struct list_head list; 210 struct mtk_pcie *pcie; 211 struct reset_control *reset; 212 struct clk *sys_ck; 213 struct clk *ahb_ck; 214 struct clk *axi_ck; 215 struct clk *aux_ck; 216 struct clk *obff_ck; 217 struct clk *pipe_ck; 218 struct phy *phy; 219 u32 slot; 220 int irq; 221 struct irq_domain *irq_domain; 222 struct irq_domain *inner_domain; 223 struct mutex lock; 224 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 225 }; 226 227 /** 228 * struct mtk_pcie - PCIe host information 229 * @dev: pointer to PCIe device 230 * @base: IO mapped register base 231 * @cfg: IO mapped register map for PCIe config 232 * @free_ck: free-run reference clock 233 * @ports: pointer to PCIe port information 234 * @soc: pointer to SoC-dependent operations 235 */ 236 struct mtk_pcie { 237 struct device *dev; 238 void __iomem *base; 239 struct regmap *cfg; 240 struct clk *free_ck; 241 242 struct list_head ports; 243 const struct mtk_pcie_soc *soc; 244 }; 245 246 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 247 { 248 struct device *dev = pcie->dev; 249 250 clk_disable_unprepare(pcie->free_ck); 251 252 pm_runtime_put_sync(dev); 253 pm_runtime_disable(dev); 254 } 255 256 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 257 { 258 struct mtk_pcie *pcie = port->pcie; 259 struct device *dev = pcie->dev; 260 261 devm_iounmap(dev, port->base); 262 list_del(&port->list); 263 devm_kfree(dev, port); 264 } 265 266 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 267 { 268 struct mtk_pcie_port *port, *tmp; 269 270 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 271 phy_power_off(port->phy); 272 phy_exit(port->phy); 273 clk_disable_unprepare(port->pipe_ck); 274 clk_disable_unprepare(port->obff_ck); 275 clk_disable_unprepare(port->axi_ck); 276 clk_disable_unprepare(port->aux_ck); 277 clk_disable_unprepare(port->ahb_ck); 278 clk_disable_unprepare(port->sys_ck); 279 mtk_pcie_port_free(port); 280 } 281 282 mtk_pcie_subsys_powerdown(pcie); 283 } 284 285 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 286 { 287 u32 val; 288 int err; 289 290 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 291 !(val & APP_CFG_REQ), 10, 292 100 * USEC_PER_MSEC); 293 if (err) 294 return PCIBIOS_SET_FAILED; 295 296 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 297 return PCIBIOS_SET_FAILED; 298 299 return PCIBIOS_SUCCESSFUL; 300 } 301 302 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 303 int where, int size, u32 *val) 304 { 305 u32 tmp; 306 307 /* Write PCIe configuration transaction header for Cfgrd */ 308 writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_NO_DATA), 309 port->base + PCIE_CFG_HEADER0); 310 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 311 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 312 port->base + PCIE_CFG_HEADER2); 313 314 /* Trigger h/w to transmit Cfgrd TLP */ 315 tmp = readl(port->base + PCIE_APP_TLP_REQ); 316 tmp |= APP_CFG_REQ; 317 writel(tmp, port->base + PCIE_APP_TLP_REQ); 318 319 /* Check completion status */ 320 if (mtk_pcie_check_cfg_cpld(port)) 321 return PCIBIOS_SET_FAILED; 322 323 /* Read cpld payload of Cfgrd */ 324 *val = readl(port->base + PCIE_CFG_RDATA); 325 326 if (size == 1) 327 *val = (*val >> (8 * (where & 3))) & 0xff; 328 else if (size == 2) 329 *val = (*val >> (8 * (where & 3))) & 0xffff; 330 331 return PCIBIOS_SUCCESSFUL; 332 } 333 334 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 335 int where, int size, u32 val) 336 { 337 /* Write PCIe configuration transaction header for Cfgwr */ 338 writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_DATA), 339 port->base + PCIE_CFG_HEADER0); 340 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 341 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 342 port->base + PCIE_CFG_HEADER2); 343 344 /* Write Cfgwr data */ 345 val = val << 8 * (where & 3); 346 writel(val, port->base + PCIE_CFG_WDATA); 347 348 /* Trigger h/w to transmit Cfgwr TLP */ 349 val = readl(port->base + PCIE_APP_TLP_REQ); 350 val |= APP_CFG_REQ; 351 writel(val, port->base + PCIE_APP_TLP_REQ); 352 353 /* Check completion status */ 354 return mtk_pcie_check_cfg_cpld(port); 355 } 356 357 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 358 unsigned int devfn) 359 { 360 struct mtk_pcie *pcie = bus->sysdata; 361 struct mtk_pcie_port *port; 362 struct pci_dev *dev = NULL; 363 364 /* 365 * Walk the bus hierarchy to get the devfn value 366 * of the port in the root bus. 367 */ 368 while (bus && bus->number) { 369 dev = bus->self; 370 bus = dev->bus; 371 devfn = dev->devfn; 372 } 373 374 list_for_each_entry(port, &pcie->ports, list) 375 if (port->slot == PCI_SLOT(devfn)) 376 return port; 377 378 return NULL; 379 } 380 381 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 382 int where, int size, u32 *val) 383 { 384 struct mtk_pcie_port *port; 385 u32 bn = bus->number; 386 387 port = mtk_pcie_find_port(bus, devfn); 388 if (!port) 389 return PCIBIOS_DEVICE_NOT_FOUND; 390 391 return mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 392 } 393 394 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 395 int where, int size, u32 val) 396 { 397 struct mtk_pcie_port *port; 398 u32 bn = bus->number; 399 400 port = mtk_pcie_find_port(bus, devfn); 401 if (!port) 402 return PCIBIOS_DEVICE_NOT_FOUND; 403 404 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 405 } 406 407 static struct pci_ops mtk_pcie_ops_v2 = { 408 .read = mtk_pcie_config_read, 409 .write = mtk_pcie_config_write, 410 }; 411 412 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 413 { 414 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 415 phys_addr_t addr; 416 417 /* MT2712/MT7622 only support 32-bit MSI addresses */ 418 addr = port->phys_base + PCIE_MSI_VECTOR; 419 msg->address_hi = 0; 420 msg->address_lo = lower_32_bits(addr); 421 422 msg->data = data->hwirq; 423 424 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 425 (int)data->hwirq, msg->address_hi, msg->address_lo); 426 } 427 428 static void mtk_msi_ack_irq(struct irq_data *data) 429 { 430 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 431 u32 hwirq = data->hwirq; 432 433 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 434 } 435 436 static struct irq_chip mtk_msi_bottom_irq_chip = { 437 .name = "MTK MSI", 438 .irq_compose_msi_msg = mtk_compose_msi_msg, 439 .irq_ack = mtk_msi_ack_irq, 440 }; 441 442 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 443 unsigned int nr_irqs, void *args) 444 { 445 struct mtk_pcie_port *port = domain->host_data; 446 unsigned long bit; 447 448 WARN_ON(nr_irqs != 1); 449 mutex_lock(&port->lock); 450 451 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 452 if (bit >= MTK_MSI_IRQS_NUM) { 453 mutex_unlock(&port->lock); 454 return -ENOSPC; 455 } 456 457 __set_bit(bit, port->msi_irq_in_use); 458 459 mutex_unlock(&port->lock); 460 461 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 462 domain->host_data, handle_edge_irq, 463 NULL, NULL); 464 465 return 0; 466 } 467 468 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 469 unsigned int virq, unsigned int nr_irqs) 470 { 471 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 472 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 473 474 mutex_lock(&port->lock); 475 476 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 477 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 478 d->hwirq); 479 else 480 __clear_bit(d->hwirq, port->msi_irq_in_use); 481 482 mutex_unlock(&port->lock); 483 484 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 485 } 486 487 static const struct irq_domain_ops msi_domain_ops = { 488 .alloc = mtk_pcie_irq_domain_alloc, 489 .free = mtk_pcie_irq_domain_free, 490 }; 491 492 #define MTK_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 493 MSI_FLAG_USE_DEF_CHIP_OPS | \ 494 MSI_FLAG_NO_AFFINITY) 495 496 #define MTK_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 497 MSI_FLAG_PCI_MSIX) 498 499 static const struct msi_parent_ops mtk_msi_parent_ops = { 500 .required_flags = MTK_MSI_FLAGS_REQUIRED, 501 .supported_flags = MTK_MSI_FLAGS_SUPPORTED, 502 .bus_select_token = DOMAIN_BUS_PCI_MSI, 503 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 504 .prefix = "MTK-", 505 .init_dev_msi_info = msi_lib_init_dev_msi_info, 506 }; 507 508 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 509 { 510 mutex_init(&port->lock); 511 512 struct irq_domain_info info = { 513 .fwnode = dev_fwnode(port->pcie->dev), 514 .ops = &msi_domain_ops, 515 .host_data = port, 516 .size = MTK_MSI_IRQS_NUM, 517 }; 518 519 port->inner_domain = msi_create_parent_irq_domain(&info, &mtk_msi_parent_ops); 520 if (!port->inner_domain) { 521 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 522 return -ENOMEM; 523 } 524 525 return 0; 526 } 527 528 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 529 { 530 u32 val; 531 phys_addr_t msg_addr; 532 533 msg_addr = port->phys_base + PCIE_MSI_VECTOR; 534 val = lower_32_bits(msg_addr); 535 writel(val, port->base + PCIE_IMSI_ADDR); 536 537 val = readl(port->base + PCIE_INT_MASK); 538 val &= ~MSI_MASK; 539 writel(val, port->base + PCIE_INT_MASK); 540 } 541 542 static void mtk_pcie_irq_teardown_port(struct mtk_pcie_port *port) 543 { 544 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 545 546 if (port->irq_domain) 547 irq_domain_remove(port->irq_domain); 548 549 if (IS_ENABLED(CONFIG_PCI_MSI)) { 550 if (port->inner_domain) 551 irq_domain_remove(port->inner_domain); 552 } 553 554 irq_dispose_mapping(port->irq); 555 } 556 557 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 558 { 559 struct mtk_pcie_port *port, *tmp; 560 561 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 562 mtk_pcie_irq_teardown_port(port); 563 } 564 565 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 566 irq_hw_number_t hwirq) 567 { 568 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 569 irq_set_chip_data(irq, domain->host_data); 570 571 return 0; 572 } 573 574 static const struct irq_domain_ops intx_domain_ops = { 575 .map = mtk_pcie_intx_map, 576 }; 577 578 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 579 struct device_node *node) 580 { 581 struct device *dev = port->pcie->dev; 582 struct device_node *pcie_intc_node; 583 int ret; 584 585 /* Setup INTx */ 586 pcie_intc_node = of_get_next_child(node, NULL); 587 if (!pcie_intc_node) { 588 dev_err(dev, "no PCIe Intc node found\n"); 589 return -ENODEV; 590 } 591 592 port->irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), PCI_NUM_INTX, 593 &intx_domain_ops, port); 594 of_node_put(pcie_intc_node); 595 if (!port->irq_domain) { 596 dev_err(dev, "failed to get INTx IRQ domain\n"); 597 return -ENODEV; 598 } 599 600 if (IS_ENABLED(CONFIG_PCI_MSI)) { 601 ret = mtk_pcie_allocate_msi_domains(port); 602 if (ret) { 603 irq_domain_remove(port->irq_domain); 604 return ret; 605 } 606 } 607 608 return 0; 609 } 610 611 static void mtk_pcie_intr_handler(struct irq_desc *desc) 612 { 613 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 614 struct irq_chip *irqchip = irq_desc_get_chip(desc); 615 unsigned long status; 616 u32 bit = INTX_SHIFT; 617 618 chained_irq_enter(irqchip, desc); 619 620 status = readl(port->base + PCIE_INT_STATUS); 621 if (status & INTX_MASK) { 622 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 623 /* Clear the INTx */ 624 writel(1 << bit, port->base + PCIE_INT_STATUS); 625 generic_handle_domain_irq(port->irq_domain, 626 bit - INTX_SHIFT); 627 } 628 } 629 630 if (IS_ENABLED(CONFIG_PCI_MSI)) { 631 if (status & MSI_STATUS){ 632 unsigned long imsi_status; 633 634 /* 635 * The interrupt status can be cleared even if the 636 * MSI status remains pending. As such, given the 637 * edge-triggered interrupt type, its status should 638 * be cleared before being dispatched to the 639 * handler of the underlying device. 640 */ 641 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 642 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 643 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) 644 generic_handle_domain_irq(port->inner_domain, bit); 645 } 646 } 647 } 648 649 chained_irq_exit(irqchip, desc); 650 } 651 652 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 653 struct device_node *node) 654 { 655 struct mtk_pcie *pcie = port->pcie; 656 struct device *dev = pcie->dev; 657 struct platform_device *pdev = to_platform_device(dev); 658 int err; 659 660 err = mtk_pcie_init_irq_domain(port, node); 661 if (err) { 662 dev_err(dev, "failed to init PCIe IRQ domain\n"); 663 return err; 664 } 665 666 if (of_property_present(dev->of_node, "interrupt-names")) 667 port->irq = platform_get_irq_byname(pdev, "pcie_irq"); 668 else 669 port->irq = platform_get_irq(pdev, port->slot); 670 671 if (port->irq < 0) 672 return port->irq; 673 674 irq_set_chained_handler_and_data(port->irq, 675 mtk_pcie_intr_handler, port); 676 677 return 0; 678 } 679 680 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 681 { 682 struct mtk_pcie *pcie = port->pcie; 683 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 684 struct resource *mem = NULL; 685 struct resource_entry *entry; 686 const struct mtk_pcie_soc *soc = port->pcie->soc; 687 u32 val; 688 int err; 689 690 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 691 if (entry) 692 mem = entry->res; 693 if (!mem) 694 return -EINVAL; 695 696 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 697 if (pcie->base) { 698 val = readl(pcie->base + PCIE_SYS_CFG_V2); 699 val |= PCIE_CSR_LTSSM_EN(port->slot) | 700 PCIE_CSR_ASPM_L1_EN(port->slot); 701 writel(val, pcie->base + PCIE_SYS_CFG_V2); 702 } else if (pcie->cfg) { 703 val = PCIE_CSR_LTSSM_EN(port->slot) | 704 PCIE_CSR_ASPM_L1_EN(port->slot); 705 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); 706 } 707 708 if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) { 709 /* Assert all reset signals */ 710 writel(0, port->base + PCIE_RST_CTRL); 711 712 /* 713 * Enable PCIe link down reset, if link status changed from 714 * link up to link down, this will reset MAC control registers 715 * and configuration space. 716 */ 717 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 718 719 msleep(PCIE_T_PVPERL_MS); 720 721 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 722 val = readl(port->base + PCIE_RST_CTRL); 723 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 724 PCIE_MAC_SRSTB | PCIE_CRSTB; 725 writel(val, port->base + PCIE_RST_CTRL); 726 } 727 728 /* Set up vendor ID and class code */ 729 if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) { 730 val = PCI_VENDOR_ID_MEDIATEK; 731 writew(val, port->base + PCIE_CONF_VEND_ID); 732 733 val = PCI_CLASS_BRIDGE_PCI; 734 writew(val, port->base + PCIE_CONF_CLASS_ID); 735 } 736 737 if (soc->quirks & MTK_PCIE_FIX_DEVICE_ID) 738 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); 739 740 /* 100ms timeout value should be enough for Gen1/2 training */ 741 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 742 !!(val & PCIE_PORT_LINKUP_V2), 20, 743 100 * USEC_PER_MSEC); 744 if (err) 745 return -ETIMEDOUT; 746 747 /* Set INTx mask */ 748 val = readl(port->base + PCIE_INT_MASK); 749 val &= ~INTX_MASK; 750 writel(val, port->base + PCIE_INT_MASK); 751 752 if (IS_ENABLED(CONFIG_PCI_MSI)) 753 mtk_pcie_enable_msi(port); 754 755 /* Set AHB to PCIe translation windows */ 756 val = lower_32_bits(mem->start) | 757 AHB2PCIE_SIZE(fls(resource_size(mem))); 758 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 759 760 val = upper_32_bits(mem->start); 761 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 762 763 /* Set PCIe to AXI translation memory space.*/ 764 val = PCIE2AHB_SIZE | WIN_ENABLE; 765 writel(val, port->base + PCIE_AXI_WINDOW0); 766 767 return 0; 768 } 769 770 static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port) 771 { 772 struct mtk_pcie *pcie = port->pcie; 773 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 774 struct resource *mem = NULL; 775 struct resource_entry *entry; 776 u32 val, link_mask; 777 int err; 778 779 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 780 if (entry) 781 mem = entry->res; 782 if (!mem) 783 return -EINVAL; 784 785 if (!pcie->cfg) { 786 dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n"); 787 return -EINVAL; 788 } 789 790 /* Assert all reset signals */ 791 writel(0, port->base + PCIE_RST_CTRL); 792 793 /* 794 * Enable PCIe link down reset, if link status changed from link up to 795 * link down, this will reset MAC control registers and configuration 796 * space. 797 */ 798 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 799 800 msleep(PCIE_T_PVPERL_MS); 801 802 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 803 val = readl(port->base + PCIE_RST_CTRL); 804 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 805 PCIE_MAC_SRSTB | PCIE_CRSTB; 806 writel(val, port->base + PCIE_RST_CTRL); 807 808 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, 809 port->base + PCIE_CONF_REV_CLASS); 810 writel(EN7528_HOST_MODE, port->base); 811 812 link_mask = (port->slot == 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINKUP; 813 814 /* 100ms timeout value should be enough for Gen1/2 training */ 815 err = regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val, 816 !!(val & link_mask), 20, 817 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); 818 if (err) { 819 dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot); 820 return -ETIMEDOUT; 821 } 822 823 /* Activate INTx interrupts */ 824 val = readl(port->base + PCIE_INT_MASK); 825 val &= ~INTX_MASK; 826 writel(val, port->base + PCIE_INT_MASK); 827 828 if (IS_ENABLED(CONFIG_PCI_MSI)) 829 mtk_pcie_enable_msi(port); 830 831 /* Set AHB to PCIe translation windows */ 832 val = lower_32_bits(mem->start) | 833 AHB2PCIE_SIZE(fls(resource_size(mem))); 834 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 835 836 val = upper_32_bits(mem->start); 837 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 838 839 writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0); 840 841 if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK)) 842 dev_info(pcie->dev, 843 "module not built-in, Gen2 unavailable even if supported\n"); 844 845 return 0; 846 } 847 848 /** 849 * mtk_pcie_retrain - retrain the root bridge link if needed 850 * @dev: The device, for use in logging 851 * @host: The host bridge which contains the link 852 * 853 * Due to what is likely a hardware bug, some devices (notably EcoNet) start up 854 * as Gen1, and must be retrained once after initial configuration in order to 855 * reach Gen2. 856 * 857 * These devices always self-identify as Gen2 capable, but sometimes the PHY is 858 * only capable of Gen1 operation, and sometimes the PCIe card (e.g. wifi) is 859 * only Gen1 capable. Therefore it is most convenient to retrain every port 860 * after startup. 861 */ 862 static int mtk_pcie_retrain(struct device *dev, struct pci_host_bridge *host) 863 { 864 struct pci_dev *rp; 865 int ret = -ENOENT; 866 u16 lnksta = 0; 867 u32 speed; 868 869 /* Should already have been warned about during startup_port */ 870 if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK)) 871 return 0; 872 873 guard(rwsem_read)(&pci_bus_sem); 874 875 for_each_pci_bridge(rp, host->bus) { 876 if (pci_pcie_type(rp) != PCI_EXP_TYPE_ROOT_PORT) 877 continue; 878 879 #if IS_BUILTIN(CONFIG_PCIE_MEDIATEK) 880 ret = pcie_retrain_link(rp, true); 881 #endif 882 883 if (ret) 884 return dev_err_probe(&rp->dev, ret, 885 "failed to retrain port\n"); 886 887 pcie_capability_read_word(rp, PCI_EXP_LNKSTA, &lnksta); 888 speed = lnksta & PCI_EXP_LNKSTA_CLS; 889 890 pci_info(rp, "link retrained, speed %s\n", 891 pci_speed_string(pcie_link_speed[speed])); 892 893 } 894 895 return 0; 896 } 897 898 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 899 unsigned int devfn, int where) 900 { 901 struct mtk_pcie *pcie = bus->sysdata; 902 903 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 904 bus->number), pcie->base + PCIE_CFG_ADDR); 905 906 return pcie->base + PCIE_CFG_DATA + (where & 3); 907 } 908 909 static struct pci_ops mtk_pcie_ops = { 910 .map_bus = mtk_pcie_map_bus, 911 .read = pci_generic_config_read, 912 .write = pci_generic_config_write, 913 }; 914 915 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 916 { 917 struct mtk_pcie *pcie = port->pcie; 918 u32 func = PCI_FUNC(port->slot); 919 u32 slot = PCI_SLOT(port->slot << 3); 920 u32 val; 921 int err; 922 923 /* assert port PERST_N */ 924 val = readl(pcie->base + PCIE_SYS_CFG); 925 val |= PCIE_PORT_PERST(port->slot); 926 writel(val, pcie->base + PCIE_SYS_CFG); 927 928 /* de-assert port PERST_N */ 929 val = readl(pcie->base + PCIE_SYS_CFG); 930 val &= ~PCIE_PORT_PERST(port->slot); 931 writel(val, pcie->base + PCIE_SYS_CFG); 932 933 /* 100ms timeout value should be enough for Gen1/2 training */ 934 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 935 !!(val & PCIE_PORT_LINKUP), 20, 936 100 * USEC_PER_MSEC); 937 if (err) 938 return -ETIMEDOUT; 939 940 /* enable interrupt */ 941 val = readl(pcie->base + PCIE_INT_ENABLE); 942 val |= PCIE_PORT_INT_EN(port->slot); 943 writel(val, pcie->base + PCIE_INT_ENABLE); 944 945 /* map to all DDR region. We need to set it before cfg operation. */ 946 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 947 port->base + PCIE_BAR0_SETUP); 948 949 /* configure class code and revision ID */ 950 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 951 952 /* configure FC credit */ 953 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 954 pcie->base + PCIE_CFG_ADDR); 955 val = readl(pcie->base + PCIE_CFG_DATA); 956 val &= ~PCIE_FC_CREDIT_MASK; 957 val |= PCIE_FC_CREDIT_VAL(0x806c); 958 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 959 pcie->base + PCIE_CFG_ADDR); 960 writel(val, pcie->base + PCIE_CFG_DATA); 961 962 /* configure RC FTS number to 250 when it leaves L0s */ 963 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 964 pcie->base + PCIE_CFG_ADDR); 965 val = readl(pcie->base + PCIE_CFG_DATA); 966 val &= ~PCIE_FTS_NUM_MASK; 967 val |= PCIE_FTS_NUM_L0(0x50); 968 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 969 pcie->base + PCIE_CFG_ADDR); 970 writel(val, pcie->base + PCIE_CFG_DATA); 971 972 return 0; 973 } 974 975 static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port) 976 { 977 struct mtk_pcie *pcie = port->pcie; 978 struct device *dev = pcie->dev; 979 struct pci_host_bridge *host; 980 struct resource_entry *entry; 981 struct regmap *pbus_regmap; 982 resource_size_t addr; 983 u32 args[2], size; 984 985 /* 986 * Configure PBus base address and base address mask to allow 987 * the hw to detect if a given address is accessible on PCIe 988 * controller. 989 */ 990 pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 991 "mediatek,pbus-csr", 992 ARRAY_SIZE(args), 993 args); 994 if (IS_ERR(pbus_regmap)) 995 return PTR_ERR(pbus_regmap); 996 997 host = pci_host_bridge_from_priv(pcie); 998 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 999 if (!entry) 1000 return -ENODEV; 1001 1002 addr = entry->res->start - entry->offset; 1003 regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); 1004 size = lower_32_bits(resource_size(entry->res)); 1005 regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); 1006 1007 return mtk_pcie_startup_port_v2(port); 1008 } 1009 1010 static int mtk_pcie_enable_port(struct mtk_pcie_port *port) 1011 { 1012 struct mtk_pcie *pcie = port->pcie; 1013 struct device *dev = pcie->dev; 1014 int err; 1015 1016 err = clk_prepare_enable(port->sys_ck); 1017 if (err) { 1018 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 1019 return err; 1020 } 1021 1022 err = clk_prepare_enable(port->ahb_ck); 1023 if (err) { 1024 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 1025 goto err_ahb_clk; 1026 } 1027 1028 err = clk_prepare_enable(port->aux_ck); 1029 if (err) { 1030 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 1031 goto err_aux_clk; 1032 } 1033 1034 err = clk_prepare_enable(port->axi_ck); 1035 if (err) { 1036 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 1037 goto err_axi_clk; 1038 } 1039 1040 err = clk_prepare_enable(port->obff_ck); 1041 if (err) { 1042 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 1043 goto err_obff_clk; 1044 } 1045 1046 err = clk_prepare_enable(port->pipe_ck); 1047 if (err) { 1048 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 1049 goto err_pipe_clk; 1050 } 1051 1052 reset_control_assert(port->reset); 1053 reset_control_deassert(port->reset); 1054 1055 err = phy_init(port->phy); 1056 if (err) { 1057 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 1058 goto err_phy_init; 1059 } 1060 1061 err = phy_power_on(port->phy); 1062 if (err) { 1063 dev_err(dev, "failed to power on port%d phy\n", port->slot); 1064 goto err_phy_on; 1065 } 1066 1067 err = pcie->soc->startup(port); 1068 if (err) { 1069 dev_info(dev, "Port%d link down\n", port->slot); 1070 goto err_soc_startup; 1071 } 1072 1073 return 0; 1074 1075 err_soc_startup: 1076 phy_power_off(port->phy); 1077 err_phy_on: 1078 phy_exit(port->phy); 1079 err_phy_init: 1080 clk_disable_unprepare(port->pipe_ck); 1081 err_pipe_clk: 1082 clk_disable_unprepare(port->obff_ck); 1083 err_obff_clk: 1084 clk_disable_unprepare(port->axi_ck); 1085 err_axi_clk: 1086 clk_disable_unprepare(port->aux_ck); 1087 err_aux_clk: 1088 clk_disable_unprepare(port->ahb_ck); 1089 err_ahb_clk: 1090 clk_disable_unprepare(port->sys_ck); 1091 1092 return err; 1093 } 1094 1095 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 1096 struct device_node *node, 1097 int slot) 1098 { 1099 struct mtk_pcie_port *port; 1100 struct device *dev = pcie->dev; 1101 struct platform_device *pdev = to_platform_device(dev); 1102 struct resource *res; 1103 char name[20]; 1104 int err; 1105 1106 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1107 if (!port) 1108 return -ENOMEM; 1109 1110 snprintf(name, sizeof(name), "port%d", slot); 1111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 1112 if (!res) { 1113 dev_err(dev, "failed to get port%d base\n", slot); 1114 return -EINVAL; 1115 } 1116 1117 port->phys_base = res->start; 1118 port->base = devm_ioremap_resource(&pdev->dev, res); 1119 if (IS_ERR(port->base)) { 1120 dev_err(dev, "failed to map port%d base\n", slot); 1121 return PTR_ERR(port->base); 1122 } 1123 1124 snprintf(name, sizeof(name), "sys_ck%d", slot); 1125 port->sys_ck = devm_clk_get(dev, name); 1126 if (IS_ERR(port->sys_ck)) { 1127 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 1128 return PTR_ERR(port->sys_ck); 1129 } 1130 1131 /* sys_ck might be divided into the following parts in some chips */ 1132 snprintf(name, sizeof(name), "ahb_ck%d", slot); 1133 port->ahb_ck = devm_clk_get_optional(dev, name); 1134 if (IS_ERR(port->ahb_ck)) 1135 return PTR_ERR(port->ahb_ck); 1136 1137 snprintf(name, sizeof(name), "axi_ck%d", slot); 1138 port->axi_ck = devm_clk_get_optional(dev, name); 1139 if (IS_ERR(port->axi_ck)) 1140 return PTR_ERR(port->axi_ck); 1141 1142 snprintf(name, sizeof(name), "aux_ck%d", slot); 1143 port->aux_ck = devm_clk_get_optional(dev, name); 1144 if (IS_ERR(port->aux_ck)) 1145 return PTR_ERR(port->aux_ck); 1146 1147 snprintf(name, sizeof(name), "obff_ck%d", slot); 1148 port->obff_ck = devm_clk_get_optional(dev, name); 1149 if (IS_ERR(port->obff_ck)) 1150 return PTR_ERR(port->obff_ck); 1151 1152 snprintf(name, sizeof(name), "pipe_ck%d", slot); 1153 port->pipe_ck = devm_clk_get_optional(dev, name); 1154 if (IS_ERR(port->pipe_ck)) 1155 return PTR_ERR(port->pipe_ck); 1156 1157 snprintf(name, sizeof(name), "pcie-rst%d", slot); 1158 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 1159 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 1160 return PTR_ERR(port->reset); 1161 1162 /* some platforms may use default PHY setting */ 1163 snprintf(name, sizeof(name), "pcie-phy%d", slot); 1164 port->phy = devm_phy_optional_get(dev, name); 1165 if (IS_ERR(port->phy)) 1166 return PTR_ERR(port->phy); 1167 1168 port->slot = slot; 1169 port->pcie = pcie; 1170 1171 if (pcie->soc->setup_irq) { 1172 err = pcie->soc->setup_irq(port, node); 1173 if (err) 1174 return err; 1175 } 1176 1177 INIT_LIST_HEAD(&port->list); 1178 list_add_tail(&port->list, &pcie->ports); 1179 1180 return 0; 1181 } 1182 1183 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 1184 { 1185 struct device *dev = pcie->dev; 1186 struct platform_device *pdev = to_platform_device(dev); 1187 struct resource *regs; 1188 struct device_node *cfg_node; 1189 int err; 1190 1191 /* get shared registers, which are optional */ 1192 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 1193 if (regs) { 1194 pcie->base = devm_ioremap_resource(dev, regs); 1195 if (IS_ERR(pcie->base)) 1196 return PTR_ERR(pcie->base); 1197 } 1198 1199 cfg_node = of_find_compatible_node(NULL, NULL, 1200 "mediatek,generic-pciecfg"); 1201 if (cfg_node) { 1202 pcie->cfg = syscon_node_to_regmap(cfg_node); 1203 of_node_put(cfg_node); 1204 if (IS_ERR(pcie->cfg)) 1205 return PTR_ERR(pcie->cfg); 1206 } 1207 1208 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1209 if (IS_ERR(pcie->free_ck)) { 1210 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1211 return -EPROBE_DEFER; 1212 1213 pcie->free_ck = NULL; 1214 } 1215 1216 pm_runtime_enable(dev); 1217 pm_runtime_get_sync(dev); 1218 1219 /* enable top level clock */ 1220 err = clk_prepare_enable(pcie->free_ck); 1221 if (err) { 1222 dev_err(dev, "failed to enable free_ck\n"); 1223 goto err_free_ck; 1224 } 1225 1226 return 0; 1227 1228 err_free_ck: 1229 pm_runtime_put_sync(dev); 1230 pm_runtime_disable(dev); 1231 1232 return err; 1233 } 1234 1235 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1236 { 1237 struct device *dev = pcie->dev; 1238 struct device_node *node = dev->of_node; 1239 struct mtk_pcie_port *port, *tmp; 1240 int err, slot; 1241 1242 slot = of_get_pci_domain_nr(dev->of_node); 1243 if (slot < 0) { 1244 for_each_available_child_of_node_scoped(node, child) { 1245 err = of_pci_get_devfn(child); 1246 if (err < 0) 1247 return dev_err_probe(dev, err, "failed to get devfn\n"); 1248 1249 slot = PCI_SLOT(err); 1250 1251 err = mtk_pcie_parse_port(pcie, child, slot); 1252 if (err) 1253 return err; 1254 } 1255 } else { 1256 err = mtk_pcie_parse_port(pcie, node, slot); 1257 if (err) 1258 return err; 1259 } 1260 1261 err = mtk_pcie_subsys_powerup(pcie); 1262 if (err) 1263 return err; 1264 1265 /* enable each port, and then check link status */ 1266 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1267 err = mtk_pcie_enable_port(port); 1268 if (err) { 1269 mtk_pcie_irq_teardown_port(port); 1270 mtk_pcie_port_free(port); 1271 } 1272 } 1273 1274 /* power down PCIe subsys if slots are all empty (link down) */ 1275 if (list_empty(&pcie->ports)) 1276 mtk_pcie_subsys_powerdown(pcie); 1277 1278 return 0; 1279 } 1280 1281 static int mtk_pcie_probe(struct platform_device *pdev) 1282 { 1283 struct device *dev = &pdev->dev; 1284 struct mtk_pcie *pcie; 1285 struct pci_host_bridge *host; 1286 int err; 1287 1288 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1289 if (!host) 1290 return -ENOMEM; 1291 1292 pcie = pci_host_bridge_priv(host); 1293 1294 pcie->dev = dev; 1295 pcie->soc = of_device_get_match_data(dev); 1296 platform_set_drvdata(pdev, pcie); 1297 INIT_LIST_HEAD(&pcie->ports); 1298 1299 err = mtk_pcie_setup(pcie); 1300 if (err) 1301 return err; 1302 1303 host->ops = pcie->soc->ops; 1304 host->sysdata = pcie; 1305 host->msi_domain = !!(pcie->soc->quirks & MTK_PCIE_NO_MSI); 1306 1307 err = pci_host_probe(host); 1308 if (err) 1309 goto put_resources; 1310 1311 /* 1312 * Ignore error because pci_host_probe() was already called, and in any 1313 * case it is possible that the port will still work as Gen1. 1314 */ 1315 if (pcie->soc->quirks & MTK_PCIE_RETRAIN) 1316 mtk_pcie_retrain(dev, host); 1317 1318 return 0; 1319 1320 put_resources: 1321 if (!list_empty(&pcie->ports)) 1322 mtk_pcie_put_resources(pcie); 1323 1324 return err; 1325 } 1326 1327 1328 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1329 { 1330 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1331 struct list_head *windows = &host->windows; 1332 1333 pci_free_resource_list(windows); 1334 } 1335 1336 static void mtk_pcie_remove(struct platform_device *pdev) 1337 { 1338 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1339 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1340 1341 pci_lock_rescan_remove(); 1342 pci_stop_root_bus(host->bus); 1343 pci_remove_root_bus(host->bus); 1344 pci_unlock_rescan_remove(); 1345 mtk_pcie_free_resources(pcie); 1346 1347 mtk_pcie_irq_teardown(pcie); 1348 1349 mtk_pcie_put_resources(pcie); 1350 } 1351 1352 static int mtk_pcie_suspend_noirq(struct device *dev) 1353 { 1354 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1355 struct mtk_pcie_port *port; 1356 1357 if (list_empty(&pcie->ports)) 1358 return 0; 1359 1360 list_for_each_entry(port, &pcie->ports, list) { 1361 clk_disable_unprepare(port->pipe_ck); 1362 clk_disable_unprepare(port->obff_ck); 1363 clk_disable_unprepare(port->axi_ck); 1364 clk_disable_unprepare(port->aux_ck); 1365 clk_disable_unprepare(port->ahb_ck); 1366 clk_disable_unprepare(port->sys_ck); 1367 phy_power_off(port->phy); 1368 phy_exit(port->phy); 1369 } 1370 1371 clk_disable_unprepare(pcie->free_ck); 1372 1373 return 0; 1374 } 1375 1376 static int mtk_pcie_resume_noirq(struct device *dev) 1377 { 1378 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1379 struct mtk_pcie_port *port, *tmp; 1380 int err; 1381 1382 if (list_empty(&pcie->ports)) 1383 return 0; 1384 1385 clk_prepare_enable(pcie->free_ck); 1386 1387 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1388 err = mtk_pcie_enable_port(port); 1389 if (err) 1390 mtk_pcie_port_free(port); 1391 } 1392 1393 /* In case of EP was removed while system suspend. */ 1394 if (list_empty(&pcie->ports)) 1395 clk_disable_unprepare(pcie->free_ck); 1396 1397 return 0; 1398 } 1399 1400 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1401 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1402 mtk_pcie_resume_noirq) 1403 }; 1404 1405 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1406 .ops = &mtk_pcie_ops, 1407 .startup = mtk_pcie_startup_port, 1408 .quirks = MTK_PCIE_NO_MSI, 1409 }; 1410 1411 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1412 .ops = &mtk_pcie_ops_v2, 1413 .startup = mtk_pcie_startup_port_v2, 1414 .setup_irq = mtk_pcie_setup_irq, 1415 }; 1416 1417 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1418 .ops = &mtk_pcie_ops_v2, 1419 .startup = mtk_pcie_startup_port_v2, 1420 .setup_irq = mtk_pcie_setup_irq, 1421 .quirks = MTK_PCIE_FIX_CLASS_ID, 1422 }; 1423 1424 static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = { 1425 .ops = &mtk_pcie_ops_v2, 1426 .startup = mtk_pcie_startup_port_an7583, 1427 .setup_irq = mtk_pcie_setup_irq, 1428 .quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB, 1429 }; 1430 1431 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { 1432 .device_id = PCI_DEVICE_ID_MEDIATEK_7629, 1433 .ops = &mtk_pcie_ops_v2, 1434 .startup = mtk_pcie_startup_port_v2, 1435 .setup_irq = mtk_pcie_setup_irq, 1436 .quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, 1437 }; 1438 1439 static const struct mtk_pcie_soc mtk_pcie_soc_en7528 = { 1440 .ops = &mtk_pcie_ops_v2, 1441 .startup = mtk_pcie_startup_port_en7528, 1442 .setup_irq = mtk_pcie_setup_irq, 1443 .quirks = MTK_PCIE_RETRAIN, 1444 }; 1445 1446 static const struct of_device_id mtk_pcie_ids[] = { 1447 { .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 }, 1448 { .compatible = "econet,en7528-pcie", .data = &mtk_pcie_soc_en7528 }, 1449 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1450 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1451 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1452 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1453 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, 1454 {}, 1455 }; 1456 MODULE_DEVICE_TABLE(of, mtk_pcie_ids); 1457 1458 static struct platform_driver mtk_pcie_driver = { 1459 .probe = mtk_pcie_probe, 1460 .remove = mtk_pcie_remove, 1461 .driver = { 1462 .name = "mtk-pcie", 1463 .of_match_table = mtk_pcie_ids, 1464 .suppress_bind_attrs = true, 1465 .pm = &mtk_pcie_pm_ops, 1466 }, 1467 }; 1468 module_platform_driver(mtk_pcie_driver); 1469 MODULE_DESCRIPTION("MediaTek PCIe host controller driver"); 1470 MODULE_LICENSE("GPL v2"); 1471