1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2020 MediaTek Inc. 6 * Author: Jianjun Wang <jianjun.wang@mediatek.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/irqchip/irq-msi-lib.h> 16 #include <linux/irqchip/chained_irq.h> 17 #include <linux/irqdomain.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/msi.h> 22 #include <linux/of_device.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_domain.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regmap.h> 30 #include <linux/reset.h> 31 32 #include "../pci.h" 33 34 #define PCIE_BASE_CFG_REG 0x14 35 #define PCIE_BASE_CFG_SPEED GENMASK(15, 8) 36 37 #define PCIE_SETTING_REG 0x80 38 #define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8) 39 #define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12) 40 #define PCIE_PCI_IDS_1 0x9c 41 #define PCI_CLASS(class) (class << 8) 42 #define PCIE_RC_MODE BIT(0) 43 44 #define PCIE_EQ_PRESET_01_REG 0x100 45 #define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0) 46 #define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8) 47 #define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16) 48 #define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24) 49 50 #define PCIE_CFGNUM_REG 0x140 51 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) 52 #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) 53 #define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16)) 54 #define PCIE_CFG_FORCE_BYTE_EN BIT(20) 55 #define PCIE_CFG_OFFSET_ADDR 0x1000 56 #define PCIE_CFG_HEADER(bus, devfn) \ 57 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) 58 59 #define PCIE_RST_CTRL_REG 0x148 60 #define PCIE_MAC_RSTB BIT(0) 61 #define PCIE_PHY_RSTB BIT(1) 62 #define PCIE_BRG_RSTB BIT(2) 63 #define PCIE_PE_RSTB BIT(3) 64 65 #define PCIE_LTSSM_STATUS_REG 0x150 66 #define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) 67 #define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24) 68 #define PCIE_LTSSM_STATE_L2_IDLE 0x14 69 70 #define PCIE_LINK_STATUS_REG 0x154 71 #define PCIE_PORT_LINKUP BIT(8) 72 73 #define PCIE_MSI_SET_NUM 8 74 #define PCIE_MSI_IRQS_PER_SET 32 75 #define PCIE_MSI_IRQS_NUM \ 76 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM) 77 78 #define PCIE_INT_ENABLE_REG 0x180 79 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) 80 #define PCIE_MSI_SHIFT 8 81 #define PCIE_INTX_SHIFT 24 82 #define PCIE_INTX_ENABLE \ 83 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) 84 85 #define PCIE_INT_STATUS_REG 0x184 86 #define PCIE_MSI_SET_ENABLE_REG 0x190 87 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) 88 89 #define PCIE_PIPE4_PIE8_REG 0x338 90 #define PCIE_K_FINETUNE_MAX GENMASK(5, 0) 91 #define PCIE_K_FINETUNE_ERR GENMASK(7, 6) 92 #define PCIE_K_PRESET_TO_USE GENMASK(18, 8) 93 #define PCIE_K_PHYPARAM_QUERY BIT(19) 94 #define PCIE_K_QUERY_TIMEOUT BIT(20) 95 #define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21) 96 97 #define PCIE_MSI_SET_BASE_REG 0xc00 98 #define PCIE_MSI_SET_OFFSET 0x10 99 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 100 #define PCIE_MSI_SET_ENABLE_OFFSET 0x08 101 102 #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 103 #define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04 104 105 #define PCIE_ICMD_PM_REG 0x198 106 #define PCIE_TURN_OFF_LINK BIT(4) 107 108 #define PCIE_MISC_CTRL_REG 0x348 109 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) 110 111 #define PCIE_TRANS_TABLE_BASE_REG 0x800 112 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 113 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 114 #define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc 115 #define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 116 #define PCIE_ATR_TLB_SET_OFFSET 0x20 117 118 #define PCIE_MAX_TRANS_TABLES 8 119 #define PCIE_ATR_EN BIT(0) 120 #define PCIE_ATR_SIZE(size) \ 121 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) 122 #define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) 123 #define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) 124 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) 125 #define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) 126 #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) 127 #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) 128 129 #define MAX_NUM_PHY_RESETS 3 130 131 #define PCIE_MTK_RESET_TIME_US 10 132 133 /* Time in ms needed to complete PCIe reset on EN7581 SoC */ 134 #define PCIE_EN7581_RESET_TIME_MS 100 135 136 struct mtk_gen3_pcie; 137 138 #define PCIE_CONF_LINK2_CTL_STS (PCIE_CFG_OFFSET_ADDR + 0xb0) 139 #define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0) 140 141 enum mtk_gen3_pcie_flags { 142 SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device 143 * probing or suspend/resume phase to 144 * avoid hw bugs/issues. 145 */ 146 }; 147 148 /** 149 * struct mtk_gen3_pcie_pdata - differentiate between host generations 150 * @power_up: pcie power_up callback 151 * @phy_resets: phy reset lines SoC data. 152 * @flags: pcie device flags. 153 */ 154 struct mtk_gen3_pcie_pdata { 155 int (*power_up)(struct mtk_gen3_pcie *pcie); 156 struct { 157 const char *id[MAX_NUM_PHY_RESETS]; 158 int num_resets; 159 } phy_resets; 160 u32 flags; 161 }; 162 163 /** 164 * struct mtk_msi_set - MSI information for each set 165 * @base: IO mapped register base 166 * @msg_addr: MSI message address 167 * @saved_irq_state: IRQ enable state saved at suspend time 168 */ 169 struct mtk_msi_set { 170 void __iomem *base; 171 phys_addr_t msg_addr; 172 u32 saved_irq_state; 173 }; 174 175 /** 176 * struct mtk_gen3_pcie - PCIe port information 177 * @dev: pointer to PCIe device 178 * @base: IO mapped register base 179 * @reg_base: physical register base 180 * @mac_reset: MAC reset control 181 * @phy_resets: PHY reset controllers 182 * @phy: PHY controller block 183 * @clks: PCIe clocks 184 * @num_clks: PCIe clocks count for this port 185 * @max_link_speed: Maximum link speed (PCIe Gen) for this port 186 * @num_lanes: Number of PCIe lanes for this port 187 * @irq: PCIe controller interrupt number 188 * @saved_irq_state: IRQ enable state saved at suspend time 189 * @irq_lock: lock protecting IRQ register access 190 * @intx_domain: legacy INTx IRQ domain 191 * @msi_bottom_domain: MSI IRQ bottom domain 192 * @msi_sets: MSI sets information 193 * @lock: lock protecting IRQ bit map 194 * @msi_irq_in_use: bit map for assigned MSI IRQ 195 * @soc: pointer to SoC-dependent operations 196 */ 197 struct mtk_gen3_pcie { 198 struct device *dev; 199 void __iomem *base; 200 phys_addr_t reg_base; 201 struct reset_control *mac_reset; 202 struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; 203 struct phy *phy; 204 struct clk_bulk_data *clks; 205 int num_clks; 206 u8 max_link_speed; 207 u8 num_lanes; 208 209 int irq; 210 u32 saved_irq_state; 211 raw_spinlock_t irq_lock; 212 struct irq_domain *intx_domain; 213 struct irq_domain *msi_bottom_domain; 214 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; 215 struct mutex lock; 216 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); 217 218 const struct mtk_gen3_pcie_pdata *soc; 219 }; 220 221 /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ 222 static const char *const ltssm_str[] = { 223 "detect.quiet", /* 0x00 */ 224 "detect.active", /* 0x01 */ 225 "polling.active", /* 0x02 */ 226 "polling.compliance", /* 0x03 */ 227 "polling.configuration", /* 0x04 */ 228 "config.linkwidthstart", /* 0x05 */ 229 "config.linkwidthaccept", /* 0x06 */ 230 "config.lanenumwait", /* 0x07 */ 231 "config.lanenumaccept", /* 0x08 */ 232 "config.complete", /* 0x09 */ 233 "config.idle", /* 0x0A */ 234 "recovery.receiverlock", /* 0x0B */ 235 "recovery.equalization", /* 0x0C */ 236 "recovery.speed", /* 0x0D */ 237 "recovery.receiverconfig", /* 0x0E */ 238 "recovery.idle", /* 0x0F */ 239 "L0", /* 0x10 */ 240 "L0s", /* 0x11 */ 241 "L1.entry", /* 0x12 */ 242 "L1.idle", /* 0x13 */ 243 "L2.idle", /* 0x14 */ 244 "L2.transmitwake", /* 0x15 */ 245 "disable", /* 0x16 */ 246 "loopback.entry", /* 0x17 */ 247 "loopback.active", /* 0x18 */ 248 "loopback.exit", /* 0x19 */ 249 "hotreset", /* 0x1A */ 250 }; 251 252 /** 253 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header 254 * @bus: PCI bus to query 255 * @devfn: device/function number 256 * @where: offset in config space 257 * @size: data size in TLP header 258 * 259 * Set byte enable field and device information in configuration TLP header. 260 */ 261 static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, 262 int where, int size) 263 { 264 struct mtk_gen3_pcie *pcie = bus->sysdata; 265 int bytes; 266 u32 val; 267 268 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); 269 270 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) | 271 PCIE_CFG_HEADER(bus->number, devfn); 272 273 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); 274 } 275 276 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 277 int where) 278 { 279 struct mtk_gen3_pcie *pcie = bus->sysdata; 280 281 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; 282 } 283 284 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 285 int where, int size, u32 *val) 286 { 287 mtk_pcie_config_tlp_header(bus, devfn, where, size); 288 289 return pci_generic_config_read32(bus, devfn, where, size, val); 290 } 291 292 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 293 int where, int size, u32 val) 294 { 295 mtk_pcie_config_tlp_header(bus, devfn, where, size); 296 297 if (size <= 2) 298 val <<= (where & 0x3) * 8; 299 300 return pci_generic_config_write32(bus, devfn, where, 4, val); 301 } 302 303 static struct pci_ops mtk_pcie_ops = { 304 .map_bus = mtk_pcie_map_bus, 305 .read = mtk_pcie_config_read, 306 .write = mtk_pcie_config_write, 307 }; 308 309 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, 310 resource_size_t cpu_addr, 311 resource_size_t pci_addr, 312 resource_size_t size, 313 unsigned long type, int *num) 314 { 315 resource_size_t remaining = size; 316 resource_size_t table_size; 317 resource_size_t addr_align; 318 const char *range_type; 319 void __iomem *table; 320 u32 val; 321 322 while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) { 323 /* Table size needs to be a power of 2 */ 324 table_size = BIT(fls(remaining) - 1); 325 326 if (cpu_addr > 0) { 327 addr_align = BIT(ffs(cpu_addr) - 1); 328 table_size = min(table_size, addr_align); 329 } 330 331 /* Minimum size of translate table is 4KiB */ 332 if (table_size < 0x1000) { 333 dev_err(pcie->dev, "illegal table size %#llx\n", 334 (unsigned long long)table_size); 335 return -EINVAL; 336 } 337 338 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; 339 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table); 340 writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET); 341 writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET); 342 writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET); 343 344 if (type == IORESOURCE_IO) { 345 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; 346 range_type = "IO"; 347 } else { 348 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; 349 range_type = "MEM"; 350 } 351 352 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET); 353 354 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", 355 range_type, *num, (unsigned long long)cpu_addr, 356 (unsigned long long)pci_addr, 357 (unsigned long long)table_size); 358 359 cpu_addr += table_size; 360 pci_addr += table_size; 361 remaining -= table_size; 362 (*num)++; 363 } 364 365 if (remaining) 366 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", 367 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES); 368 369 return 0; 370 } 371 372 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) 373 { 374 int i; 375 u32 val; 376 377 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 378 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 379 380 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + 381 i * PCIE_MSI_SET_OFFSET; 382 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG + 383 i * PCIE_MSI_SET_OFFSET; 384 385 /* Configure the MSI capture address */ 386 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); 387 writel_relaxed(upper_32_bits(msi_set->msg_addr), 388 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + 389 i * PCIE_MSI_SET_ADDR_HI_OFFSET); 390 } 391 392 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); 393 val |= PCIE_MSI_SET_ENABLE; 394 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); 395 396 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 397 val |= PCIE_MSI_ENABLE; 398 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 399 } 400 401 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) 402 { 403 struct resource_entry *entry; 404 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 405 unsigned int table_index = 0; 406 int err; 407 u32 val; 408 409 /* Set as RC mode and set controller PCIe Gen speed restriction, if any */ 410 val = readl_relaxed(pcie->base + PCIE_SETTING_REG); 411 val |= PCIE_RC_MODE; 412 if (pcie->max_link_speed) { 413 val &= ~PCIE_SETTING_GEN_SUPPORT; 414 415 /* Can enable link speed support only from Gen2 onwards */ 416 if (pcie->max_link_speed >= 2) 417 val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT, 418 GENMASK(pcie->max_link_speed - 2, 0)); 419 } 420 if (pcie->num_lanes) { 421 val &= ~PCIE_SETTING_LINK_WIDTH; 422 423 /* Zero means one lane, each bit activates x2/x4/x8/x16 */ 424 if (pcie->num_lanes > 1) 425 val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH, 426 GENMASK(fls(pcie->num_lanes >> 2), 0)); 427 } 428 writel_relaxed(val, pcie->base + PCIE_SETTING_REG); 429 430 /* Set Link Control 2 (LNKCTL2) speed restriction, if any */ 431 if (pcie->max_link_speed) { 432 val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS); 433 val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED; 434 val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed); 435 writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS); 436 } 437 438 /* Set class code */ 439 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1); 440 val &= ~GENMASK(31, 8); 441 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL); 442 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1); 443 444 /* Mask all INTx interrupts */ 445 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 446 val &= ~PCIE_INTX_ENABLE; 447 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 448 449 /* Disable DVFSRC voltage request */ 450 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); 451 val |= PCIE_DISABLE_DVFSRC_VLT_REQ; 452 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); 453 454 /* 455 * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal 456 * causing occasional PCIe link down. In order to overcome the issue, 457 * PCIE_RSTB signals are not asserted/released at this stage and the 458 * PCIe block is reset using en7523_reset_assert() and 459 * en7581_pci_enable(). 460 */ 461 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { 462 /* Assert all reset signals */ 463 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); 464 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | 465 PCIE_PE_RSTB; 466 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 467 468 /* 469 * Described in PCIe CEM specification revision 6.0. 470 * 471 * The deassertion of PERST# should be delayed 100ms (TPVPERL) 472 * for the power and clock to become stable. 473 */ 474 msleep(PCIE_T_PVPERL_MS); 475 476 /* De-assert reset signals */ 477 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | 478 PCIE_PE_RSTB); 479 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 480 } 481 482 /* Check if the link is up or not */ 483 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, 484 !!(val & PCIE_PORT_LINKUP), 20, 485 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); 486 if (err) { 487 const char *ltssm_state; 488 int ltssm_index; 489 490 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG); 491 ltssm_index = PCIE_LTSSM_STATE(val); 492 ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ? 493 "Unknown state" : ltssm_str[ltssm_index]; 494 dev_err(pcie->dev, 495 "PCIe link down, current LTSSM state: %s (%#x)\n", 496 ltssm_state, val); 497 return err; 498 } 499 500 mtk_pcie_enable_msi(pcie); 501 502 /* Set PCIe translation windows */ 503 resource_list_for_each_entry(entry, &host->windows) { 504 struct resource *res = entry->res; 505 unsigned long type = resource_type(res); 506 resource_size_t cpu_addr; 507 resource_size_t pci_addr; 508 resource_size_t size; 509 510 if (type == IORESOURCE_IO) 511 cpu_addr = pci_pio_to_address(res->start); 512 else if (type == IORESOURCE_MEM) 513 cpu_addr = res->start; 514 else 515 continue; 516 517 pci_addr = res->start - entry->offset; 518 size = resource_size(res); 519 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, 520 type, &table_index); 521 if (err) 522 return err; 523 } 524 525 return 0; 526 } 527 528 #define MTK_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 529 MSI_FLAG_USE_DEF_CHIP_OPS | \ 530 MSI_FLAG_NO_AFFINITY | \ 531 MSI_FLAG_PCI_MSI_MASK_PARENT) 532 533 #define MTK_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 534 MSI_FLAG_PCI_MSIX | \ 535 MSI_FLAG_MULTI_PCI_MSI) 536 537 static const struct msi_parent_ops mtk_msi_parent_ops = { 538 .required_flags = MTK_MSI_FLAGS_REQUIRED, 539 .supported_flags = MTK_MSI_FLAGS_SUPPORTED, 540 .bus_select_token = DOMAIN_BUS_PCI_MSI, 541 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 542 .prefix = "MTK3-", 543 .init_dev_msi_info = msi_lib_init_dev_msi_info, 544 }; 545 546 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 547 { 548 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 549 struct mtk_gen3_pcie *pcie = data->domain->host_data; 550 unsigned long hwirq; 551 552 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 553 554 msg->address_hi = upper_32_bits(msi_set->msg_addr); 555 msg->address_lo = lower_32_bits(msi_set->msg_addr); 556 msg->data = hwirq; 557 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", 558 hwirq, msg->address_hi, msg->address_lo, msg->data); 559 } 560 561 static void mtk_msi_bottom_irq_ack(struct irq_data *data) 562 { 563 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 564 unsigned long hwirq; 565 566 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 567 568 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET); 569 } 570 571 static void mtk_msi_bottom_irq_mask(struct irq_data *data) 572 { 573 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 574 struct mtk_gen3_pcie *pcie = data->domain->host_data; 575 unsigned long hwirq, flags; 576 u32 val; 577 578 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 579 580 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 581 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 582 val &= ~BIT(hwirq); 583 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 584 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 585 } 586 587 static void mtk_msi_bottom_irq_unmask(struct irq_data *data) 588 { 589 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 590 struct mtk_gen3_pcie *pcie = data->domain->host_data; 591 unsigned long hwirq, flags; 592 u32 val; 593 594 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 595 596 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 597 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 598 val |= BIT(hwirq); 599 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 600 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 601 } 602 603 static struct irq_chip mtk_msi_bottom_irq_chip = { 604 .irq_ack = mtk_msi_bottom_irq_ack, 605 .irq_mask = mtk_msi_bottom_irq_mask, 606 .irq_unmask = mtk_msi_bottom_irq_unmask, 607 .irq_compose_msi_msg = mtk_compose_msi_msg, 608 .name = "MSI", 609 }; 610 611 static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain, 612 unsigned int virq, unsigned int nr_irqs, 613 void *arg) 614 { 615 struct mtk_gen3_pcie *pcie = domain->host_data; 616 struct mtk_msi_set *msi_set; 617 int i, hwirq, set_idx; 618 619 mutex_lock(&pcie->lock); 620 621 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM, 622 order_base_2(nr_irqs)); 623 624 mutex_unlock(&pcie->lock); 625 626 if (hwirq < 0) 627 return -ENOSPC; 628 629 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET; 630 msi_set = &pcie->msi_sets[set_idx]; 631 632 for (i = 0; i < nr_irqs; i++) 633 irq_domain_set_info(domain, virq + i, hwirq + i, 634 &mtk_msi_bottom_irq_chip, msi_set, 635 handle_edge_irq, NULL, NULL); 636 637 return 0; 638 } 639 640 static void mtk_msi_bottom_domain_free(struct irq_domain *domain, 641 unsigned int virq, unsigned int nr_irqs) 642 { 643 struct mtk_gen3_pcie *pcie = domain->host_data; 644 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 645 646 mutex_lock(&pcie->lock); 647 648 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, 649 order_base_2(nr_irqs)); 650 651 mutex_unlock(&pcie->lock); 652 653 irq_domain_free_irqs_common(domain, virq, nr_irqs); 654 } 655 656 static const struct irq_domain_ops mtk_msi_bottom_domain_ops = { 657 .alloc = mtk_msi_bottom_domain_alloc, 658 .free = mtk_msi_bottom_domain_free, 659 }; 660 661 static void mtk_intx_mask(struct irq_data *data) 662 { 663 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 664 unsigned long flags; 665 u32 val; 666 667 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 668 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 669 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); 670 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 671 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 672 } 673 674 static void mtk_intx_unmask(struct irq_data *data) 675 { 676 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 677 unsigned long flags; 678 u32 val; 679 680 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 681 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 682 val |= BIT(data->hwirq + PCIE_INTX_SHIFT); 683 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 684 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 685 } 686 687 /** 688 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt 689 * @data: pointer to chip specific data 690 * 691 * As an emulated level IRQ, its interrupt status will remain 692 * until the corresponding de-assert message is received; hence that 693 * the status can only be cleared when the interrupt has been serviced. 694 */ 695 static void mtk_intx_eoi(struct irq_data *data) 696 { 697 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 698 unsigned long hwirq; 699 700 hwirq = data->hwirq + PCIE_INTX_SHIFT; 701 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG); 702 } 703 704 static struct irq_chip mtk_intx_irq_chip = { 705 .irq_mask = mtk_intx_mask, 706 .irq_unmask = mtk_intx_unmask, 707 .irq_eoi = mtk_intx_eoi, 708 .name = "INTx", 709 }; 710 711 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 712 irq_hw_number_t hwirq) 713 { 714 irq_set_chip_data(irq, domain->host_data); 715 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip, 716 handle_fasteoi_irq, "INTx"); 717 return 0; 718 } 719 720 static const struct irq_domain_ops intx_domain_ops = { 721 .map = mtk_pcie_intx_map, 722 }; 723 724 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) 725 { 726 struct device *dev = pcie->dev; 727 struct device_node *intc_node, *node = dev->of_node; 728 int ret; 729 730 raw_spin_lock_init(&pcie->irq_lock); 731 732 /* Setup INTx */ 733 intc_node = of_get_child_by_name(node, "interrupt-controller"); 734 if (!intc_node) { 735 dev_err(dev, "missing interrupt-controller node\n"); 736 return -ENODEV; 737 } 738 739 pcie->intx_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX, 740 &intx_domain_ops, pcie); 741 if (!pcie->intx_domain) { 742 dev_err(dev, "failed to create INTx IRQ domain\n"); 743 ret = -ENODEV; 744 goto out_put_node; 745 } 746 747 /* Setup MSI */ 748 mutex_init(&pcie->lock); 749 750 struct irq_domain_info info = { 751 .fwnode = dev_fwnode(dev), 752 .ops = &mtk_msi_bottom_domain_ops, 753 .host_data = pcie, 754 .size = PCIE_MSI_IRQS_NUM, 755 }; 756 757 pcie->msi_bottom_domain = msi_create_parent_irq_domain(&info, &mtk_msi_parent_ops); 758 if (!pcie->msi_bottom_domain) { 759 dev_err(dev, "failed to create MSI bottom domain\n"); 760 ret = -ENODEV; 761 goto err_msi_bottom_domain; 762 } 763 764 of_node_put(intc_node); 765 return 0; 766 767 err_msi_bottom_domain: 768 irq_domain_remove(pcie->intx_domain); 769 out_put_node: 770 of_node_put(intc_node); 771 return ret; 772 } 773 774 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) 775 { 776 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); 777 778 if (pcie->intx_domain) 779 irq_domain_remove(pcie->intx_domain); 780 781 if (pcie->msi_bottom_domain) 782 irq_domain_remove(pcie->msi_bottom_domain); 783 784 irq_dispose_mapping(pcie->irq); 785 } 786 787 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx) 788 { 789 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx]; 790 unsigned long msi_enable, msi_status; 791 irq_hw_number_t bit, hwirq; 792 793 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 794 795 do { 796 msi_status = readl_relaxed(msi_set->base + 797 PCIE_MSI_SET_STATUS_OFFSET); 798 msi_status &= msi_enable; 799 if (!msi_status) 800 break; 801 802 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) { 803 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET; 804 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq); 805 } 806 } while (true); 807 } 808 809 static void mtk_pcie_irq_handler(struct irq_desc *desc) 810 { 811 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc); 812 struct irq_chip *irqchip = irq_desc_get_chip(desc); 813 unsigned long status; 814 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT; 815 816 chained_irq_enter(irqchip, desc); 817 818 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG); 819 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX + 820 PCIE_INTX_SHIFT) 821 generic_handle_domain_irq(pcie->intx_domain, 822 irq_bit - PCIE_INTX_SHIFT); 823 824 irq_bit = PCIE_MSI_SHIFT; 825 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + 826 PCIE_MSI_SHIFT) { 827 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT); 828 829 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG); 830 } 831 832 chained_irq_exit(irqchip, desc); 833 } 834 835 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) 836 { 837 struct device *dev = pcie->dev; 838 struct platform_device *pdev = to_platform_device(dev); 839 int err; 840 841 err = mtk_pcie_init_irq_domains(pcie); 842 if (err) 843 return err; 844 845 pcie->irq = platform_get_irq(pdev, 0); 846 if (pcie->irq < 0) 847 return pcie->irq; 848 849 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie); 850 851 return 0; 852 } 853 854 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 855 { 856 int i, ret, num_resets = pcie->soc->phy_resets.num_resets; 857 struct device *dev = pcie->dev; 858 struct platform_device *pdev = to_platform_device(dev); 859 struct resource *regs; 860 u32 num_lanes; 861 862 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); 863 if (!regs) 864 return -EINVAL; 865 pcie->base = devm_ioremap_resource(dev, regs); 866 if (IS_ERR(pcie->base)) { 867 dev_err(dev, "failed to map register base\n"); 868 return PTR_ERR(pcie->base); 869 } 870 871 pcie->reg_base = regs->start; 872 873 for (i = 0; i < num_resets; i++) 874 pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i]; 875 876 ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, 877 pcie->phy_resets); 878 if (ret) { 879 dev_err(dev, "failed to get PHY bulk reset\n"); 880 return ret; 881 } 882 883 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); 884 if (IS_ERR(pcie->mac_reset)) { 885 ret = PTR_ERR(pcie->mac_reset); 886 if (ret != -EPROBE_DEFER) 887 dev_err(dev, "failed to get MAC reset\n"); 888 889 return ret; 890 } 891 892 pcie->phy = devm_phy_optional_get(dev, "pcie-phy"); 893 if (IS_ERR(pcie->phy)) { 894 ret = PTR_ERR(pcie->phy); 895 if (ret != -EPROBE_DEFER) 896 dev_err(dev, "failed to get PHY\n"); 897 898 return ret; 899 } 900 901 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); 902 if (pcie->num_clks < 0) { 903 dev_err(dev, "failed to get clocks\n"); 904 return pcie->num_clks; 905 } 906 907 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); 908 if (ret == 0) { 909 if (num_lanes == 0 || num_lanes > 16 || 910 (num_lanes != 1 && num_lanes % 2)) 911 dev_warn(dev, "invalid num-lanes, using controller defaults\n"); 912 else 913 pcie->num_lanes = num_lanes; 914 } 915 916 return 0; 917 } 918 919 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 920 { 921 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 922 struct device *dev = pcie->dev; 923 struct resource_entry *entry; 924 struct regmap *pbus_regmap; 925 u32 val, args[2], size; 926 resource_size_t addr; 927 int err; 928 929 /* 930 * The controller may have been left out of reset by the bootloader 931 * so make sure that we get a clean start by asserting resets here. 932 */ 933 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 934 pcie->phy_resets); 935 936 /* Wait for the time needed to complete the reset lines assert. */ 937 msleep(PCIE_EN7581_RESET_TIME_MS); 938 939 /* 940 * Configure PBus base address and base address mask to allow the 941 * hw to detect if a given address is accessible on PCIe controller. 942 */ 943 pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 944 "mediatek,pbus-csr", 945 ARRAY_SIZE(args), 946 args); 947 if (IS_ERR(pbus_regmap)) 948 return PTR_ERR(pbus_regmap); 949 950 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 951 if (!entry) 952 return -ENODEV; 953 954 addr = entry->res->start - entry->offset; 955 regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); 956 size = lower_32_bits(resource_size(entry->res)); 957 regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); 958 959 /* 960 * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 961 * requires PHY initialization and power-on before PHY reset deassert. 962 */ 963 err = phy_init(pcie->phy); 964 if (err) { 965 dev_err(dev, "failed to initialize PHY\n"); 966 return err; 967 } 968 969 err = phy_power_on(pcie->phy); 970 if (err) { 971 dev_err(dev, "failed to power on PHY\n"); 972 goto err_phy_on; 973 } 974 975 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 976 pcie->phy_resets); 977 if (err) { 978 dev_err(dev, "failed to deassert PHYs\n"); 979 goto err_phy_deassert; 980 } 981 982 /* 983 * Wait for the time needed to complete the bulk de-assert above. 984 * This time is specific for EN7581 SoC. 985 */ 986 msleep(PCIE_EN7581_RESET_TIME_MS); 987 988 pm_runtime_enable(dev); 989 pm_runtime_get_sync(dev); 990 991 val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | 992 FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | 993 FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | 994 FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); 995 writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); 996 997 val = PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | 998 FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | 999 FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | 1000 FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); 1001 writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); 1002 1003 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); 1004 if (err) { 1005 dev_err(dev, "failed to prepare clock\n"); 1006 goto err_clk_prepare_enable; 1007 } 1008 1009 /* 1010 * Airoha EN7581 performs PCIe reset via clk callbacks since it has a 1011 * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to 1012 * complete the PCIe reset. 1013 */ 1014 msleep(PCIE_T_PVPERL_MS); 1015 1016 return 0; 1017 1018 err_clk_prepare_enable: 1019 pm_runtime_put_sync(dev); 1020 pm_runtime_disable(dev); 1021 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1022 pcie->phy_resets); 1023 err_phy_deassert: 1024 phy_power_off(pcie->phy); 1025 err_phy_on: 1026 phy_exit(pcie->phy); 1027 1028 return err; 1029 } 1030 1031 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 1032 { 1033 struct device *dev = pcie->dev; 1034 int err; 1035 1036 /* 1037 * The controller may have been left out of reset by the bootloader 1038 * so make sure that we get a clean start by asserting resets here. 1039 */ 1040 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1041 pcie->phy_resets); 1042 reset_control_assert(pcie->mac_reset); 1043 usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); 1044 1045 /* PHY power on and enable pipe clock */ 1046 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 1047 pcie->phy_resets); 1048 if (err) { 1049 dev_err(dev, "failed to deassert PHYs\n"); 1050 return err; 1051 } 1052 1053 err = phy_init(pcie->phy); 1054 if (err) { 1055 dev_err(dev, "failed to initialize PHY\n"); 1056 goto err_phy_init; 1057 } 1058 1059 err = phy_power_on(pcie->phy); 1060 if (err) { 1061 dev_err(dev, "failed to power on PHY\n"); 1062 goto err_phy_on; 1063 } 1064 1065 /* MAC power on and enable transaction layer clocks */ 1066 reset_control_deassert(pcie->mac_reset); 1067 1068 pm_runtime_enable(dev); 1069 pm_runtime_get_sync(dev); 1070 1071 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); 1072 if (err) { 1073 dev_err(dev, "failed to enable clocks\n"); 1074 goto err_clk_init; 1075 } 1076 1077 return 0; 1078 1079 err_clk_init: 1080 pm_runtime_put_sync(dev); 1081 pm_runtime_disable(dev); 1082 reset_control_assert(pcie->mac_reset); 1083 phy_power_off(pcie->phy); 1084 err_phy_on: 1085 phy_exit(pcie->phy); 1086 err_phy_init: 1087 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1088 pcie->phy_resets); 1089 1090 return err; 1091 } 1092 1093 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) 1094 { 1095 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); 1096 1097 pm_runtime_put_sync(pcie->dev); 1098 pm_runtime_disable(pcie->dev); 1099 reset_control_assert(pcie->mac_reset); 1100 1101 phy_power_off(pcie->phy); 1102 phy_exit(pcie->phy); 1103 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1104 pcie->phy_resets); 1105 } 1106 1107 static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie) 1108 { 1109 u32 val; 1110 int ret; 1111 1112 val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG); 1113 val = FIELD_GET(PCIE_BASE_CFG_SPEED, val); 1114 ret = fls(val); 1115 1116 return ret > 0 ? ret : -EINVAL; 1117 } 1118 1119 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) 1120 { 1121 int err, max_speed; 1122 1123 err = mtk_pcie_parse_port(pcie); 1124 if (err) 1125 return err; 1126 1127 /* 1128 * Deassert the line in order to avoid unbalance in deassert_count 1129 * counter since the bulk is shared. 1130 */ 1131 reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 1132 pcie->phy_resets); 1133 1134 /* Don't touch the hardware registers before power up */ 1135 err = pcie->soc->power_up(pcie); 1136 if (err) 1137 return err; 1138 1139 err = of_pci_get_max_link_speed(pcie->dev->of_node); 1140 if (err) { 1141 /* Get the maximum speed supported by the controller */ 1142 max_speed = mtk_pcie_get_controller_max_link_speed(pcie); 1143 1144 /* Set max_link_speed only if the controller supports it */ 1145 if (max_speed >= 0 && max_speed <= err) { 1146 pcie->max_link_speed = err; 1147 dev_info(pcie->dev, 1148 "maximum controller link speed Gen%d, overriding to Gen%u", 1149 max_speed, pcie->max_link_speed); 1150 } 1151 } 1152 1153 /* Try link up */ 1154 err = mtk_pcie_startup_port(pcie); 1155 if (err) 1156 goto err_setup; 1157 1158 err = mtk_pcie_setup_irq(pcie); 1159 if (err) 1160 goto err_setup; 1161 1162 return 0; 1163 1164 err_setup: 1165 mtk_pcie_power_down(pcie); 1166 1167 return err; 1168 } 1169 1170 static int mtk_pcie_probe(struct platform_device *pdev) 1171 { 1172 struct device *dev = &pdev->dev; 1173 struct mtk_gen3_pcie *pcie; 1174 struct pci_host_bridge *host; 1175 int err; 1176 1177 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1178 if (!host) 1179 return -ENOMEM; 1180 1181 pcie = pci_host_bridge_priv(host); 1182 1183 pcie->dev = dev; 1184 pcie->soc = device_get_match_data(dev); 1185 platform_set_drvdata(pdev, pcie); 1186 1187 err = mtk_pcie_setup(pcie); 1188 if (err) 1189 return err; 1190 1191 host->ops = &mtk_pcie_ops; 1192 host->sysdata = pcie; 1193 1194 err = pci_host_probe(host); 1195 if (err) { 1196 mtk_pcie_irq_teardown(pcie); 1197 mtk_pcie_power_down(pcie); 1198 return err; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static void mtk_pcie_remove(struct platform_device *pdev) 1205 { 1206 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev); 1207 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1208 1209 pci_lock_rescan_remove(); 1210 pci_stop_root_bus(host->bus); 1211 pci_remove_root_bus(host->bus); 1212 pci_unlock_rescan_remove(); 1213 1214 mtk_pcie_irq_teardown(pcie); 1215 mtk_pcie_power_down(pcie); 1216 } 1217 1218 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) 1219 { 1220 int i; 1221 1222 raw_spin_lock(&pcie->irq_lock); 1223 1224 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 1225 1226 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 1227 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 1228 1229 msi_set->saved_irq_state = readl_relaxed(msi_set->base + 1230 PCIE_MSI_SET_ENABLE_OFFSET); 1231 } 1232 1233 raw_spin_unlock(&pcie->irq_lock); 1234 } 1235 1236 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) 1237 { 1238 int i; 1239 1240 raw_spin_lock(&pcie->irq_lock); 1241 1242 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG); 1243 1244 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 1245 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 1246 1247 writel_relaxed(msi_set->saved_irq_state, 1248 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 1249 } 1250 1251 raw_spin_unlock(&pcie->irq_lock); 1252 } 1253 1254 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie) 1255 { 1256 u32 val; 1257 1258 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG); 1259 val |= PCIE_TURN_OFF_LINK; 1260 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG); 1261 1262 /* Check the link is L2 */ 1263 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val, 1264 (PCIE_LTSSM_STATE(val) == 1265 PCIE_LTSSM_STATE_L2_IDLE), 20, 1266 50 * USEC_PER_MSEC); 1267 } 1268 1269 static int mtk_pcie_suspend_noirq(struct device *dev) 1270 { 1271 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); 1272 int err; 1273 u32 val; 1274 1275 /* Trigger link to L2 state */ 1276 err = mtk_pcie_turn_off_link(pcie); 1277 if (err) { 1278 dev_err(pcie->dev, "cannot enter L2 state\n"); 1279 return err; 1280 } 1281 1282 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { 1283 /* Assert the PERST# pin */ 1284 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); 1285 val |= PCIE_PE_RSTB; 1286 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 1287 } 1288 1289 dev_dbg(pcie->dev, "entered L2 states successfully"); 1290 1291 mtk_pcie_irq_save(pcie); 1292 mtk_pcie_power_down(pcie); 1293 1294 return 0; 1295 } 1296 1297 static int mtk_pcie_resume_noirq(struct device *dev) 1298 { 1299 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); 1300 int err; 1301 1302 err = pcie->soc->power_up(pcie); 1303 if (err) 1304 return err; 1305 1306 err = mtk_pcie_startup_port(pcie); 1307 if (err) { 1308 mtk_pcie_power_down(pcie); 1309 return err; 1310 } 1311 1312 mtk_pcie_irq_restore(pcie); 1313 1314 return 0; 1315 } 1316 1317 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1318 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1319 mtk_pcie_resume_noirq) 1320 }; 1321 1322 static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { 1323 .power_up = mtk_pcie_power_up, 1324 .phy_resets = { 1325 .id[0] = "phy", 1326 .num_resets = 1, 1327 }, 1328 }; 1329 1330 static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { 1331 .power_up = mtk_pcie_en7581_power_up, 1332 .phy_resets = { 1333 .id[0] = "phy-lane0", 1334 .id[1] = "phy-lane1", 1335 .id[2] = "phy-lane2", 1336 .num_resets = 3, 1337 }, 1338 .flags = SKIP_PCIE_RSTB, 1339 }; 1340 1341 static const struct of_device_id mtk_pcie_of_match[] = { 1342 { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, 1343 { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, 1344 {}, 1345 }; 1346 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match); 1347 1348 static struct platform_driver mtk_pcie_driver = { 1349 .probe = mtk_pcie_probe, 1350 .remove = mtk_pcie_remove, 1351 .driver = { 1352 .name = "mtk-pcie-gen3", 1353 .of_match_table = mtk_pcie_of_match, 1354 .pm = &mtk_pcie_pm_ops, 1355 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1356 }, 1357 }; 1358 1359 module_platform_driver(mtk_pcie_driver); 1360 MODULE_DESCRIPTION("MediaTek Gen3 PCIe host controller driver"); 1361 MODULE_LICENSE("GPL v2"); 1362