1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2009 - 2019 Broadcom */ 3 4 #include <linux/bitfield.h> 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/compiler.h> 8 #include <linux/delay.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/list.h> 17 #include <linux/log2.h> 18 #include <linux/module.h> 19 #include <linux/msi.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_pci.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/printk.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/string.h> 29 #include <linux/types.h> 30 31 #include <soc/bcm2835/raspberrypi-firmware.h> 32 33 #include "../pci.h" 34 35 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ 36 #define BRCM_PCIE_CAP_REGS 0x00ac 37 38 /* Broadcom STB PCIe Register Offsets */ 39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc 41 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 42 43 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c 44 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff 45 46 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc 47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 48 49 #define PCIE_RC_DL_MDIO_ADDR 0x1100 50 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 51 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 52 53 #define PCIE_MISC_MISC_CTRL 0x4008 54 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 55 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 56 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 57 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 58 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 59 60 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c 61 #define PCIE_MEM_WIN0_LO(win) \ 62 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8) 63 64 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 65 #define PCIE_MEM_WIN0_HI(win) \ 66 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) 67 68 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c 69 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f 70 71 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 72 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f 73 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 74 75 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c 76 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f 77 78 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 79 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 80 81 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c 82 #define PCIE_MISC_MSI_DATA_CONFIG_VAL 0xffe06540 83 84 #define PCIE_MISC_PCIE_CTRL 0x4064 85 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 86 87 #define PCIE_MISC_PCIE_STATUS 0x4068 88 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 89 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 90 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 91 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 92 93 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 94 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 95 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 96 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \ 97 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) 98 99 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 100 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff 101 #define PCIE_MEM_WIN0_BASE_HI(win) \ 102 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) 103 104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 105 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff 106 #define PCIE_MEM_WIN0_LIMIT_HI(win) \ 107 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) 108 109 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 110 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 111 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 112 113 #define PCIE_MSI_INTR2_STATUS 0x4500 114 #define PCIE_MSI_INTR2_CLR 0x4508 115 #define PCIE_MSI_INTR2_MASK_SET 0x4510 116 #define PCIE_MSI_INTR2_MASK_CLR 0x4514 117 118 #define PCIE_EXT_CFG_DATA 0x8000 119 120 #define PCIE_EXT_CFG_INDEX 0x9000 121 #define PCIE_EXT_BUSNUM_SHIFT 20 122 #define PCIE_EXT_SLOT_SHIFT 15 123 #define PCIE_EXT_FUNC_SHIFT 12 124 125 #define PCIE_RGR1_SW_INIT_1 0x9210 126 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 127 #define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 128 129 /* PCIe parameters */ 130 #define BRCM_NUM_PCIE_OUT_WINS 0x4 131 #define BRCM_INT_PCI_MSI_NR 32 132 133 /* MSI target adresses */ 134 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL 135 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL 136 137 /* MDIO registers */ 138 #define MDIO_PORT0 0x0 139 #define MDIO_DATA_MASK 0x7fffffff 140 #define MDIO_PORT_MASK 0xf0000 141 #define MDIO_REGAD_MASK 0xffff 142 #define MDIO_CMD_MASK 0xfff00000 143 #define MDIO_CMD_READ 0x1 144 #define MDIO_CMD_WRITE 0x0 145 #define MDIO_DATA_DONE_MASK 0x80000000 146 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) 147 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) 148 #define SSC_REGS_ADDR 0x1100 149 #define SET_ADDR_OFFSET 0x1f 150 #define SSC_CNTL_OFFSET 0x2 151 #define SSC_CNTL_OVRD_EN_MASK 0x8000 152 #define SSC_CNTL_OVRD_VAL_MASK 0x4000 153 #define SSC_STATUS_OFFSET 0x1 154 #define SSC_STATUS_SSC_MASK 0x400 155 #define SSC_STATUS_PLL_LOCK_MASK 0x800 156 157 struct brcm_msi { 158 struct device *dev; 159 void __iomem *base; 160 struct device_node *np; 161 struct irq_domain *msi_domain; 162 struct irq_domain *inner_domain; 163 struct mutex lock; /* guards the alloc/free operations */ 164 u64 target_addr; 165 int irq; 166 /* used indicates which MSI interrupts have been alloc'd */ 167 unsigned long used; 168 }; 169 170 /* Internal PCIe Host Controller Information.*/ 171 struct brcm_pcie { 172 struct device *dev; 173 void __iomem *base; 174 struct clk *clk; 175 struct device_node *np; 176 bool ssc; 177 int gen; 178 u64 msi_target_addr; 179 struct brcm_msi *msi; 180 }; 181 182 /* 183 * This is to convert the size of the inbound "BAR" region to the 184 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE 185 */ 186 static int brcm_pcie_encode_ibar_size(u64 size) 187 { 188 int log2_in = ilog2(size); 189 190 if (log2_in >= 12 && log2_in <= 15) 191 /* Covers 4KB to 32KB (inclusive) */ 192 return (log2_in - 12) + 0x1c; 193 else if (log2_in >= 16 && log2_in <= 35) 194 /* Covers 64KB to 32GB, (inclusive) */ 195 return log2_in - 15; 196 /* Something is awry so disable */ 197 return 0; 198 } 199 200 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) 201 { 202 u32 pkt = 0; 203 204 pkt |= FIELD_PREP(MDIO_PORT_MASK, port); 205 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); 206 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); 207 208 return pkt; 209 } 210 211 /* negative return value indicates error */ 212 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) 213 { 214 int tries; 215 u32 data; 216 217 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), 218 base + PCIE_RC_DL_MDIO_ADDR); 219 readl(base + PCIE_RC_DL_MDIO_ADDR); 220 221 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 222 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { 223 udelay(10); 224 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); 225 } 226 227 *val = FIELD_GET(MDIO_DATA_MASK, data); 228 return MDIO_RD_DONE(data) ? 0 : -EIO; 229 } 230 231 /* negative return value indicates error */ 232 static int brcm_pcie_mdio_write(void __iomem *base, u8 port, 233 u8 regad, u16 wrdata) 234 { 235 int tries; 236 u32 data; 237 238 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), 239 base + PCIE_RC_DL_MDIO_ADDR); 240 readl(base + PCIE_RC_DL_MDIO_ADDR); 241 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); 242 243 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 244 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { 245 udelay(10); 246 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); 247 } 248 249 return MDIO_WT_DONE(data) ? 0 : -EIO; 250 } 251 252 /* 253 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative 254 * return value indicates error. 255 */ 256 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) 257 { 258 int pll, ssc; 259 int ret; 260 u32 tmp; 261 262 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 263 SSC_REGS_ADDR); 264 if (ret < 0) 265 return ret; 266 267 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 268 SSC_CNTL_OFFSET, &tmp); 269 if (ret < 0) 270 return ret; 271 272 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); 273 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); 274 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, 275 SSC_CNTL_OFFSET, tmp); 276 if (ret < 0) 277 return ret; 278 279 usleep_range(1000, 2000); 280 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, 281 SSC_STATUS_OFFSET, &tmp); 282 if (ret < 0) 283 return ret; 284 285 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); 286 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); 287 288 return ssc && pll ? 0 : -EIO; 289 } 290 291 /* Limits operation to a specific generation (1, 2, or 3) */ 292 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) 293 { 294 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 295 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 296 297 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; 298 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); 299 300 lnkctl2 = (lnkctl2 & ~0xf) | gen; 301 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); 302 } 303 304 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, 305 unsigned int win, u64 cpu_addr, 306 u64 pcie_addr, u64 size) 307 { 308 u32 cpu_addr_mb_high, limit_addr_mb_high; 309 phys_addr_t cpu_addr_mb, limit_addr_mb; 310 int high_addr_shift; 311 u32 tmp; 312 313 /* Set the base of the pcie_addr window */ 314 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); 315 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); 316 317 /* Write the addr base & limit lower bits (in MBs) */ 318 cpu_addr_mb = cpu_addr / SZ_1M; 319 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; 320 321 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 322 u32p_replace_bits(&tmp, cpu_addr_mb, 323 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 324 u32p_replace_bits(&tmp, limit_addr_mb, 325 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); 326 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); 327 328 /* Write the cpu & limit addr upper bits */ 329 high_addr_shift = 330 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); 331 332 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift; 333 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 334 u32p_replace_bits(&tmp, cpu_addr_mb_high, 335 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); 336 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); 337 338 limit_addr_mb_high = limit_addr_mb >> high_addr_shift; 339 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 340 u32p_replace_bits(&tmp, limit_addr_mb_high, 341 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); 342 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); 343 } 344 345 static struct irq_chip brcm_msi_irq_chip = { 346 .name = "BRCM STB PCIe MSI", 347 .irq_ack = irq_chip_ack_parent, 348 .irq_mask = pci_msi_mask_irq, 349 .irq_unmask = pci_msi_unmask_irq, 350 }; 351 352 static struct msi_domain_info brcm_msi_domain_info = { 353 /* Multi MSI is supported by the controller, but not by this driver */ 354 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 355 .chip = &brcm_msi_irq_chip, 356 }; 357 358 static void brcm_pcie_msi_isr(struct irq_desc *desc) 359 { 360 struct irq_chip *chip = irq_desc_get_chip(desc); 361 unsigned long status, virq; 362 struct brcm_msi *msi; 363 struct device *dev; 364 u32 bit; 365 366 chained_irq_enter(chip, desc); 367 msi = irq_desc_get_handler_data(desc); 368 dev = msi->dev; 369 370 status = readl(msi->base + PCIE_MSI_INTR2_STATUS); 371 for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) { 372 virq = irq_find_mapping(msi->inner_domain, bit); 373 if (virq) 374 generic_handle_irq(virq); 375 else 376 dev_dbg(dev, "unexpected MSI\n"); 377 } 378 379 chained_irq_exit(chip, desc); 380 } 381 382 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 383 { 384 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 385 386 msg->address_lo = lower_32_bits(msi->target_addr); 387 msg->address_hi = upper_32_bits(msi->target_addr); 388 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL) | data->hwirq; 389 } 390 391 static int brcm_msi_set_affinity(struct irq_data *irq_data, 392 const struct cpumask *mask, bool force) 393 { 394 return -EINVAL; 395 } 396 397 static void brcm_msi_ack_irq(struct irq_data *data) 398 { 399 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); 400 401 writel(1 << data->hwirq, msi->base + PCIE_MSI_INTR2_CLR); 402 } 403 404 405 static struct irq_chip brcm_msi_bottom_irq_chip = { 406 .name = "BRCM STB MSI", 407 .irq_compose_msi_msg = brcm_msi_compose_msi_msg, 408 .irq_set_affinity = brcm_msi_set_affinity, 409 .irq_ack = brcm_msi_ack_irq, 410 }; 411 412 static int brcm_msi_alloc(struct brcm_msi *msi) 413 { 414 int hwirq; 415 416 mutex_lock(&msi->lock); 417 hwirq = bitmap_find_free_region(&msi->used, BRCM_INT_PCI_MSI_NR, 0); 418 mutex_unlock(&msi->lock); 419 420 return hwirq; 421 } 422 423 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) 424 { 425 mutex_lock(&msi->lock); 426 bitmap_release_region(&msi->used, hwirq, 0); 427 mutex_unlock(&msi->lock); 428 } 429 430 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 431 unsigned int nr_irqs, void *args) 432 { 433 struct brcm_msi *msi = domain->host_data; 434 int hwirq; 435 436 hwirq = brcm_msi_alloc(msi); 437 438 if (hwirq < 0) 439 return hwirq; 440 441 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, 442 &brcm_msi_bottom_irq_chip, domain->host_data, 443 handle_edge_irq, NULL, NULL); 444 return 0; 445 } 446 447 static void brcm_irq_domain_free(struct irq_domain *domain, 448 unsigned int virq, unsigned int nr_irqs) 449 { 450 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 451 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); 452 453 brcm_msi_free(msi, d->hwirq); 454 } 455 456 static const struct irq_domain_ops msi_domain_ops = { 457 .alloc = brcm_irq_domain_alloc, 458 .free = brcm_irq_domain_free, 459 }; 460 461 static int brcm_allocate_domains(struct brcm_msi *msi) 462 { 463 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); 464 struct device *dev = msi->dev; 465 466 msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR, 467 &msi_domain_ops, msi); 468 if (!msi->inner_domain) { 469 dev_err(dev, "failed to create IRQ domain\n"); 470 return -ENOMEM; 471 } 472 473 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 474 &brcm_msi_domain_info, 475 msi->inner_domain); 476 if (!msi->msi_domain) { 477 dev_err(dev, "failed to create MSI domain\n"); 478 irq_domain_remove(msi->inner_domain); 479 return -ENOMEM; 480 } 481 482 return 0; 483 } 484 485 static void brcm_free_domains(struct brcm_msi *msi) 486 { 487 irq_domain_remove(msi->msi_domain); 488 irq_domain_remove(msi->inner_domain); 489 } 490 491 static void brcm_msi_remove(struct brcm_pcie *pcie) 492 { 493 struct brcm_msi *msi = pcie->msi; 494 495 if (!msi) 496 return; 497 irq_set_chained_handler(msi->irq, NULL); 498 irq_set_handler_data(msi->irq, NULL); 499 brcm_free_domains(msi); 500 } 501 502 static void brcm_msi_set_regs(struct brcm_msi *msi) 503 { 504 writel(0xffffffff, msi->base + PCIE_MSI_INTR2_MASK_CLR); 505 506 /* 507 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI 508 * enable, which we set to 1. 509 */ 510 writel(lower_32_bits(msi->target_addr) | 0x1, 511 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); 512 writel(upper_32_bits(msi->target_addr), 513 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); 514 515 writel(PCIE_MISC_MSI_DATA_CONFIG_VAL, 516 msi->base + PCIE_MISC_MSI_DATA_CONFIG); 517 } 518 519 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) 520 { 521 struct brcm_msi *msi; 522 int irq, ret; 523 struct device *dev = pcie->dev; 524 525 irq = irq_of_parse_and_map(dev->of_node, 1); 526 if (irq <= 0) { 527 dev_err(dev, "cannot map MSI interrupt\n"); 528 return -ENODEV; 529 } 530 531 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); 532 if (!msi) 533 return -ENOMEM; 534 535 mutex_init(&msi->lock); 536 msi->dev = dev; 537 msi->base = pcie->base; 538 msi->np = pcie->np; 539 msi->target_addr = pcie->msi_target_addr; 540 msi->irq = irq; 541 542 ret = brcm_allocate_domains(msi); 543 if (ret) 544 return ret; 545 546 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); 547 548 brcm_msi_set_regs(msi); 549 pcie->msi = msi; 550 551 return 0; 552 } 553 554 /* The controller is capable of serving in both RC and EP roles */ 555 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) 556 { 557 void __iomem *base = pcie->base; 558 u32 val = readl(base + PCIE_MISC_PCIE_STATUS); 559 560 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); 561 } 562 563 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) 564 { 565 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); 566 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); 567 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); 568 569 return dla && plu; 570 } 571 572 /* Configuration space read/write support */ 573 static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) 574 { 575 return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) 576 | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) 577 | (busnr << PCIE_EXT_BUSNUM_SHIFT) 578 | (reg & ~3); 579 } 580 581 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, 582 int where) 583 { 584 struct brcm_pcie *pcie = bus->sysdata; 585 void __iomem *base = pcie->base; 586 int idx; 587 588 /* Accesses to the RC go right to the RC registers if slot==0 */ 589 if (pci_is_root_bus(bus)) 590 return PCI_SLOT(devfn) ? NULL : base + where; 591 592 /* For devices, write to the config space index register */ 593 idx = brcm_pcie_cfg_index(bus->number, devfn, 0); 594 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); 595 return base + PCIE_EXT_CFG_DATA + where; 596 } 597 598 static struct pci_ops brcm_pcie_ops = { 599 .map_bus = brcm_pcie_map_conf, 600 .read = pci_generic_config_read, 601 .write = pci_generic_config_write, 602 }; 603 604 static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) 605 { 606 u32 tmp; 607 608 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); 609 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); 610 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); 611 } 612 613 static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) 614 { 615 u32 tmp; 616 617 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); 618 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); 619 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); 620 } 621 622 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, 623 u64 *rc_bar2_size, 624 u64 *rc_bar2_offset) 625 { 626 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 627 struct device *dev = pcie->dev; 628 struct resource_entry *entry; 629 630 entry = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); 631 if (!entry) 632 return -ENODEV; 633 634 635 /* 636 * The controller expects the inbound window offset to be calculated as 637 * the difference between PCIe's address space and CPU's. The offset 638 * provided by the firmware is calculated the opposite way, so we 639 * negate it. 640 */ 641 *rc_bar2_offset = -entry->offset; 642 *rc_bar2_size = 1ULL << fls64(entry->res->end - entry->res->start); 643 644 /* 645 * We validate the inbound memory view even though we should trust 646 * whatever the device-tree provides. This is because of an HW issue on 647 * early Raspberry Pi 4's revisions (bcm2711). It turns out its 648 * firmware has to dynamically edit dma-ranges due to a bug on the 649 * PCIe controller integration, which prohibits any access above the 650 * lower 3GB of memory. Given this, we decided to keep the dma-ranges 651 * in check, avoiding hard to debug device-tree related issues in the 652 * future: 653 * 654 * The PCIe host controller by design must set the inbound viewport to 655 * be a contiguous arrangement of all of the system's memory. In 656 * addition, its size mut be a power of two. To further complicate 657 * matters, the viewport must start on a pcie-address that is aligned 658 * on a multiple of its size. If a portion of the viewport does not 659 * represent system memory -- e.g. 3GB of memory requires a 4GB 660 * viewport -- we can map the outbound memory in or after 3GB and even 661 * though the viewport will overlap the outbound memory the controller 662 * will know to send outbound memory downstream and everything else 663 * upstream. 664 * 665 * For example: 666 * 667 * - The best-case scenario, memory up to 3GB, is to place the inbound 668 * region in the first 4GB of pcie-space, as some legacy devices can 669 * only address 32bits. We would also like to put the MSI under 4GB 670 * as well, since some devices require a 32bit MSI target address. 671 * 672 * - If the system memory is 4GB or larger we cannot start the inbound 673 * region at location 0 (since we have to allow some space for 674 * outbound memory @ 3GB). So instead it will start at the 1x 675 * multiple of its size 676 */ 677 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || 678 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { 679 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", 680 *rc_bar2_size, *rc_bar2_offset); 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static int brcm_pcie_setup(struct brcm_pcie *pcie) 688 { 689 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 690 u64 rc_bar2_offset, rc_bar2_size; 691 void __iomem *base = pcie->base; 692 struct device *dev = pcie->dev; 693 struct resource_entry *entry; 694 unsigned int scb_size_val; 695 bool ssc_good = false; 696 struct resource *res; 697 int num_out_wins = 0; 698 u16 nlw, cls, lnksta; 699 int i, ret; 700 u32 tmp, aspm_support; 701 702 /* Reset the bridge */ 703 brcm_pcie_bridge_sw_init_set(pcie, 1); 704 brcm_pcie_perst_set(pcie, 1); 705 706 usleep_range(100, 200); 707 708 /* Take the bridge out of reset */ 709 brcm_pcie_bridge_sw_init_set(pcie, 0); 710 711 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 712 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; 713 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 714 /* Wait for SerDes to be stable */ 715 usleep_range(100, 200); 716 717 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ 718 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); 719 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); 720 u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, 721 PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); 722 writel(tmp, base + PCIE_MISC_MISC_CTRL); 723 724 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, 725 &rc_bar2_offset); 726 if (ret) 727 return ret; 728 729 tmp = lower_32_bits(rc_bar2_offset); 730 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), 731 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); 732 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); 733 writel(upper_32_bits(rc_bar2_offset), 734 base + PCIE_MISC_RC_BAR2_CONFIG_HI); 735 736 scb_size_val = rc_bar2_size ? 737 ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ 738 tmp = readl(base + PCIE_MISC_MISC_CTRL); 739 u32p_replace_bits(&tmp, scb_size_val, 740 PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); 741 writel(tmp, base + PCIE_MISC_MISC_CTRL); 742 743 /* 744 * We ideally want the MSI target address to be located in the 32bit 745 * addressable memory area. Some devices might depend on it. This is 746 * possible either when the inbound window is located above the lower 747 * 4GB or when the inbound area is smaller than 4GB (taking into 748 * account the rounding-up we're forced to perform). 749 */ 750 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) 751 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; 752 else 753 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; 754 755 /* disable the PCIe->GISB memory window (RC_BAR1) */ 756 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); 757 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; 758 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); 759 760 /* disable the PCIe->SCB memory window (RC_BAR3) */ 761 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); 762 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; 763 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); 764 765 /* Mask all interrupts since we are not handling any yet */ 766 writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_MASK_SET); 767 768 /* clear any interrupts we find on boot */ 769 writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_CLR); 770 771 if (pcie->gen) 772 brcm_pcie_set_gen(pcie, pcie->gen); 773 774 /* Unassert the fundamental reset */ 775 brcm_pcie_perst_set(pcie, 0); 776 777 /* 778 * Give the RC/EP time to wake up, before trying to configure RC. 779 * Intermittently check status for link-up, up to a total of 100ms. 780 */ 781 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) 782 msleep(5); 783 784 if (!brcm_pcie_link_up(pcie)) { 785 dev_err(dev, "link down\n"); 786 return -ENODEV; 787 } 788 789 if (!brcm_pcie_rc_mode(pcie)) { 790 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); 791 return -EINVAL; 792 } 793 794 resource_list_for_each_entry(entry, &bridge->windows) { 795 res = entry->res; 796 797 if (resource_type(res) != IORESOURCE_MEM) 798 continue; 799 800 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) { 801 dev_err(pcie->dev, "too many outbound wins\n"); 802 return -EINVAL; 803 } 804 805 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, 806 res->start - entry->offset, 807 resource_size(res)); 808 num_out_wins++; 809 } 810 811 /* Don't advertise L0s capability if 'aspm-no-l0s' */ 812 aspm_support = PCIE_LINK_STATE_L1; 813 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) 814 aspm_support |= PCIE_LINK_STATE_L0S; 815 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 816 u32p_replace_bits(&tmp, aspm_support, 817 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); 818 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); 819 820 /* 821 * For config space accesses on the RC, show the right class for 822 * a PCIe-PCIe bridge (the default setting is to be EP mode). 823 */ 824 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); 825 u32p_replace_bits(&tmp, 0x060400, 826 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); 827 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); 828 829 if (pcie->ssc) { 830 ret = brcm_pcie_set_ssc(pcie); 831 if (ret == 0) 832 ssc_good = true; 833 else 834 dev_err(dev, "failed attempt to enter ssc mode\n"); 835 } 836 837 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); 838 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); 839 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); 840 dev_info(dev, "link up, %s x%u %s\n", 841 pci_speed_string(pcie_link_speed[cls]), nlw, 842 ssc_good ? "(SSC)" : "(!SSC)"); 843 844 /* PCIe->SCB endian mode for BAR */ 845 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 846 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, 847 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); 848 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); 849 850 /* 851 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 852 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. 853 */ 854 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 855 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; 856 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 857 858 return 0; 859 } 860 861 /* L23 is a low-power PCIe link state */ 862 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) 863 { 864 void __iomem *base = pcie->base; 865 int l23, i; 866 u32 tmp; 867 868 /* Assert request for L23 */ 869 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 870 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 871 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 872 873 /* Wait up to 36 msec for L23 */ 874 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 875 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp); 876 for (i = 0; i < 15 && !l23; i++) { 877 usleep_range(2000, 2400); 878 tmp = readl(base + PCIE_MISC_PCIE_STATUS); 879 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, 880 tmp); 881 } 882 883 if (!l23) 884 dev_err(pcie->dev, "failed to enter low-power link state\n"); 885 } 886 887 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) 888 { 889 void __iomem *base = pcie->base; 890 int tmp; 891 892 if (brcm_pcie_link_up(pcie)) 893 brcm_pcie_enter_l23(pcie); 894 /* Assert fundamental reset */ 895 brcm_pcie_perst_set(pcie, 1); 896 897 /* Deassert request for L23 in case it was asserted */ 898 tmp = readl(base + PCIE_MISC_PCIE_CTRL); 899 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); 900 writel(tmp, base + PCIE_MISC_PCIE_CTRL); 901 902 /* Turn off SerDes */ 903 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 904 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); 905 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); 906 907 /* Shutdown PCIe bridge */ 908 brcm_pcie_bridge_sw_init_set(pcie, 1); 909 } 910 911 static void __brcm_pcie_remove(struct brcm_pcie *pcie) 912 { 913 brcm_msi_remove(pcie); 914 brcm_pcie_turn_off(pcie); 915 clk_disable_unprepare(pcie->clk); 916 } 917 918 static int brcm_pcie_remove(struct platform_device *pdev) 919 { 920 struct brcm_pcie *pcie = platform_get_drvdata(pdev); 921 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 922 923 pci_stop_root_bus(bridge->bus); 924 pci_remove_root_bus(bridge->bus); 925 __brcm_pcie_remove(pcie); 926 927 return 0; 928 } 929 930 static int brcm_pcie_probe(struct platform_device *pdev) 931 { 932 struct device_node *np = pdev->dev.of_node, *msi_np; 933 struct pci_host_bridge *bridge; 934 struct device_node *fw_np; 935 struct brcm_pcie *pcie; 936 int ret; 937 938 /* 939 * We have to wait for Raspberry Pi's firmware interface to be up as a 940 * PCI fixup, rpi_firmware_init_vl805(), depends on it. This driver's 941 * probe can race with the firmware interface's (see 942 * drivers/firmware/raspberrypi.c) and potentially break the PCI fixup. 943 */ 944 fw_np = of_find_compatible_node(NULL, NULL, 945 "raspberrypi,bcm2835-firmware"); 946 if (fw_np && !rpi_firmware_get(fw_np)) { 947 of_node_put(fw_np); 948 return -EPROBE_DEFER; 949 } 950 of_node_put(fw_np); 951 952 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); 953 if (!bridge) 954 return -ENOMEM; 955 956 pcie = pci_host_bridge_priv(bridge); 957 pcie->dev = &pdev->dev; 958 pcie->np = np; 959 960 pcie->base = devm_platform_ioremap_resource(pdev, 0); 961 if (IS_ERR(pcie->base)) 962 return PTR_ERR(pcie->base); 963 964 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); 965 if (IS_ERR(pcie->clk)) 966 return PTR_ERR(pcie->clk); 967 968 ret = of_pci_get_max_link_speed(np); 969 pcie->gen = (ret < 0) ? 0 : ret; 970 971 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); 972 973 ret = clk_prepare_enable(pcie->clk); 974 if (ret) { 975 dev_err(&pdev->dev, "could not enable clock\n"); 976 return ret; 977 } 978 979 ret = brcm_pcie_setup(pcie); 980 if (ret) 981 goto fail; 982 983 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); 984 if (pci_msi_enabled() && msi_np == pcie->np) { 985 ret = brcm_pcie_enable_msi(pcie); 986 if (ret) { 987 dev_err(pcie->dev, "probe of internal MSI failed"); 988 goto fail; 989 } 990 } 991 992 bridge->ops = &brcm_pcie_ops; 993 bridge->sysdata = pcie; 994 995 platform_set_drvdata(pdev, pcie); 996 997 return pci_host_probe(bridge); 998 fail: 999 __brcm_pcie_remove(pcie); 1000 return ret; 1001 } 1002 1003 static const struct of_device_id brcm_pcie_match[] = { 1004 { .compatible = "brcm,bcm2711-pcie" }, 1005 {}, 1006 }; 1007 MODULE_DEVICE_TABLE(of, brcm_pcie_match); 1008 1009 static struct platform_driver brcm_pcie_driver = { 1010 .probe = brcm_pcie_probe, 1011 .remove = brcm_pcie_remove, 1012 .driver = { 1013 .name = "brcm-pcie", 1014 .of_match_table = brcm_pcie_match, 1015 }, 1016 }; 1017 module_platform_driver(brcm_pcie_driver); 1018 1019 MODULE_LICENSE("GPL"); 1020 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver"); 1021 MODULE_AUTHOR("Broadcom"); 1022