1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * APM X-Gene PCIe Driver 4 * 5 * Copyright (c) 2014 Applied Micro Circuits Corporation. 6 * 7 * Author: Tanmay Inamdar <tinamdar@apm.com>. 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/memblock.h> 14 #include <linux/init.h> 15 #include <linux/irqdomain.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_pci.h> 19 #include <linux/pci.h> 20 #include <linux/pci-acpi.h> 21 #include <linux/pci-ecam.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 25 #include "../pci.h" 26 27 #define PCIECORE_CTLANDSTATUS 0x50 28 #define PIM1_1L 0x80 29 #define IBAR2 0x98 30 #define IR2MSK 0x9c 31 #define PIM2_1L 0xa0 32 #define IBAR3L 0xb4 33 #define IR3MSKL 0xbc 34 #define PIM3_1L 0xc4 35 #define OMR1BARL 0x100 36 #define OMR2BARL 0x118 37 #define OMR3BARL 0x130 38 #define CFGBARL 0x154 39 #define CFGBARH 0x158 40 #define CFGCTL 0x15c 41 #define RTDID 0x160 42 #define BRIDGE_CFG_0 0x2000 43 #define BRIDGE_CFG_4 0x2010 44 #define BRIDGE_STATUS_0 0x2600 45 46 #define LINK_UP_MASK 0x00000100 47 #define AXI_EP_CFG_ACCESS 0x10000 48 #define EN_COHERENCY 0xF0000000 49 #define EN_REG 0x00000001 50 #define OB_LO_IO 0x00000002 51 #define XGENE_PCIE_DEVICEID 0xE004 52 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) 53 54 #define XGENE_V1_PCI_EXP_CAP 0x40 55 56 /* PCIe IP version */ 57 #define XGENE_PCIE_IP_VER_1 1 58 #define XGENE_PCIE_IP_VER_2 2 59 60 struct xgene_pcie { 61 struct device *dev; 62 struct clk *clk; 63 void __iomem *csr_base; 64 void __iomem *cfg_base; 65 unsigned long cfg_addr; 66 bool link_up; 67 u32 version; 68 }; 69 70 static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg) 71 { 72 return readl(port->csr_base + reg); 73 } 74 75 static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val) 76 { 77 writel(val, port->csr_base + reg); 78 } 79 80 static inline u32 pcie_bar_low_val(u32 addr, u32 flags) 81 { 82 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; 83 } 84 85 static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus) 86 { 87 struct pci_config_window *cfg; 88 89 if (acpi_disabled) 90 return (struct xgene_pcie *)(bus->sysdata); 91 92 cfg = bus->sysdata; 93 return (struct xgene_pcie *)(cfg->priv); 94 } 95 96 /* 97 * When the address bit [17:16] is 2'b01, the Configuration access will be 98 * treated as Type 1 and it will be forwarded to external PCIe device. 99 */ 100 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) 101 { 102 struct xgene_pcie *port = pcie_bus_to_port(bus); 103 104 if (bus->number >= (bus->primary + 1)) 105 return port->cfg_base + AXI_EP_CFG_ACCESS; 106 107 return port->cfg_base; 108 } 109 110 /* 111 * For Configuration request, RTDID register is used as Bus Number, 112 * Device Number and Function number of the header fields. 113 */ 114 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) 115 { 116 struct xgene_pcie *port = pcie_bus_to_port(bus); 117 unsigned int b, d, f; 118 u32 rtdid_val = 0; 119 120 b = bus->number; 121 d = PCI_SLOT(devfn); 122 f = PCI_FUNC(devfn); 123 124 if (!pci_is_root_bus(bus)) 125 rtdid_val = (b << 8) | (d << 3) | f; 126 127 xgene_pcie_writel(port, RTDID, rtdid_val); 128 /* read the register back to ensure flush */ 129 xgene_pcie_readl(port, RTDID); 130 } 131 132 /* 133 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as 134 * the translation from PCI bus to native BUS. Entire DDR region 135 * is mapped into PCIe space using these registers, so it can be 136 * reached by DMA from EP devices. The BAR0/1 of bridge should be 137 * hidden during enumeration to avoid the sizing and resource allocation 138 * by PCIe core. 139 */ 140 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) 141 { 142 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || 143 (offset == PCI_BASE_ADDRESS_1))) 144 return true; 145 146 return false; 147 } 148 149 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 150 int offset) 151 { 152 if ((pci_is_root_bus(bus) && devfn != 0) || 153 xgene_pcie_hide_rc_bars(bus, offset)) 154 return NULL; 155 156 xgene_pcie_set_rtdid_reg(bus, devfn); 157 return xgene_pcie_get_cfg_base(bus) + offset; 158 } 159 160 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, 161 int where, int size, u32 *val) 162 { 163 struct xgene_pcie *port = pcie_bus_to_port(bus); 164 int ret; 165 166 ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val); 167 if (ret != PCIBIOS_SUCCESSFUL) 168 return ret; 169 170 /* 171 * The v1 controller has a bug in its Configuration Request Retry 172 * Status (RRS) logic: when RRS Software Visibility is enabled and 173 * we read the Vendor and Device ID of a non-existent device, the 174 * controller fabricates return data of 0xFFFF0001 ("device exists 175 * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE) 176 * ("device does not exist"). This causes the PCI core to retry 177 * the read until it times out. Avoid this by not claiming to 178 * support RRS SV. 179 */ 180 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && 181 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) 182 *val &= ~(PCI_EXP_RTCAP_RRS_SV << 16); 183 184 if (size <= 2) 185 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 186 187 return PCIBIOS_SUCCESSFUL; 188 } 189 190 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) 191 static int xgene_get_csr_resource(struct acpi_device *adev, 192 struct resource *res) 193 { 194 struct device *dev = &adev->dev; 195 struct resource_entry *entry; 196 struct list_head list; 197 unsigned long flags; 198 int ret; 199 200 INIT_LIST_HEAD(&list); 201 flags = IORESOURCE_MEM; 202 ret = acpi_dev_get_resources(adev, &list, 203 acpi_dev_filter_resource_type_cb, 204 (void *) flags); 205 if (ret < 0) { 206 dev_err(dev, "failed to parse _CRS method, error code %d\n", 207 ret); 208 return ret; 209 } 210 211 if (ret == 0) { 212 dev_err(dev, "no IO and memory resources present in _CRS\n"); 213 return -EINVAL; 214 } 215 216 entry = list_first_entry(&list, struct resource_entry, node); 217 *res = *entry->res; 218 acpi_dev_free_resource_list(&list); 219 return 0; 220 } 221 222 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) 223 { 224 struct device *dev = cfg->parent; 225 struct acpi_device *adev = to_acpi_device(dev); 226 struct xgene_pcie *port; 227 struct resource csr; 228 int ret; 229 230 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 231 if (!port) 232 return -ENOMEM; 233 234 ret = xgene_get_csr_resource(adev, &csr); 235 if (ret) { 236 dev_err(dev, "can't get CSR resource\n"); 237 return ret; 238 } 239 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); 240 if (IS_ERR(port->csr_base)) 241 return PTR_ERR(port->csr_base); 242 243 port->cfg_base = cfg->win; 244 port->version = ipversion; 245 246 cfg->priv = port; 247 return 0; 248 } 249 250 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) 251 { 252 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); 253 } 254 255 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { 256 .init = xgene_v1_pcie_ecam_init, 257 .pci_ops = { 258 .map_bus = xgene_pcie_map_bus, 259 .read = xgene_pcie_config_read32, 260 .write = pci_generic_config_write, 261 } 262 }; 263 264 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) 265 { 266 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); 267 } 268 269 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { 270 .init = xgene_v2_pcie_ecam_init, 271 .pci_ops = { 272 .map_bus = xgene_pcie_map_bus, 273 .read = xgene_pcie_config_read32, 274 .write = pci_generic_config_write, 275 } 276 }; 277 #endif 278 279 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr, 280 u32 flags, u64 size) 281 { 282 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; 283 u32 val32 = 0; 284 u32 val; 285 286 val32 = xgene_pcie_readl(port, addr); 287 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); 288 xgene_pcie_writel(port, addr, val); 289 290 val32 = xgene_pcie_readl(port, addr + 0x04); 291 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); 292 xgene_pcie_writel(port, addr + 0x04, val); 293 294 val32 = xgene_pcie_readl(port, addr + 0x04); 295 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); 296 xgene_pcie_writel(port, addr + 0x04, val); 297 298 val32 = xgene_pcie_readl(port, addr + 0x08); 299 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); 300 xgene_pcie_writel(port, addr + 0x08, val); 301 302 return mask; 303 } 304 305 static void xgene_pcie_linkup(struct xgene_pcie *port, 306 u32 *lanes, u32 *speed) 307 { 308 u32 val32; 309 310 port->link_up = false; 311 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS); 312 if (val32 & LINK_UP_MASK) { 313 port->link_up = true; 314 *speed = PIPE_PHY_RATE_RD(val32); 315 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0); 316 *lanes = val32 >> 26; 317 } 318 } 319 320 static int xgene_pcie_init_port(struct xgene_pcie *port) 321 { 322 struct device *dev = port->dev; 323 int rc; 324 325 port->clk = clk_get(dev, NULL); 326 if (IS_ERR(port->clk)) { 327 dev_err(dev, "clock not available\n"); 328 return -ENODEV; 329 } 330 331 rc = clk_prepare_enable(port->clk); 332 if (rc) { 333 dev_err(dev, "clock enable failed\n"); 334 return rc; 335 } 336 337 return 0; 338 } 339 340 static int xgene_pcie_map_reg(struct xgene_pcie *port, 341 struct platform_device *pdev) 342 { 343 struct device *dev = port->dev; 344 struct resource *res; 345 346 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); 347 port->csr_base = devm_pci_remap_cfg_resource(dev, res); 348 if (IS_ERR(port->csr_base)) 349 return PTR_ERR(port->csr_base); 350 351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 352 port->cfg_base = devm_ioremap_resource(dev, res); 353 if (IS_ERR(port->cfg_base)) 354 return PTR_ERR(port->cfg_base); 355 port->cfg_addr = res->start; 356 357 return 0; 358 } 359 360 static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port, 361 struct resource *res, u32 offset, 362 u64 cpu_addr, u64 pci_addr) 363 { 364 struct device *dev = port->dev; 365 resource_size_t size = resource_size(res); 366 u64 restype = resource_type(res); 367 u64 mask = 0; 368 u32 min_size; 369 u32 flag = EN_REG; 370 371 if (restype == IORESOURCE_MEM) { 372 min_size = SZ_128M; 373 } else { 374 min_size = 128; 375 flag |= OB_LO_IO; 376 } 377 378 if (size >= min_size) 379 mask = ~(size - 1) | flag; 380 else 381 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", 382 (u64)size, min_size); 383 384 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); 385 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); 386 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); 387 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); 388 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); 389 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); 390 } 391 392 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port) 393 { 394 u64 addr = port->cfg_addr; 395 396 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); 397 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); 398 xgene_pcie_writel(port, CFGCTL, EN_REG); 399 } 400 401 static int xgene_pcie_map_ranges(struct xgene_pcie *port) 402 { 403 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); 404 struct resource_entry *window; 405 struct device *dev = port->dev; 406 407 resource_list_for_each_entry(window, &bridge->windows) { 408 struct resource *res = window->res; 409 u64 restype = resource_type(res); 410 411 dev_dbg(dev, "%pR\n", res); 412 413 switch (restype) { 414 case IORESOURCE_IO: 415 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, 416 pci_pio_to_address(res->start), 417 res->start - window->offset); 418 break; 419 case IORESOURCE_MEM: 420 if (res->flags & IORESOURCE_PREFETCH) 421 xgene_pcie_setup_ob_reg(port, res, OMR2BARL, 422 res->start, 423 res->start - 424 window->offset); 425 else 426 xgene_pcie_setup_ob_reg(port, res, OMR1BARL, 427 res->start, 428 res->start - 429 window->offset); 430 break; 431 case IORESOURCE_BUS: 432 break; 433 default: 434 dev_err(dev, "invalid resource %pR\n", res); 435 return -EINVAL; 436 } 437 } 438 xgene_pcie_setup_cfg_reg(port); 439 return 0; 440 } 441 442 static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg, 443 u64 pim, u64 size) 444 { 445 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); 446 xgene_pcie_writel(port, pim_reg + 0x04, 447 upper_32_bits(pim) | EN_COHERENCY); 448 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); 449 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); 450 } 451 452 /* 453 * X-Gene PCIe support maximum 3 inbound memory regions 454 * This function helps to select a region based on size of region 455 */ 456 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) 457 { 458 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { 459 *ib_reg_mask |= (1 << 1); 460 return 1; 461 } 462 463 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { 464 *ib_reg_mask |= (1 << 0); 465 return 0; 466 } 467 468 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { 469 *ib_reg_mask |= (1 << 2); 470 return 2; 471 } 472 473 return -EINVAL; 474 } 475 476 static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port, 477 struct of_pci_range *range, u8 *ib_reg_mask) 478 { 479 void __iomem *cfg_base = port->cfg_base; 480 struct device *dev = port->dev; 481 void __iomem *bar_addr; 482 u32 pim_reg; 483 u64 cpu_addr = range->cpu_addr; 484 u64 pci_addr = range->pci_addr; 485 u64 size = range->size; 486 u64 mask = ~(size - 1) | EN_REG; 487 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; 488 u32 bar_low; 489 int region; 490 491 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); 492 if (region < 0) { 493 dev_warn(dev, "invalid pcie dma-range config\n"); 494 return; 495 } 496 497 if (range->flags & IORESOURCE_PREFETCH) 498 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; 499 500 bar_low = pcie_bar_low_val((u32)cpu_addr, flags); 501 switch (region) { 502 case 0: 503 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); 504 bar_addr = cfg_base + PCI_BASE_ADDRESS_0; 505 writel(bar_low, bar_addr); 506 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); 507 pim_reg = PIM1_1L; 508 break; 509 case 1: 510 xgene_pcie_writel(port, IBAR2, bar_low); 511 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); 512 pim_reg = PIM2_1L; 513 break; 514 case 2: 515 xgene_pcie_writel(port, IBAR3L, bar_low); 516 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); 517 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); 518 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); 519 pim_reg = PIM3_1L; 520 break; 521 } 522 523 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); 524 } 525 526 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port) 527 { 528 struct device_node *np = port->dev->of_node; 529 struct of_pci_range range; 530 struct of_pci_range_parser parser; 531 struct device *dev = port->dev; 532 u8 ib_reg_mask = 0; 533 534 if (of_pci_dma_range_parser_init(&parser, np)) { 535 dev_err(dev, "missing dma-ranges property\n"); 536 return -EINVAL; 537 } 538 539 /* Get the dma-ranges from DT */ 540 for_each_of_pci_range(&parser, &range) { 541 u64 end = range.cpu_addr + range.size - 1; 542 543 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", 544 range.flags, range.cpu_addr, end, range.pci_addr); 545 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); 546 } 547 return 0; 548 } 549 550 /* clear BAR configuration which was done by firmware */ 551 static void xgene_pcie_clear_config(struct xgene_pcie *port) 552 { 553 int i; 554 555 for (i = PIM1_1L; i <= CFGCTL; i += 4) 556 xgene_pcie_writel(port, i, 0); 557 } 558 559 static int xgene_pcie_setup(struct xgene_pcie *port) 560 { 561 struct device *dev = port->dev; 562 u32 val, lanes = 0, speed = 0; 563 int ret; 564 565 xgene_pcie_clear_config(port); 566 567 /* setup the vendor and device IDs correctly */ 568 val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC; 569 xgene_pcie_writel(port, BRIDGE_CFG_0, val); 570 571 ret = xgene_pcie_map_ranges(port); 572 if (ret) 573 return ret; 574 575 ret = xgene_pcie_parse_map_dma_ranges(port); 576 if (ret) 577 return ret; 578 579 xgene_pcie_linkup(port, &lanes, &speed); 580 if (!port->link_up) 581 dev_info(dev, "(rc) link down\n"); 582 else 583 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); 584 return 0; 585 } 586 587 static struct pci_ops xgene_pcie_ops = { 588 .map_bus = xgene_pcie_map_bus, 589 .read = xgene_pcie_config_read32, 590 .write = pci_generic_config_write32, 591 }; 592 593 static bool xgene_check_pcie_msi_ready(void) 594 { 595 struct device_node *np; 596 struct irq_domain *d; 597 598 if (!IS_ENABLED(CONFIG_PCI_XGENE_MSI)) 599 return true; 600 601 np = of_find_compatible_node(NULL, NULL, "apm,xgene1-msi"); 602 if (!np) 603 return true; 604 605 d = irq_find_matching_host(np, DOMAIN_BUS_PCI_MSI); 606 of_node_put(np); 607 608 return d && irq_domain_is_msi_parent(d); 609 } 610 611 static int xgene_pcie_probe(struct platform_device *pdev) 612 { 613 struct device *dev = &pdev->dev; 614 struct xgene_pcie *port; 615 struct pci_host_bridge *bridge; 616 int ret; 617 618 if (!xgene_check_pcie_msi_ready()) 619 return dev_err_probe(&pdev->dev, -EPROBE_DEFER, 620 "MSI driver not ready\n"); 621 622 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); 623 if (!bridge) 624 return -ENOMEM; 625 626 port = pci_host_bridge_priv(bridge); 627 628 port->dev = dev; 629 port->version = XGENE_PCIE_IP_VER_1; 630 631 ret = xgene_pcie_map_reg(port, pdev); 632 if (ret) 633 return ret; 634 635 ret = xgene_pcie_init_port(port); 636 if (ret) 637 return ret; 638 639 ret = xgene_pcie_setup(port); 640 if (ret) 641 return ret; 642 643 bridge->sysdata = port; 644 bridge->ops = &xgene_pcie_ops; 645 646 return pci_host_probe(bridge); 647 } 648 649 static const struct of_device_id xgene_pcie_match_table[] = { 650 {.compatible = "apm,xgene-pcie",}, 651 {}, 652 }; 653 654 static struct platform_driver xgene_pcie_driver = { 655 .driver = { 656 .name = "xgene-pcie", 657 .of_match_table = xgene_pcie_match_table, 658 .suppress_bind_attrs = true, 659 }, 660 .probe = xgene_pcie_probe, 661 }; 662 builtin_platform_driver(xgene_pcie_driver); 663