1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * Based on the code from arch/arm/mach-integrator/pci_v3.c 7 * Copyright (C) 1999 ARM Limited 8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd 9 * 10 * Contributors to the old driver include: 11 * Russell King <linux@armlinux.org.uk> 12 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite) 13 * Rob Herring <robh@kernel.org> 14 * Liviu Dudau <Liviu.Dudau@arm.com> 15 * Grant Likely <grant.likely@secretlab.ca> 16 * Arnd Bergmann <arnd@arndb.de> 17 * Bjorn Helgaas <bhelgaas@google.com> 18 */ 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_pci.h> 26 #include <linux/pci.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <linux/bitops.h> 30 #include <linux/irq.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/regmap.h> 33 #include <linux/clk.h> 34 35 #include "../pci.h" 36 37 #define V3_PCI_VENDOR 0x00000000 38 #define V3_PCI_DEVICE 0x00000002 39 #define V3_PCI_CMD 0x00000004 40 #define V3_PCI_STAT 0x00000006 41 #define V3_PCI_CC_REV 0x00000008 42 #define V3_PCI_HDR_CFG 0x0000000C 43 #define V3_PCI_IO_BASE 0x00000010 44 #define V3_PCI_BASE0 0x00000014 45 #define V3_PCI_BASE1 0x00000018 46 #define V3_PCI_SUB_VENDOR 0x0000002C 47 #define V3_PCI_SUB_ID 0x0000002E 48 #define V3_PCI_ROM 0x00000030 49 #define V3_PCI_BPARAM 0x0000003C 50 #define V3_PCI_MAP0 0x00000040 51 #define V3_PCI_MAP1 0x00000044 52 #define V3_PCI_INT_STAT 0x00000048 53 #define V3_PCI_INT_CFG 0x0000004C 54 #define V3_LB_BASE0 0x00000054 55 #define V3_LB_BASE1 0x00000058 56 #define V3_LB_MAP0 0x0000005E 57 #define V3_LB_MAP1 0x00000062 58 #define V3_LB_BASE2 0x00000064 59 #define V3_LB_MAP2 0x00000066 60 #define V3_LB_SIZE 0x00000068 61 #define V3_LB_IO_BASE 0x0000006E 62 #define V3_FIFO_CFG 0x00000070 63 #define V3_FIFO_PRIORITY 0x00000072 64 #define V3_FIFO_STAT 0x00000074 65 #define V3_LB_ISTAT 0x00000076 66 #define V3_LB_IMASK 0x00000077 67 #define V3_SYSTEM 0x00000078 68 #define V3_LB_CFG 0x0000007A 69 #define V3_PCI_CFG 0x0000007C 70 #define V3_DMA_PCI_ADR0 0x00000080 71 #define V3_DMA_PCI_ADR1 0x00000090 72 #define V3_DMA_LOCAL_ADR0 0x00000084 73 #define V3_DMA_LOCAL_ADR1 0x00000094 74 #define V3_DMA_LENGTH0 0x00000088 75 #define V3_DMA_LENGTH1 0x00000098 76 #define V3_DMA_CSR0 0x0000008B 77 #define V3_DMA_CSR1 0x0000009B 78 #define V3_DMA_CTLB_ADR0 0x0000008C 79 #define V3_DMA_CTLB_ADR1 0x0000009C 80 #define V3_DMA_DELAY 0x000000E0 81 #define V3_MAIL_DATA 0x000000C0 82 #define V3_PCI_MAIL_IEWR 0x000000D0 83 #define V3_PCI_MAIL_IERD 0x000000D2 84 #define V3_LB_MAIL_IEWR 0x000000D4 85 #define V3_LB_MAIL_IERD 0x000000D6 86 #define V3_MAIL_WR_STAT 0x000000D8 87 #define V3_MAIL_RD_STAT 0x000000DA 88 #define V3_QBA_MAP 0x000000DC 89 90 /* PCI STATUS bits */ 91 #define V3_PCI_STAT_PAR_ERR BIT(15) 92 #define V3_PCI_STAT_SYS_ERR BIT(14) 93 #define V3_PCI_STAT_M_ABORT_ERR BIT(13) 94 #define V3_PCI_STAT_T_ABORT_ERR BIT(12) 95 96 /* LB ISTAT bits */ 97 #define V3_LB_ISTAT_MAILBOX BIT(7) 98 #define V3_LB_ISTAT_PCI_RD BIT(6) 99 #define V3_LB_ISTAT_PCI_WR BIT(5) 100 #define V3_LB_ISTAT_PCI_INT BIT(4) 101 #define V3_LB_ISTAT_PCI_PERR BIT(3) 102 #define V3_LB_ISTAT_I2O_QWR BIT(2) 103 #define V3_LB_ISTAT_DMA1 BIT(1) 104 #define V3_LB_ISTAT_DMA0 BIT(0) 105 106 /* PCI COMMAND bits */ 107 #define V3_COMMAND_M_FBB_EN BIT(9) 108 #define V3_COMMAND_M_SERR_EN BIT(8) 109 #define V3_COMMAND_M_PAR_EN BIT(6) 110 #define V3_COMMAND_M_MASTER_EN BIT(2) 111 #define V3_COMMAND_M_MEM_EN BIT(1) 112 #define V3_COMMAND_M_IO_EN BIT(0) 113 114 /* SYSTEM bits */ 115 #define V3_SYSTEM_M_RST_OUT BIT(15) 116 #define V3_SYSTEM_M_LOCK BIT(14) 117 #define V3_SYSTEM_UNLOCK 0xa05f 118 119 /* PCI CFG bits */ 120 #define V3_PCI_CFG_M_I2O_EN BIT(15) 121 #define V3_PCI_CFG_M_IO_REG_DIS BIT(14) 122 #define V3_PCI_CFG_M_IO_DIS BIT(13) 123 #define V3_PCI_CFG_M_EN3V BIT(12) 124 #define V3_PCI_CFG_M_RETRY_EN BIT(10) 125 #define V3_PCI_CFG_M_AD_LOW1 BIT(9) 126 #define V3_PCI_CFG_M_AD_LOW0 BIT(8) 127 /* 128 * This is the value applied to C/BE[3:1], with bit 0 always held 0 129 * during DMA access. 130 */ 131 #define V3_PCI_CFG_M_RTYPE_SHIFT 5 132 #define V3_PCI_CFG_M_WTYPE_SHIFT 1 133 #define V3_PCI_CFG_TYPE_DEFAULT 0x3 134 135 /* PCI BASE bits (PCI -> Local Bus) */ 136 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U 137 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U 138 #define V3_PCI_BASE_M_PREFETCH BIT(3) 139 #define V3_PCI_BASE_M_TYPE (3 << 1) 140 #define V3_PCI_BASE_M_IO BIT(0) 141 142 /* PCI MAP bits (PCI -> Local bus) */ 143 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U 144 #define V3_PCI_MAP_M_RD_POST_INH BIT(15) 145 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) 146 #define V3_PCI_MAP_M_SWAP (3 << 8) 147 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U 148 #define V3_PCI_MAP_M_REG_EN BIT(1) 149 #define V3_PCI_MAP_M_ENABLE BIT(0) 150 151 /* LB_BASE0,1 bits (Local bus -> PCI) */ 152 #define V3_LB_BASE_ADR_BASE 0xfff00000U 153 #define V3_LB_BASE_SWAP (3 << 8) 154 #define V3_LB_BASE_ADR_SIZE (15 << 4) 155 #define V3_LB_BASE_PREFETCH BIT(3) 156 #define V3_LB_BASE_ENABLE BIT(0) 157 158 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) 159 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) 160 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) 161 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) 162 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) 163 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) 164 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) 165 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) 166 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) 167 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) 168 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) 169 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) 170 171 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) 172 173 /* LB_MAP0,1 bits (Local bus -> PCI) */ 174 #define V3_LB_MAP_MAP_ADR 0xfff0U 175 #define V3_LB_MAP_TYPE (7 << 1) 176 #define V3_LB_MAP_AD_LOW_EN BIT(0) 177 178 #define V3_LB_MAP_TYPE_IACK (0 << 1) 179 #define V3_LB_MAP_TYPE_IO (1 << 1) 180 #define V3_LB_MAP_TYPE_MEM (3 << 1) 181 #define V3_LB_MAP_TYPE_CONFIG (5 << 1) 182 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) 183 184 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) 185 186 /* LB_BASE2 bits (Local bus -> PCI IO) */ 187 #define V3_LB_BASE2_ADR_BASE 0xff00U 188 #define V3_LB_BASE2_SWAP_AUTO (3 << 6) 189 #define V3_LB_BASE2_ENABLE BIT(0) 190 191 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) 192 193 /* LB_MAP2 bits (Local bus -> PCI IO) */ 194 #define V3_LB_MAP2_MAP_ADR 0xff00U 195 196 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) 197 198 /* FIFO priority bits */ 199 #define V3_FIFO_PRIO_LOCAL BIT(12) 200 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10) 201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11) 202 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11)) 203 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8) 204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9) 205 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9)) 206 #define V3_FIFO_PRIO_PCI BIT(4) 207 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2) 208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3) 209 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3)) 210 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0) 211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1) 212 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1)) 213 214 /* Local bus configuration bits */ 215 #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000 216 #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13) 217 #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14) 218 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14)) 219 #define V3_LB_CFG_LB_RST BIT(12) 220 #define V3_LB_CFG_LB_PPC_RDY BIT(11) 221 #define V3_LB_CFG_LB_LB_INT BIT(10) 222 #define V3_LB_CFG_LB_ERR_EN BIT(9) 223 #define V3_LB_CFG_LB_RDY_EN BIT(8) 224 #define V3_LB_CFG_LB_BE_IMODE BIT(7) 225 #define V3_LB_CFG_LB_BE_OMODE BIT(6) 226 #define V3_LB_CFG_LB_ENDIAN BIT(5) 227 #define V3_LB_CFG_LB_PARK_EN BIT(4) 228 #define V3_LB_CFG_LB_FBB_DIS BIT(2) 229 230 /* ARM Integrator-specific extended control registers */ 231 #define INTEGRATOR_SC_PCI_OFFSET 0x18 232 #define INTEGRATOR_SC_PCI_ENABLE BIT(0) 233 #define INTEGRATOR_SC_PCI_INTCLR BIT(1) 234 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20 235 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24 236 237 struct v3_pci { 238 struct device *dev; 239 void __iomem *base; 240 void __iomem *config_base; 241 u32 config_mem; 242 u32 non_pre_mem; 243 u32 pre_mem; 244 phys_addr_t non_pre_bus_addr; 245 phys_addr_t pre_bus_addr; 246 struct regmap *map; 247 }; 248 249 /* 250 * The V3 PCI interface chip in Integrator provides several windows from 251 * local bus memory into the PCI memory areas. Unfortunately, there 252 * are not really enough windows for our usage, therefore we reuse 253 * one of the windows for access to PCI configuration space. On the 254 * Integrator/AP, the memory map is as follows: 255 * 256 * Local Bus Memory Usage 257 * 258 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable 259 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable 260 * 60000000 - 60FFFFFF PCI IO. 16M 261 * 61000000 - 61FFFFFF PCI Configuration. 16M 262 * 263 * There are three V3 windows, each described by a pair of V3 registers. 264 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. 265 * Base0 and Base1 can be used for any type of PCI memory access. Base2 266 * can be used either for PCI I/O or for I20 accesses. By default, uHAL 267 * uses this only for PCI IO space. 268 * 269 * Normally these spaces are mapped using the following base registers: 270 * 271 * Usage Local Bus Memory Base/Map registers used 272 * 273 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 274 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 275 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 276 * Cfg 61000000 - 61FFFFFF 277 * 278 * This means that I20 and PCI configuration space accesses will fail. 279 * When PCI configuration accesses are needed (via the uHAL PCI 280 * configuration space primitives) we must remap the spaces as follows: 281 * 282 * Usage Local Bus Memory Base/Map registers used 283 * 284 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 285 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 286 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 287 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 288 * 289 * To make this work, the code depends on overlapping windows working. 290 * The V3 chip translates an address by checking its range within 291 * each of the BASE/MAP pairs in turn (in ascending register number 292 * order). It will use the first matching pair. So, for example, 293 * if the same address is mapped by both LB_BASE0/LB_MAP0 and 294 * LB_BASE1/LB_MAP1, the V3 will use the translation from 295 * LB_BASE0/LB_MAP0. 296 * 297 * To allow PCI Configuration space access, the code enlarges the 298 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes 299 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can 300 * be remapped for use by configuration cycles. 301 * 302 * At the end of the PCI Configuration space accesses, 303 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window 304 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to 305 * reveal the now restored LB_BASE1/LB_MAP1 window. 306 * 307 * NOTE: We do not set up I2O mapping. I suspect that this is only 308 * for an intelligent (target) device. Using I2O disables most of 309 * the mappings into PCI memory. 310 */ 311 static void __iomem *v3_map_bus(struct pci_bus *bus, 312 unsigned int devfn, int offset) 313 { 314 struct v3_pci *v3 = bus->sysdata; 315 unsigned int address, mapaddress, busnr; 316 317 busnr = bus->number; 318 if (busnr == 0) { 319 int slot = PCI_SLOT(devfn); 320 321 /* 322 * local bus segment so need a type 0 config cycle 323 * 324 * build the PCI configuration "address" with one-hot in 325 * A31-A11 326 * 327 * mapaddress: 328 * 3:1 = config cycle (101) 329 * 0 = PCI A1 & A0 are 0 (0) 330 */ 331 address = PCI_FUNC(devfn) << 8; 332 mapaddress = V3_LB_MAP_TYPE_CONFIG; 333 334 if (slot > 12) 335 /* 336 * high order bits are handled by the MAP register 337 */ 338 mapaddress |= BIT(slot - 5); 339 else 340 /* 341 * low order bits handled directly in the address 342 */ 343 address |= BIT(slot + 11); 344 } else { 345 /* 346 * not the local bus segment so need a type 1 config cycle 347 * 348 * address: 349 * 23:16 = bus number 350 * 15:11 = slot number (7:3 of devfn) 351 * 10:8 = func number (2:0 of devfn) 352 * 353 * mapaddress: 354 * 3:1 = config cycle (101) 355 * 0 = PCI A1 & A0 from host bus (1) 356 */ 357 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; 358 address = (busnr << 16) | (devfn << 8); 359 } 360 361 /* 362 * Set up base0 to see all 512Mbytes of memory space (not 363 * prefetchable), this frees up base1 for re-use by 364 * configuration memory 365 */ 366 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 367 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE, 368 v3->base + V3_LB_BASE0); 369 370 /* 371 * Set up base1/map1 to point into configuration space. 372 * The config mem is always 16MB. 373 */ 374 writel(v3_addr_to_lb_base(v3->config_mem) | 375 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE, 376 v3->base + V3_LB_BASE1); 377 writew(mapaddress, v3->base + V3_LB_MAP1); 378 379 return v3->config_base + address + offset; 380 } 381 382 static void v3_unmap_bus(struct v3_pci *v3) 383 { 384 /* 385 * Reassign base1 for use by prefetchable PCI memory 386 */ 387 writel(v3_addr_to_lb_base(v3->pre_mem) | 388 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 389 V3_LB_BASE_ENABLE, 390 v3->base + V3_LB_BASE1); 391 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 392 V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 393 v3->base + V3_LB_MAP1); 394 395 /* 396 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 397 */ 398 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 399 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE, 400 v3->base + V3_LB_BASE0); 401 } 402 403 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn, 404 int config, int size, u32 *value) 405 { 406 struct v3_pci *v3 = bus->sysdata; 407 int ret; 408 409 dev_dbg(&bus->dev, 410 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 411 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); 412 ret = pci_generic_config_read(bus, fn, config, size, value); 413 v3_unmap_bus(v3); 414 return ret; 415 } 416 417 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn, 418 int config, int size, u32 value) 419 { 420 struct v3_pci *v3 = bus->sysdata; 421 int ret; 422 423 dev_dbg(&bus->dev, 424 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 425 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); 426 ret = pci_generic_config_write(bus, fn, config, size, value); 427 v3_unmap_bus(v3); 428 return ret; 429 } 430 431 static struct pci_ops v3_pci_ops = { 432 .map_bus = v3_map_bus, 433 .read = v3_pci_read_config, 434 .write = v3_pci_write_config, 435 }; 436 437 static irqreturn_t v3_irq(int irq, void *data) 438 { 439 struct v3_pci *v3 = data; 440 struct device *dev = v3->dev; 441 u32 status; 442 443 status = readw(v3->base + V3_PCI_STAT); 444 if (status & V3_PCI_STAT_PAR_ERR) 445 dev_err(dev, "parity error interrupt\n"); 446 if (status & V3_PCI_STAT_SYS_ERR) 447 dev_err(dev, "system error interrupt\n"); 448 if (status & V3_PCI_STAT_M_ABORT_ERR) 449 dev_err(dev, "master abort error interrupt\n"); 450 if (status & V3_PCI_STAT_T_ABORT_ERR) 451 dev_err(dev, "target abort error interrupt\n"); 452 writew(status, v3->base + V3_PCI_STAT); 453 454 status = readb(v3->base + V3_LB_ISTAT); 455 if (status & V3_LB_ISTAT_MAILBOX) 456 dev_info(dev, "PCI mailbox interrupt\n"); 457 if (status & V3_LB_ISTAT_PCI_RD) 458 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n"); 459 if (status & V3_LB_ISTAT_PCI_WR) 460 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n"); 461 if (status & V3_LB_ISTAT_PCI_INT) 462 dev_info(dev, "PCI pin interrupt\n"); 463 if (status & V3_LB_ISTAT_PCI_PERR) 464 dev_err(dev, "PCI parity error interrupt\n"); 465 if (status & V3_LB_ISTAT_I2O_QWR) 466 dev_info(dev, "I2O inbound post queue interrupt\n"); 467 if (status & V3_LB_ISTAT_DMA1) 468 dev_info(dev, "DMA channel 1 interrupt\n"); 469 if (status & V3_LB_ISTAT_DMA0) 470 dev_info(dev, "DMA channel 0 interrupt\n"); 471 /* Clear all possible interrupts on the local bus */ 472 writeb(0, v3->base + V3_LB_ISTAT); 473 if (v3->map) 474 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 475 INTEGRATOR_SC_PCI_ENABLE | 476 INTEGRATOR_SC_PCI_INTCLR); 477 478 return IRQ_HANDLED; 479 } 480 481 static int v3_integrator_init(struct v3_pci *v3) 482 { 483 unsigned int val; 484 485 v3->map = 486 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon"); 487 if (IS_ERR(v3->map)) { 488 dev_err(v3->dev, "no syscon\n"); 489 return -ENODEV; 490 } 491 492 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); 493 /* Take the PCI bridge out of reset, clear IRQs */ 494 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, 495 INTEGRATOR_SC_PCI_ENABLE | 496 INTEGRATOR_SC_PCI_INTCLR); 497 498 if (!(val & INTEGRATOR_SC_PCI_ENABLE)) { 499 /* If we were in reset we need to sleep a bit */ 500 msleep(230); 501 502 /* Set the physical base for the controller itself */ 503 writel(0x6200, v3->base + V3_LB_IO_BASE); 504 505 /* Wait for the mailbox to settle after reset */ 506 do { 507 writeb(0xaa, v3->base + V3_MAIL_DATA); 508 writeb(0x55, v3->base + V3_MAIL_DATA + 4); 509 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && 510 readb(v3->base + V3_MAIL_DATA) != 0x55); 511 } 512 513 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); 514 515 return 0; 516 } 517 518 static int v3_pci_setup_resource(struct v3_pci *v3, 519 struct pci_host_bridge *host, 520 struct resource_entry *win) 521 { 522 struct device *dev = v3->dev; 523 struct resource *mem; 524 struct resource *io; 525 526 switch (resource_type(win->res)) { 527 case IORESOURCE_IO: 528 io = win->res; 529 530 /* Setup window 2 - PCI I/O */ 531 writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) | 532 V3_LB_BASE2_ENABLE, 533 v3->base + V3_LB_BASE2); 534 writew(v3_addr_to_lb_map2(io->start - win->offset), 535 v3->base + V3_LB_MAP2); 536 break; 537 case IORESOURCE_MEM: 538 mem = win->res; 539 if (mem->flags & IORESOURCE_PREFETCH) { 540 mem->name = "V3 PCI PRE-MEM"; 541 v3->pre_mem = mem->start; 542 v3->pre_bus_addr = mem->start - win->offset; 543 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n", 544 mem, &v3->pre_bus_addr); 545 if (resource_size(mem) != SZ_256M) { 546 dev_err(dev, "prefetchable memory range is not 256MB\n"); 547 return -EINVAL; 548 } 549 if (v3->non_pre_mem && 550 (mem->start != v3->non_pre_mem + SZ_256M)) { 551 dev_err(dev, 552 "prefetchable memory is not adjacent to non-prefetchable memory\n"); 553 return -EINVAL; 554 } 555 /* Setup window 1 - PCI prefetchable memory */ 556 writel(v3_addr_to_lb_base(v3->pre_mem) | 557 V3_LB_BASE_ADR_SIZE_256MB | 558 V3_LB_BASE_PREFETCH | 559 V3_LB_BASE_ENABLE, 560 v3->base + V3_LB_BASE1); 561 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | 562 V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */ 563 v3->base + V3_LB_MAP1); 564 } else { 565 mem->name = "V3 PCI NON-PRE-MEM"; 566 v3->non_pre_mem = mem->start; 567 v3->non_pre_bus_addr = mem->start - win->offset; 568 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n", 569 mem, &v3->non_pre_bus_addr); 570 if (resource_size(mem) != SZ_256M) { 571 dev_err(dev, 572 "non-prefetchable memory range is not 256MB\n"); 573 return -EINVAL; 574 } 575 /* Setup window 0 - PCI non-prefetchable memory */ 576 writel(v3_addr_to_lb_base(v3->non_pre_mem) | 577 V3_LB_BASE_ADR_SIZE_256MB | 578 V3_LB_BASE_ENABLE, 579 v3->base + V3_LB_BASE0); 580 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | 581 V3_LB_MAP_TYPE_MEM, 582 v3->base + V3_LB_MAP0); 583 } 584 break; 585 case IORESOURCE_BUS: 586 break; 587 default: 588 dev_info(dev, "Unknown resource type %lu\n", 589 resource_type(win->res)); 590 break; 591 } 592 593 return 0; 594 } 595 596 static int v3_get_dma_range_config(struct v3_pci *v3, 597 struct resource_entry *entry, 598 u32 *pci_base, u32 *pci_map) 599 { 600 struct device *dev = v3->dev; 601 u64 cpu_addr = entry->res->start; 602 u64 cpu_end = entry->res->end; 603 u64 pci_end = cpu_end - entry->offset; 604 u64 pci_addr = entry->res->start - entry->offset; 605 u32 val; 606 607 if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { 608 dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n"); 609 return -EINVAL; 610 } 611 val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE; 612 *pci_base = val; 613 614 if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { 615 dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n"); 616 return -EINVAL; 617 } 618 val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR; 619 620 switch (resource_size(entry->res)) { 621 case SZ_1M: 622 val |= V3_LB_BASE_ADR_SIZE_1MB; 623 break; 624 case SZ_2M: 625 val |= V3_LB_BASE_ADR_SIZE_2MB; 626 break; 627 case SZ_4M: 628 val |= V3_LB_BASE_ADR_SIZE_4MB; 629 break; 630 case SZ_8M: 631 val |= V3_LB_BASE_ADR_SIZE_8MB; 632 break; 633 case SZ_16M: 634 val |= V3_LB_BASE_ADR_SIZE_16MB; 635 break; 636 case SZ_32M: 637 val |= V3_LB_BASE_ADR_SIZE_32MB; 638 break; 639 case SZ_64M: 640 val |= V3_LB_BASE_ADR_SIZE_64MB; 641 break; 642 case SZ_128M: 643 val |= V3_LB_BASE_ADR_SIZE_128MB; 644 break; 645 case SZ_256M: 646 val |= V3_LB_BASE_ADR_SIZE_256MB; 647 break; 648 case SZ_512M: 649 val |= V3_LB_BASE_ADR_SIZE_512MB; 650 break; 651 case SZ_1G: 652 val |= V3_LB_BASE_ADR_SIZE_1GB; 653 break; 654 case SZ_2G: 655 val |= V3_LB_BASE_ADR_SIZE_2GB; 656 break; 657 default: 658 dev_err(v3->dev, "illegal dma memory chunk size\n"); 659 return -EINVAL; 660 } 661 val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE; 662 *pci_map = val; 663 664 dev_dbg(dev, 665 "DMA MEM CPU: 0x%016llx -> 0x%016llx => " 666 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", 667 cpu_addr, cpu_end, 668 pci_addr, pci_end, 669 *pci_base, *pci_map); 670 671 return 0; 672 } 673 674 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3, 675 struct device_node *np) 676 { 677 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3); 678 struct device *dev = v3->dev; 679 struct resource_entry *entry; 680 int i = 0; 681 682 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 683 int ret; 684 u32 pci_base, pci_map; 685 686 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map); 687 if (ret) 688 return ret; 689 690 if (i == 0) { 691 writel(pci_base, v3->base + V3_PCI_BASE0); 692 writel(pci_map, v3->base + V3_PCI_MAP0); 693 } else if (i == 1) { 694 writel(pci_base, v3->base + V3_PCI_BASE1); 695 writel(pci_map, v3->base + V3_PCI_MAP1); 696 } else { 697 dev_err(dev, "too many ranges, only two supported\n"); 698 dev_err(dev, "range %d ignored\n", i); 699 } 700 i++; 701 } 702 return 0; 703 } 704 705 static int v3_pci_probe(struct platform_device *pdev) 706 { 707 struct device *dev = &pdev->dev; 708 struct device_node *np = dev->of_node; 709 struct resource *regs; 710 struct resource_entry *win; 711 struct v3_pci *v3; 712 struct pci_host_bridge *host; 713 struct clk *clk; 714 u16 val; 715 int irq; 716 int ret; 717 718 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3)); 719 if (!host) 720 return -ENOMEM; 721 722 host->ops = &v3_pci_ops; 723 v3 = pci_host_bridge_priv(host); 724 host->sysdata = v3; 725 v3->dev = dev; 726 727 /* Get and enable host clock */ 728 clk = devm_clk_get(dev, NULL); 729 if (IS_ERR(clk)) { 730 dev_err(dev, "clock not found\n"); 731 return PTR_ERR(clk); 732 } 733 ret = clk_prepare_enable(clk); 734 if (ret) { 735 dev_err(dev, "unable to enable clock\n"); 736 return ret; 737 } 738 739 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 740 v3->base = devm_ioremap_resource(dev, regs); 741 if (IS_ERR(v3->base)) 742 return PTR_ERR(v3->base); 743 /* 744 * The hardware has a register with the physical base address 745 * of the V3 controller itself, verify that this is the same 746 * as the physical memory we've remapped it from. 747 */ 748 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) 749 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n", 750 readl(v3->base + V3_LB_IO_BASE), regs); 751 752 /* Configuration space is 16MB directly mapped */ 753 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 754 if (resource_size(regs) != SZ_16M) { 755 dev_err(dev, "config mem is not 16MB!\n"); 756 return -EINVAL; 757 } 758 v3->config_mem = regs->start; 759 v3->config_base = devm_ioremap_resource(dev, regs); 760 if (IS_ERR(v3->config_base)) 761 return PTR_ERR(v3->config_base); 762 763 /* Get and request error IRQ resource */ 764 irq = platform_get_irq(pdev, 0); 765 if (irq < 0) 766 return irq; 767 768 ret = devm_request_irq(dev, irq, v3_irq, 0, 769 "PCIv3 error", v3); 770 if (ret < 0) { 771 dev_err(dev, 772 "unable to request PCIv3 error IRQ %d (%d)\n", 773 irq, ret); 774 return ret; 775 } 776 777 /* 778 * Unlock V3 registers, but only if they were previously locked. 779 */ 780 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) 781 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); 782 783 /* Disable all slave access while we set up the windows */ 784 val = readw(v3->base + V3_PCI_CMD); 785 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 786 writew(val, v3->base + V3_PCI_CMD); 787 788 /* Put the PCI bus into reset */ 789 val = readw(v3->base + V3_SYSTEM); 790 val &= ~V3_SYSTEM_M_RST_OUT; 791 writew(val, v3->base + V3_SYSTEM); 792 793 /* Retry until we're ready */ 794 val = readw(v3->base + V3_PCI_CFG); 795 val |= V3_PCI_CFG_M_RETRY_EN; 796 writew(val, v3->base + V3_PCI_CFG); 797 798 /* Set up the local bus protocol */ 799 val = readw(v3->base + V3_LB_CFG); 800 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */ 801 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */ 802 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */ 803 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */ 804 writew(val, v3->base + V3_LB_CFG); 805 806 /* Enable the PCI bus master */ 807 val = readw(v3->base + V3_PCI_CMD); 808 val |= PCI_COMMAND_MASTER; 809 writew(val, v3->base + V3_PCI_CMD); 810 811 /* Get the I/O and memory ranges from DT */ 812 resource_list_for_each_entry(win, &host->windows) { 813 ret = v3_pci_setup_resource(v3, host, win); 814 if (ret) { 815 dev_err(dev, "error setting up resources\n"); 816 return ret; 817 } 818 } 819 ret = v3_pci_parse_map_dma_ranges(v3, np); 820 if (ret) 821 return ret; 822 823 /* 824 * Disable PCI to host IO cycles, enable I/O buffers @3.3V, 825 * set AD_LOW0 to 1 if one of the LB_MAP registers choose 826 * to use this (should be unused). 827 */ 828 writel(0x00000000, v3->base + V3_PCI_IO_BASE); 829 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS | 830 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0; 831 /* 832 * DMA read and write from PCI bus commands types 833 */ 834 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT; 835 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT; 836 writew(val, v3->base + V3_PCI_CFG); 837 838 /* 839 * Set the V3 FIFO such that writes have higher priority than 840 * reads, and local bus write causes local bus read fifo flush 841 * on aperture 1. Same for PCI. 842 */ 843 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 | 844 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 | 845 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 | 846 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1, 847 v3->base + V3_FIFO_PRIORITY); 848 849 850 /* 851 * Clear any error interrupts, and enable parity and write error 852 * interrupts 853 */ 854 writeb(0, v3->base + V3_LB_ISTAT); 855 val = readw(v3->base + V3_LB_CFG); 856 val |= V3_LB_CFG_LB_LB_INT; 857 writew(val, v3->base + V3_LB_CFG); 858 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 859 v3->base + V3_LB_IMASK); 860 861 /* Special Integrator initialization */ 862 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { 863 ret = v3_integrator_init(v3); 864 if (ret) 865 return ret; 866 } 867 868 /* Post-init: enable PCI memory and invalidate (master already on) */ 869 val = readw(v3->base + V3_PCI_CMD); 870 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE; 871 writew(val, v3->base + V3_PCI_CMD); 872 873 /* Clear pending interrupts */ 874 writeb(0, v3->base + V3_LB_ISTAT); 875 /* Read or write errors and parity errors cause interrupts */ 876 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 877 v3->base + V3_LB_IMASK); 878 879 /* Take the PCI bus out of reset so devices can initialize */ 880 val = readw(v3->base + V3_SYSTEM); 881 val |= V3_SYSTEM_M_RST_OUT; 882 writew(val, v3->base + V3_SYSTEM); 883 884 /* 885 * Re-lock the system register. 886 */ 887 val = readw(v3->base + V3_SYSTEM); 888 val |= V3_SYSTEM_M_LOCK; 889 writew(val, v3->base + V3_SYSTEM); 890 891 return pci_host_probe(host); 892 } 893 894 static const struct of_device_id v3_pci_of_match[] = { 895 { 896 .compatible = "v3,v360epc-pci", 897 }, 898 {}, 899 }; 900 901 static struct platform_driver v3_pci_driver = { 902 .driver = { 903 .name = "pci-v3-semi", 904 .of_match_table = v3_pci_of_match, 905 .suppress_bind_attrs = true, 906 }, 907 .probe = v3_pci_probe, 908 }; 909 builtin_platform_driver(v3_pci_driver); 910