1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015 - 2016 Cavium, Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/kernel.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/of_address.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci-acpi.h> 13 #include <linux/pci-ecam.h> 14 #include <linux/platform_device.h> 15 #include "../pci.h" 16 17 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) 18 19 #define PEM_CFG_WR 0x28 20 #define PEM_CFG_RD 0x30 21 22 struct thunder_pem_pci { 23 u32 ea_entry[3]; 24 void __iomem *pem_reg_base; 25 }; 26 27 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn, 28 int where, int size, u32 *val) 29 { 30 u64 read_val, tmp_val; 31 struct pci_config_window *cfg = bus->sysdata; 32 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; 33 34 if (devfn != 0 || where >= 2048) { 35 *val = ~0; 36 return PCIBIOS_DEVICE_NOT_FOUND; 37 } 38 39 /* 40 * 32-bit accesses only. Write the address to the low order 41 * bits of PEM_CFG_RD, then trigger the read by reading back. 42 * The config data lands in the upper 32-bits of PEM_CFG_RD. 43 */ 44 read_val = where & ~3ull; 45 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD); 46 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); 47 read_val >>= 32; 48 49 /* 50 * The config space contains some garbage, fix it up. Also 51 * synthesize an EA capability for the BAR used by MSI-X. 52 */ 53 switch (where & ~3) { 54 case 0x40: 55 read_val &= 0xffff00ff; 56 read_val |= 0x00007000; /* Skip MSI CAP */ 57 break; 58 case 0x70: /* Express Cap */ 59 /* 60 * Change PME interrupt to vector 2 on T88 where it 61 * reads as 0, else leave it alone. 62 */ 63 if (!(read_val & (0x1f << 25))) 64 read_val |= (2u << 25); 65 break; 66 case 0xb0: /* MSI-X Cap */ 67 /* TableSize=2 or 4, Next Cap is EA */ 68 read_val &= 0xc00000ff; 69 /* 70 * If Express Cap(0x70) raw PME vector reads as 0 we are on 71 * T88 and TableSize is reported as 4, else TableSize 72 * is 2. 73 */ 74 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD); 75 tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); 76 tmp_val >>= 32; 77 if (!(tmp_val & (0x1f << 25))) 78 read_val |= 0x0003bc00; 79 else 80 read_val |= 0x0001bc00; 81 break; 82 case 0xb4: 83 /* Table offset=0, BIR=0 */ 84 read_val = 0x00000000; 85 break; 86 case 0xb8: 87 /* BPA offset=0xf0000, BIR=0 */ 88 read_val = 0x000f0000; 89 break; 90 case 0xbc: 91 /* EA, 1 entry, no next Cap */ 92 read_val = 0x00010014; 93 break; 94 case 0xc0: 95 /* DW2 for type-1 */ 96 read_val = 0x00000000; 97 break; 98 case 0xc4: 99 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */ 100 read_val = 0x80ff0003; 101 break; 102 case 0xc8: 103 read_val = pem_pci->ea_entry[0]; 104 break; 105 case 0xcc: 106 read_val = pem_pci->ea_entry[1]; 107 break; 108 case 0xd0: 109 read_val = pem_pci->ea_entry[2]; 110 break; 111 default: 112 break; 113 } 114 read_val >>= (8 * (where & 3)); 115 switch (size) { 116 case 1: 117 read_val &= 0xff; 118 break; 119 case 2: 120 read_val &= 0xffff; 121 break; 122 default: 123 break; 124 } 125 *val = read_val; 126 return PCIBIOS_SUCCESSFUL; 127 } 128 129 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn, 130 int where, int size, u32 *val) 131 { 132 struct pci_config_window *cfg = bus->sysdata; 133 134 if (bus->number < cfg->busr.start || 135 bus->number > cfg->busr.end) 136 return PCIBIOS_DEVICE_NOT_FOUND; 137 138 /* 139 * The first device on the bus is the PEM PCIe bridge. 140 * Special case its config access. 141 */ 142 if (bus->number == cfg->busr.start) 143 return thunder_pem_bridge_read(bus, devfn, where, size, val); 144 145 return pci_generic_config_read(bus, devfn, where, size, val); 146 } 147 148 /* 149 * Some of the w1c_bits below also include read-only or non-writable 150 * reserved bits, this makes the code simpler and is OK as the bits 151 * are not affected by writing zeros to them. 152 */ 153 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned) 154 { 155 u32 w1c_bits = 0; 156 157 switch (where_aligned) { 158 case 0x04: /* Command/Status */ 159 case 0x1c: /* Base and I/O Limit/Secondary Status */ 160 w1c_bits = 0xff000000; 161 break; 162 case 0x44: /* Power Management Control and Status */ 163 w1c_bits = 0xfffffe00; 164 break; 165 case 0x78: /* Device Control/Device Status */ 166 case 0x80: /* Link Control/Link Status */ 167 case 0x88: /* Slot Control/Slot Status */ 168 case 0x90: /* Root Status */ 169 case 0xa0: /* Link Control 2 Registers/Link Status 2 */ 170 w1c_bits = 0xffff0000; 171 break; 172 case 0x104: /* Uncorrectable Error Status */ 173 case 0x110: /* Correctable Error Status */ 174 case 0x130: /* Error Status */ 175 case 0x160: /* Link Control 4 */ 176 w1c_bits = 0xffffffff; 177 break; 178 default: 179 break; 180 } 181 return w1c_bits; 182 } 183 184 /* Some bits must be written to one so they appear to be read-only. */ 185 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned) 186 { 187 u32 w1_bits; 188 189 switch (where_aligned) { 190 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */ 191 /* Force 32-bit I/O addressing. */ 192 w1_bits = 0x0101; 193 break; 194 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */ 195 /* Force 64-bit addressing */ 196 w1_bits = 0x00010001; 197 break; 198 default: 199 w1_bits = 0; 200 break; 201 } 202 return w1_bits; 203 } 204 205 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, 206 int where, int size, u32 val) 207 { 208 struct pci_config_window *cfg = bus->sysdata; 209 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; 210 u64 write_val, read_val; 211 u64 where_aligned = where & ~3ull; 212 u32 mask = 0; 213 214 215 if (devfn != 0 || where >= 2048) 216 return PCIBIOS_DEVICE_NOT_FOUND; 217 218 /* 219 * 32-bit accesses only. If the write is for a size smaller 220 * than 32-bits, we must first read the 32-bit value and merge 221 * in the desired bits and then write the whole 32-bits back 222 * out. 223 */ 224 switch (size) { 225 case 1: 226 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); 227 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); 228 read_val >>= 32; 229 mask = ~(0xff << (8 * (where & 3))); 230 read_val &= mask; 231 val = (val & 0xff) << (8 * (where & 3)); 232 val |= (u32)read_val; 233 break; 234 case 2: 235 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); 236 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); 237 read_val >>= 32; 238 mask = ~(0xffff << (8 * (where & 3))); 239 read_val &= mask; 240 val = (val & 0xffff) << (8 * (where & 3)); 241 val |= (u32)read_val; 242 break; 243 default: 244 break; 245 } 246 247 /* 248 * By expanding the write width to 32 bits, we may 249 * inadvertently hit some W1C bits that were not intended to 250 * be written. Calculate the mask that must be applied to the 251 * data to be written to avoid these cases. 252 */ 253 if (mask) { 254 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where); 255 256 if (w1c_bits) { 257 mask &= w1c_bits; 258 val &= ~mask; 259 } 260 } 261 262 /* 263 * Some bits must be read-only with value of one. Since the 264 * access method allows these to be cleared if a zero is 265 * written, force them to one before writing. 266 */ 267 val |= thunder_pem_bridge_w1_bits(where_aligned); 268 269 /* 270 * Low order bits are the config address, the high order 32 271 * bits are the data to be written. 272 */ 273 write_val = (((u64)val) << 32) | where_aligned; 274 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR); 275 return PCIBIOS_SUCCESSFUL; 276 } 277 278 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn, 279 int where, int size, u32 val) 280 { 281 struct pci_config_window *cfg = bus->sysdata; 282 283 if (bus->number < cfg->busr.start || 284 bus->number > cfg->busr.end) 285 return PCIBIOS_DEVICE_NOT_FOUND; 286 /* 287 * The first device on the bus is the PEM PCIe bridge. 288 * Special case its config access. 289 */ 290 if (bus->number == cfg->busr.start) 291 return thunder_pem_bridge_write(bus, devfn, where, size, val); 292 293 294 return pci_generic_config_write(bus, devfn, where, size, val); 295 } 296 297 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg, 298 struct resource *res_pem) 299 { 300 struct thunder_pem_pci *pem_pci; 301 resource_size_t bar4_start; 302 303 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL); 304 if (!pem_pci) 305 return -ENOMEM; 306 307 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000); 308 if (!pem_pci->pem_reg_base) 309 return -ENOMEM; 310 311 /* 312 * The MSI-X BAR for the PEM and AER interrupts is located at 313 * a fixed offset from the PEM register base. Generate a 314 * fragment of the synthesized Enhanced Allocation capability 315 * structure here for the BAR. 316 */ 317 bar4_start = res_pem->start + 0xf00000; 318 pem_pci->ea_entry[0] = (u32)bar4_start | 2; 319 pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u; 320 pem_pci->ea_entry[2] = (u32)(bar4_start >> 32); 321 322 cfg->priv = pem_pci; 323 return 0; 324 } 325 326 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) 327 328 #define PEM_RES_BASE 0x87e0c0000000UL 329 #define PEM_NODE_MASK GENMASK(45, 44) 330 #define PEM_INDX_MASK GENMASK(26, 24) 331 #define PEM_MIN_DOM_IN_NODE 4 332 #define PEM_MAX_DOM_IN_NODE 10 333 334 static void thunder_pem_reserve_range(struct device *dev, int seg, 335 struct resource *r) 336 { 337 resource_size_t start = r->start, end = r->end; 338 struct resource *res; 339 const char *regionid; 340 341 regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg); 342 if (!regionid) 343 return; 344 345 res = request_mem_region(start, end - start + 1, regionid); 346 if (res) 347 res->flags &= ~IORESOURCE_BUSY; 348 else 349 kfree(regionid); 350 351 dev_info(dev, "%pR %s reserved\n", r, 352 res ? "has been" : "could not be"); 353 } 354 355 static void thunder_pem_legacy_fw(struct acpi_pci_root *root, 356 struct resource *res_pem) 357 { 358 int node = acpi_get_node(root->device->handle); 359 int index; 360 361 if (node == NUMA_NO_NODE) 362 node = 0; 363 364 index = root->segment - PEM_MIN_DOM_IN_NODE; 365 index -= node * PEM_MAX_DOM_IN_NODE; 366 res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) | 367 FIELD_PREP(PEM_INDX_MASK, index); 368 res_pem->flags = IORESOURCE_MEM; 369 } 370 371 static int thunder_pem_acpi_init(struct pci_config_window *cfg) 372 { 373 struct device *dev = cfg->parent; 374 struct acpi_device *adev = to_acpi_device(dev); 375 struct acpi_pci_root *root = acpi_driver_data(adev); 376 struct resource *res_pem; 377 int ret; 378 379 res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL); 380 if (!res_pem) 381 return -ENOMEM; 382 383 ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem); 384 385 /* 386 * If we fail to gather resources it means that we run with old 387 * FW where we need to calculate PEM-specific resources manually. 388 */ 389 if (ret) { 390 thunder_pem_legacy_fw(root, res_pem); 391 /* 392 * Reserve 64K size PEM specific resources. The full 16M range 393 * size is required for thunder_pem_init() call. 394 */ 395 res_pem->end = res_pem->start + SZ_64K - 1; 396 thunder_pem_reserve_range(dev, root->segment, res_pem); 397 res_pem->end = res_pem->start + SZ_16M - 1; 398 399 /* Reserve PCI configuration space as well. */ 400 thunder_pem_reserve_range(dev, root->segment, &cfg->res); 401 } 402 403 return thunder_pem_init(dev, cfg, res_pem); 404 } 405 406 struct pci_ecam_ops thunder_pem_ecam_ops = { 407 .bus_shift = 24, 408 .init = thunder_pem_acpi_init, 409 .pci_ops = { 410 .map_bus = pci_ecam_map_bus, 411 .read = thunder_pem_config_read, 412 .write = thunder_pem_config_write, 413 } 414 }; 415 416 #endif 417 418 #ifdef CONFIG_PCI_HOST_THUNDER_PEM 419 420 static int thunder_pem_platform_init(struct pci_config_window *cfg) 421 { 422 struct device *dev = cfg->parent; 423 struct platform_device *pdev = to_platform_device(dev); 424 struct resource *res_pem; 425 426 if (!dev->of_node) 427 return -EINVAL; 428 429 /* 430 * The second register range is the PEM bridge to the PCIe 431 * bus. It has a different config access method than those 432 * devices behind the bridge. 433 */ 434 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 435 if (!res_pem) { 436 dev_err(dev, "missing \"reg[1]\"property\n"); 437 return -EINVAL; 438 } 439 440 return thunder_pem_init(dev, cfg, res_pem); 441 } 442 443 static struct pci_ecam_ops pci_thunder_pem_ops = { 444 .bus_shift = 24, 445 .init = thunder_pem_platform_init, 446 .pci_ops = { 447 .map_bus = pci_ecam_map_bus, 448 .read = thunder_pem_config_read, 449 .write = thunder_pem_config_write, 450 } 451 }; 452 453 static const struct of_device_id thunder_pem_of_match[] = { 454 { .compatible = "cavium,pci-host-thunder-pem" }, 455 { }, 456 }; 457 458 static int thunder_pem_probe(struct platform_device *pdev) 459 { 460 return pci_host_common_probe(pdev, &pci_thunder_pem_ops); 461 } 462 463 static struct platform_driver thunder_pem_driver = { 464 .driver = { 465 .name = KBUILD_MODNAME, 466 .of_match_table = thunder_pem_of_match, 467 .suppress_bind_attrs = true, 468 }, 469 .probe = thunder_pem_probe, 470 }; 471 builtin_platform_driver(thunder_pem_driver); 472 473 #endif 474 #endif 475