1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common library for PCI host controller drivers 4 * 5 * Copyright (C) 2014 ARM Limited 6 * 7 * Author: Will Deacon <will.deacon@arm.com> 8 */ 9 10 #ifndef _PCI_HOST_COMMON_H 11 #define _PCI_HOST_COMMON_H 12 13 #include <linux/delay.h> 14 #include "../pci.h" 15 16 struct pci_ecam_ops; 17 18 /** 19 * struct pci_host_perst - PERST# GPIO descriptor 20 * @list: List node for linking multiple PERST# GPIOs 21 * @desc: GPIO descriptor for PERST# signal 22 * 23 * This structure holds a single PERST# GPIO descriptor. 24 */ 25 struct pci_host_perst { 26 struct list_head list; 27 struct gpio_desc *desc; 28 }; 29 30 /** 31 * struct pci_host_port - Generic Root Port properties 32 * @list: List node for linking multiple ports 33 * @perst: List of PERST# GPIO descriptors for this port and its children 34 * 35 * This structure contains common properties that can be parsed from 36 * Root Port device tree nodes. 37 */ 38 struct pci_host_port { 39 struct list_head list; 40 struct list_head perst; 41 }; 42 43 void pci_host_common_delete_ports(void *data); 44 int pci_host_common_parse_ports(struct device *dev, 45 struct pci_host_bridge *bridge); 46 int pci_host_common_probe(struct platform_device *pdev); 47 int pci_host_common_init(struct platform_device *pdev, 48 struct pci_host_bridge *bridge, 49 const struct pci_ecam_ops *ops); 50 void pci_host_common_remove(struct platform_device *pdev); 51 52 struct pci_config_window *pci_host_common_ecam_create(struct device *dev, 53 struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); 54 55 bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge, 56 bool *pme_capable); 57 58 /** 59 * pci_host_common_link_train_delay - Wait 100 ms if link speed > 5 GT/s 60 * @max_link_speed: the maximum link speed (2 = 5.0 GT/s, 3 = 8.0 GT/s, ...) 61 * 62 * Must be called after Link training completes and before the first 63 * Configuration Request is sent. 64 */ 65 static inline void pci_host_common_link_train_delay(int max_link_speed) 66 { 67 if (max_link_speed > 2) 68 msleep(PCIE_RESET_CONFIG_WAIT_MS); 69 } 70 71 #endif 72