1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Faraday Technology FTPC100 PCI Controller 4 * 5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini: 8 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com> 9 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 10 * Based on SL2312 PCI controller code 11 * Storlink (C) 2003 12 */ 13 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_pci.h> 22 #include <linux/pci.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/irqdomain.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/bitops.h> 28 #include <linux/irq.h> 29 #include <linux/clk.h> 30 31 #include "../pci.h" 32 33 /* 34 * Special configuration registers directly in the first few words 35 * in I/O space. 36 */ 37 #define FTPCI_IOSIZE 0x00 38 #define FTPCI_PROT 0x04 /* AHB protection */ 39 #define FTPCI_CTRL 0x08 /* PCI control signal */ 40 #define FTPCI_SOFTRST 0x10 /* Soft reset counter and response error enable */ 41 #define FTPCI_CONFIG 0x28 /* PCI configuration command register */ 42 #define FTPCI_DATA 0x2C 43 44 #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */ 45 #define FARADAY_PCI_PMC 0x40 /* Power management control */ 46 #define FARADAY_PCI_PMCSR 0x44 /* Power management status */ 47 #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */ 48 #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */ 49 #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */ 50 #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */ 51 #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */ 52 53 #define PCI_STATUS_66MHZ_CAPABLE BIT(21) 54 55 /* Bits 31..28 gives INTD..INTA status */ 56 #define PCI_CTRL2_INTSTS_SHIFT 28 57 #define PCI_CTRL2_INTMASK_CMDERR BIT(27) 58 #define PCI_CTRL2_INTMASK_PARERR BIT(26) 59 /* Bits 25..22 masks INTD..INTA */ 60 #define PCI_CTRL2_INTMASK_SHIFT 22 61 #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21) 62 #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20) 63 #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19) 64 #define PCI_CTRL2_INTMASK_RETRY4 BIT(18) 65 #define PCI_CTRL2_INTMASK_SERR_RX BIT(17) 66 #define PCI_CTRL2_INTMASK_PERR_RX BIT(16) 67 /* Bit 15 reserved */ 68 #define PCI_CTRL2_MSTPRI_REQ6 BIT(14) 69 #define PCI_CTRL2_MSTPRI_REQ5 BIT(13) 70 #define PCI_CTRL2_MSTPRI_REQ4 BIT(12) 71 #define PCI_CTRL2_MSTPRI_REQ3 BIT(11) 72 #define PCI_CTRL2_MSTPRI_REQ2 BIT(10) 73 #define PCI_CTRL2_MSTPRI_REQ1 BIT(9) 74 #define PCI_CTRL2_MSTPRI_REQ0 BIT(8) 75 /* Bits 7..4 reserved */ 76 /* Bits 3..0 TRDYW */ 77 78 /* 79 * Memory configs: 80 * Bit 31..20 defines the PCI side memory base 81 * Bit 19..16 (4 bits) defines the size per below 82 */ 83 #define FARADAY_PCI_MEMBASE_MASK 0xfff00000 84 #define FARADAY_PCI_MEMSIZE_1MB 0x0 85 #define FARADAY_PCI_MEMSIZE_2MB 0x1 86 #define FARADAY_PCI_MEMSIZE_4MB 0x2 87 #define FARADAY_PCI_MEMSIZE_8MB 0x3 88 #define FARADAY_PCI_MEMSIZE_16MB 0x4 89 #define FARADAY_PCI_MEMSIZE_32MB 0x5 90 #define FARADAY_PCI_MEMSIZE_64MB 0x6 91 #define FARADAY_PCI_MEMSIZE_128MB 0x7 92 #define FARADAY_PCI_MEMSIZE_256MB 0x8 93 #define FARADAY_PCI_MEMSIZE_512MB 0x9 94 #define FARADAY_PCI_MEMSIZE_1GB 0xa 95 #define FARADAY_PCI_MEMSIZE_2GB 0xb 96 #define FARADAY_PCI_MEMSIZE_SHIFT 16 97 98 /* 99 * The DMA base is set to 0x0 for all memory segments, it reflects the 100 * fact that the memory of the host system starts at 0x0. 101 */ 102 #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000 103 #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000 104 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000 105 106 /** 107 * struct faraday_pci_variant - encodes IP block differences 108 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller 109 * embedded in the host bridge. 110 */ 111 struct faraday_pci_variant { 112 bool cascaded_irq; 113 }; 114 115 struct faraday_pci { 116 struct device *dev; 117 void __iomem *base; 118 struct irq_domain *irqdomain; 119 struct pci_bus *bus; 120 struct clk *bus_clk; 121 }; 122 123 static int faraday_res_to_memcfg(resource_size_t mem_base, 124 resource_size_t mem_size, u32 *val) 125 { 126 u32 outval; 127 128 switch (mem_size) { 129 case SZ_1M: 130 outval = FARADAY_PCI_MEMSIZE_1MB; 131 break; 132 case SZ_2M: 133 outval = FARADAY_PCI_MEMSIZE_2MB; 134 break; 135 case SZ_4M: 136 outval = FARADAY_PCI_MEMSIZE_4MB; 137 break; 138 case SZ_8M: 139 outval = FARADAY_PCI_MEMSIZE_8MB; 140 break; 141 case SZ_16M: 142 outval = FARADAY_PCI_MEMSIZE_16MB; 143 break; 144 case SZ_32M: 145 outval = FARADAY_PCI_MEMSIZE_32MB; 146 break; 147 case SZ_64M: 148 outval = FARADAY_PCI_MEMSIZE_64MB; 149 break; 150 case SZ_128M: 151 outval = FARADAY_PCI_MEMSIZE_128MB; 152 break; 153 case SZ_256M: 154 outval = FARADAY_PCI_MEMSIZE_256MB; 155 break; 156 case SZ_512M: 157 outval = FARADAY_PCI_MEMSIZE_512MB; 158 break; 159 case SZ_1G: 160 outval = FARADAY_PCI_MEMSIZE_1GB; 161 break; 162 case SZ_2G: 163 outval = FARADAY_PCI_MEMSIZE_2GB; 164 break; 165 default: 166 return -EINVAL; 167 } 168 outval <<= FARADAY_PCI_MEMSIZE_SHIFT; 169 170 /* This is probably not good */ 171 if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK)) 172 pr_warn("truncated PCI memory base\n"); 173 /* Translate to bridge side address space */ 174 outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK); 175 pr_debug("Translated pci base @%pap, size %pap to config %08x\n", 176 &mem_base, &mem_size, outval); 177 178 *val = outval; 179 return 0; 180 } 181 182 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, 183 unsigned int fn, int config, int size, 184 u32 *value) 185 { 186 writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), 187 PCI_FUNC(fn), config), 188 p->base + FTPCI_CONFIG); 189 190 *value = readl(p->base + FTPCI_DATA); 191 192 if (size == 1) 193 *value = (*value >> (8 * (config & 3))) & 0xFF; 194 else if (size == 2) 195 *value = (*value >> (8 * (config & 3))) & 0xFFFF; 196 197 return PCIBIOS_SUCCESSFUL; 198 } 199 200 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn, 201 int config, int size, u32 *value) 202 { 203 struct faraday_pci *p = bus->sysdata; 204 205 dev_dbg(&bus->dev, 206 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 207 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); 208 209 return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value); 210 } 211 212 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, 213 unsigned int fn, int config, int size, 214 u32 value) 215 { 216 int ret = PCIBIOS_SUCCESSFUL; 217 218 writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), 219 PCI_FUNC(fn), config), 220 p->base + FTPCI_CONFIG); 221 222 switch (size) { 223 case 4: 224 writel(value, p->base + FTPCI_DATA); 225 break; 226 case 2: 227 writew(value, p->base + FTPCI_DATA + (config & 3)); 228 break; 229 case 1: 230 writeb(value, p->base + FTPCI_DATA + (config & 3)); 231 break; 232 default: 233 ret = PCIBIOS_BAD_REGISTER_NUMBER; 234 } 235 236 return ret; 237 } 238 239 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn, 240 int config, int size, u32 value) 241 { 242 struct faraday_pci *p = bus->sysdata; 243 244 dev_dbg(&bus->dev, 245 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", 246 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); 247 248 return faraday_raw_pci_write_config(p, bus->number, fn, config, size, 249 value); 250 } 251 252 static struct pci_ops faraday_pci_ops = { 253 .read = faraday_pci_read_config, 254 .write = faraday_pci_write_config, 255 }; 256 257 static void faraday_pci_ack_irq(struct irq_data *d) 258 { 259 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 260 unsigned int reg; 261 262 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 263 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); 264 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT); 265 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 266 } 267 268 static void faraday_pci_mask_irq(struct irq_data *d) 269 { 270 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 271 unsigned int reg; 272 273 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 274 reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT) 275 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT)); 276 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 277 } 278 279 static void faraday_pci_unmask_irq(struct irq_data *d) 280 { 281 struct faraday_pci *p = irq_data_get_irq_chip_data(d); 282 unsigned int reg; 283 284 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 285 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); 286 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT); 287 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); 288 } 289 290 static void faraday_pci_irq_handler(struct irq_desc *desc) 291 { 292 struct faraday_pci *p = irq_desc_get_handler_data(desc); 293 struct irq_chip *irqchip = irq_desc_get_chip(desc); 294 unsigned int irq_stat, reg, i; 295 296 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); 297 irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT; 298 299 chained_irq_enter(irqchip, desc); 300 301 for (i = 0; i < 4; i++) { 302 if ((irq_stat & BIT(i)) == 0) 303 continue; 304 generic_handle_domain_irq(p->irqdomain, i); 305 } 306 307 chained_irq_exit(irqchip, desc); 308 } 309 310 static struct irq_chip faraday_pci_irq_chip = { 311 .name = "PCI", 312 .irq_ack = faraday_pci_ack_irq, 313 .irq_mask = faraday_pci_mask_irq, 314 .irq_unmask = faraday_pci_unmask_irq, 315 }; 316 317 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq, 318 irq_hw_number_t hwirq) 319 { 320 irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq); 321 irq_set_chip_data(irq, domain->host_data); 322 323 return 0; 324 } 325 326 static const struct irq_domain_ops faraday_pci_irqdomain_ops = { 327 .map = faraday_pci_irq_map, 328 }; 329 330 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p) 331 { 332 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL); 333 int irq; 334 int i; 335 336 if (!intc) { 337 dev_err(p->dev, "missing child interrupt-controller node\n"); 338 return -EINVAL; 339 } 340 341 /* All PCI IRQs cascade off this one */ 342 irq = of_irq_get(intc, 0); 343 if (irq <= 0) { 344 dev_err(p->dev, "failed to get parent IRQ\n"); 345 of_node_put(intc); 346 return irq ?: -EINVAL; 347 } 348 349 p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX, 350 &faraday_pci_irqdomain_ops, p); 351 of_node_put(intc); 352 if (!p->irqdomain) { 353 dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n"); 354 return -EINVAL; 355 } 356 357 irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p); 358 359 for (i = 0; i < 4; i++) 360 irq_create_mapping(p->irqdomain, i); 361 362 return 0; 363 } 364 365 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p) 366 { 367 struct device *dev = p->dev; 368 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 369 struct resource_entry *entry; 370 u32 confreg[3] = { 371 FARADAY_PCI_MEM1_BASE_SIZE, 372 FARADAY_PCI_MEM2_BASE_SIZE, 373 FARADAY_PCI_MEM3_BASE_SIZE, 374 }; 375 int i = 0; 376 u32 val; 377 378 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 379 u64 pci_addr = entry->res->start - entry->offset; 380 u64 end = entry->res->end - entry->offset; 381 int ret; 382 383 ret = faraday_res_to_memcfg(pci_addr, 384 resource_size(entry->res), &val); 385 if (ret) { 386 dev_err(dev, 387 "DMA range %d: illegal MEM resource size\n", i); 388 return -EINVAL; 389 } 390 391 dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n", 392 i + 1, pci_addr, end, val); 393 if (i <= 2) { 394 faraday_raw_pci_write_config(p, 0, 0, confreg[i], 395 4, val); 396 } else { 397 dev_err(dev, "ignore extraneous dma-range %d\n", i); 398 break; 399 } 400 401 i++; 402 } 403 404 return 0; 405 } 406 407 static int faraday_pci_probe(struct platform_device *pdev) 408 { 409 struct device *dev = &pdev->dev; 410 const struct faraday_pci_variant *variant = 411 of_device_get_match_data(dev); 412 struct resource_entry *win; 413 struct faraday_pci *p; 414 struct resource *io; 415 struct pci_host_bridge *host; 416 struct clk *clk; 417 unsigned char max_bus_speed = PCI_SPEED_33MHz; 418 unsigned char cur_bus_speed = PCI_SPEED_33MHz; 419 int ret; 420 u32 val; 421 422 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 423 if (!host) 424 return -ENOMEM; 425 426 host->ops = &faraday_pci_ops; 427 p = pci_host_bridge_priv(host); 428 host->sysdata = p; 429 p->dev = dev; 430 431 /* Retrieve and enable optional clocks */ 432 clk = devm_clk_get(dev, "PCLK"); 433 if (IS_ERR(clk)) 434 return PTR_ERR(clk); 435 ret = clk_prepare_enable(clk); 436 if (ret) { 437 dev_err(dev, "could not prepare PCLK\n"); 438 return ret; 439 } 440 p->bus_clk = devm_clk_get(dev, "PCICLK"); 441 if (IS_ERR(p->bus_clk)) 442 return PTR_ERR(p->bus_clk); 443 ret = clk_prepare_enable(p->bus_clk); 444 if (ret) { 445 dev_err(dev, "could not prepare PCICLK\n"); 446 return ret; 447 } 448 449 p->base = devm_platform_ioremap_resource(pdev, 0); 450 if (IS_ERR(p->base)) 451 return PTR_ERR(p->base); 452 453 win = resource_list_first_type(&host->windows, IORESOURCE_IO); 454 if (win) { 455 io = win->res; 456 if (!faraday_res_to_memcfg(io->start - win->offset, 457 resource_size(io), &val)) { 458 /* setup I/O space size */ 459 writel(val, p->base + FTPCI_IOSIZE); 460 } else { 461 dev_err(dev, "illegal IO mem size\n"); 462 return -EINVAL; 463 } 464 } 465 466 /* Setup hostbridge */ 467 val = readl(p->base + FTPCI_CTRL); 468 val |= PCI_COMMAND_IO; 469 val |= PCI_COMMAND_MEMORY; 470 val |= PCI_COMMAND_MASTER; 471 writel(val, p->base + FTPCI_CTRL); 472 /* Mask and clear all interrupts */ 473 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000); 474 if (variant->cascaded_irq) { 475 ret = faraday_pci_setup_cascaded_irq(p); 476 if (ret) { 477 dev_err(dev, "failed to setup cascaded IRQ\n"); 478 return ret; 479 } 480 } 481 482 /* Check bus clock if we can gear up to 66 MHz */ 483 if (!IS_ERR(p->bus_clk)) { 484 unsigned long rate; 485 u32 val; 486 487 faraday_raw_pci_read_config(p, 0, 0, 488 FARADAY_PCI_STATUS_CMD, 4, &val); 489 rate = clk_get_rate(p->bus_clk); 490 491 if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) { 492 dev_info(dev, "33MHz bus is 66MHz capable\n"); 493 max_bus_speed = PCI_SPEED_66MHz; 494 ret = clk_set_rate(p->bus_clk, 66000000); 495 if (ret) 496 dev_err(dev, "failed to set bus clock\n"); 497 } else { 498 dev_info(dev, "33MHz only bus\n"); 499 max_bus_speed = PCI_SPEED_33MHz; 500 } 501 502 /* Bumping the clock may fail so read back the rate */ 503 rate = clk_get_rate(p->bus_clk); 504 if (rate == 33000000) 505 cur_bus_speed = PCI_SPEED_33MHz; 506 if (rate == 66000000) 507 cur_bus_speed = PCI_SPEED_66MHz; 508 } 509 510 ret = faraday_pci_parse_map_dma_ranges(p); 511 if (ret) 512 return ret; 513 514 ret = pci_scan_root_bus_bridge(host); 515 if (ret) { 516 dev_err(dev, "failed to scan host: %d\n", ret); 517 return ret; 518 } 519 p->bus = host->bus; 520 p->bus->max_bus_speed = max_bus_speed; 521 p->bus->cur_bus_speed = cur_bus_speed; 522 523 pci_bus_assign_resources(p->bus); 524 pci_bus_add_devices(p->bus); 525 526 return 0; 527 } 528 529 /* 530 * We encode bridge variants here, we have at least two so it doesn't 531 * hurt to have infrastructure to encompass future variants as well. 532 */ 533 static const struct faraday_pci_variant faraday_regular = { 534 .cascaded_irq = true, 535 }; 536 537 static const struct faraday_pci_variant faraday_dual = { 538 .cascaded_irq = false, 539 }; 540 541 static const struct of_device_id faraday_pci_of_match[] = { 542 { 543 .compatible = "faraday,ftpci100", 544 .data = &faraday_regular, 545 }, 546 { 547 .compatible = "faraday,ftpci100-dual", 548 .data = &faraday_dual, 549 }, 550 {}, 551 }; 552 553 static struct platform_driver faraday_pci_driver = { 554 .driver = { 555 .name = "ftpci100", 556 .of_match_table = faraday_pci_of_match, 557 .suppress_bind_attrs = true, 558 }, 559 .probe = faraday_pci_probe, 560 }; 561 builtin_platform_driver(faraday_pci_driver); 562