1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics STM32MP25 PCIe root complex driver. 4 * 5 * Copyright (C) 2025 STMicroelectronics 6 * Author: Christian Bruel <christian.bruel@foss.st.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/irq.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/phy/phy.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pm_wakeirq.h> 25 #include <linux/regmap.h> 26 #include <linux/reset.h> 27 #include <linux/stddef.h> 28 29 #include "../../pci.h" 30 31 #include "pcie-designware.h" 32 #include "pcie-stm32.h" 33 34 struct stm32_pcie { 35 struct dw_pcie pci; 36 struct regmap *regmap; 37 struct reset_control *rst; 38 struct phy *phy; 39 struct clk *clk; 40 struct gpio_desc *perst_gpio; 41 struct gpio_desc *wake_gpio; 42 }; 43 44 static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie) 45 { 46 if (stm32_pcie->perst_gpio) { 47 msleep(PCIE_T_PVPERL_MS); 48 gpiod_set_value(stm32_pcie->perst_gpio, 0); 49 } 50 51 msleep(PCIE_RESET_CONFIG_WAIT_MS); 52 } 53 54 static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie) 55 { 56 gpiod_set_value(stm32_pcie->perst_gpio, 1); 57 } 58 59 static int stm32_pcie_start_link(struct dw_pcie *pci) 60 { 61 struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); 62 63 return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, 64 STM32MP25_PCIECR_LTSSM_EN, 65 STM32MP25_PCIECR_LTSSM_EN); 66 } 67 68 static void stm32_pcie_stop_link(struct dw_pcie *pci) 69 { 70 struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); 71 72 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, 73 STM32MP25_PCIECR_LTSSM_EN, 0); 74 } 75 76 static int stm32_pcie_suspend_noirq(struct device *dev) 77 { 78 struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); 79 int ret; 80 81 ret = dw_pcie_suspend_noirq(&stm32_pcie->pci); 82 if (ret) 83 return ret; 84 85 stm32_pcie_assert_perst(stm32_pcie); 86 87 clk_disable_unprepare(stm32_pcie->clk); 88 89 if (!device_wakeup_path(dev)) 90 phy_exit(stm32_pcie->phy); 91 92 return pinctrl_pm_select_sleep_state(dev); 93 } 94 95 static int stm32_pcie_resume_noirq(struct device *dev) 96 { 97 struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); 98 int ret; 99 100 /* 101 * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK, 102 * thus if no device is present, must deassert it with a GPIO from 103 * pinctrl pinmux before accessing the DBI registers. 104 */ 105 ret = pinctrl_pm_select_init_state(dev); 106 if (ret) { 107 dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret); 108 return ret; 109 } 110 111 if (!device_wakeup_path(dev)) { 112 ret = phy_init(stm32_pcie->phy); 113 if (ret) { 114 pinctrl_pm_select_default_state(dev); 115 return ret; 116 } 117 } 118 119 ret = clk_prepare_enable(stm32_pcie->clk); 120 if (ret) 121 goto err_phy_exit; 122 123 stm32_pcie_deassert_perst(stm32_pcie); 124 125 ret = dw_pcie_resume_noirq(&stm32_pcie->pci); 126 if (ret) 127 goto err_disable_clk; 128 129 pinctrl_pm_select_default_state(dev); 130 131 return 0; 132 133 err_disable_clk: 134 stm32_pcie_assert_perst(stm32_pcie); 135 clk_disable_unprepare(stm32_pcie->clk); 136 137 err_phy_exit: 138 phy_exit(stm32_pcie->phy); 139 pinctrl_pm_select_default_state(dev); 140 141 return ret; 142 } 143 144 static const struct dev_pm_ops stm32_pcie_pm_ops = { 145 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq, 146 stm32_pcie_resume_noirq) 147 }; 148 149 static const struct dw_pcie_host_ops stm32_pcie_host_ops = { 150 }; 151 152 static const struct dw_pcie_ops dw_pcie_ops = { 153 .start_link = stm32_pcie_start_link, 154 .stop_link = stm32_pcie_stop_link 155 }; 156 157 static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie) 158 { 159 struct device *dev = stm32_pcie->pci.dev; 160 unsigned int wake_irq; 161 int ret; 162 163 ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); 164 if (ret) 165 return ret; 166 167 ret = phy_init(stm32_pcie->phy); 168 if (ret) 169 return ret; 170 171 ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, 172 STM32MP25_PCIECR_TYPE_MASK, 173 STM32MP25_PCIECR_RC); 174 if (ret) 175 goto err_phy_exit; 176 177 stm32_pcie_deassert_perst(stm32_pcie); 178 179 if (stm32_pcie->wake_gpio) { 180 wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio); 181 ret = dev_pm_set_dedicated_wake_irq(dev, wake_irq); 182 if (ret) { 183 dev_err(dev, "Failed to enable wakeup irq %d\n", ret); 184 goto err_assert_perst; 185 } 186 irq_set_irq_type(wake_irq, IRQ_TYPE_EDGE_FALLING); 187 } 188 189 return 0; 190 191 err_assert_perst: 192 stm32_pcie_assert_perst(stm32_pcie); 193 194 err_phy_exit: 195 phy_exit(stm32_pcie->phy); 196 197 return ret; 198 } 199 200 static void stm32_remove_pcie_port(struct stm32_pcie *stm32_pcie) 201 { 202 dev_pm_clear_wake_irq(stm32_pcie->pci.dev); 203 204 stm32_pcie_assert_perst(stm32_pcie); 205 206 phy_exit(stm32_pcie->phy); 207 } 208 209 static int stm32_pcie_parse_port(struct stm32_pcie *stm32_pcie) 210 { 211 struct device *dev = stm32_pcie->pci.dev; 212 struct device_node *root_port; 213 214 root_port = of_get_next_available_child(dev->of_node, NULL); 215 216 stm32_pcie->phy = devm_of_phy_get(dev, root_port, NULL); 217 if (IS_ERR(stm32_pcie->phy)) { 218 of_node_put(root_port); 219 return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), 220 "Failed to get pcie-phy\n"); 221 } 222 223 stm32_pcie->perst_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port), 224 "reset", GPIOD_OUT_HIGH, NULL); 225 if (IS_ERR(stm32_pcie->perst_gpio)) { 226 if (PTR_ERR(stm32_pcie->perst_gpio) != -ENOENT) { 227 of_node_put(root_port); 228 return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), 229 "Failed to get reset GPIO\n"); 230 } 231 stm32_pcie->perst_gpio = NULL; 232 } 233 234 stm32_pcie->wake_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port), 235 "wake", GPIOD_IN, NULL); 236 237 if (IS_ERR(stm32_pcie->wake_gpio)) { 238 if (PTR_ERR(stm32_pcie->wake_gpio) != -ENOENT) { 239 of_node_put(root_port); 240 return dev_err_probe(dev, PTR_ERR(stm32_pcie->wake_gpio), 241 "Failed to get wake GPIO\n"); 242 } 243 stm32_pcie->wake_gpio = NULL; 244 } 245 246 of_node_put(root_port); 247 248 return 0; 249 } 250 251 static int stm32_pcie_probe(struct platform_device *pdev) 252 { 253 struct stm32_pcie *stm32_pcie; 254 struct device *dev = &pdev->dev; 255 int ret; 256 257 stm32_pcie = devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); 258 if (!stm32_pcie) 259 return -ENOMEM; 260 261 stm32_pcie->pci.dev = dev; 262 stm32_pcie->pci.ops = &dw_pcie_ops; 263 stm32_pcie->pci.pp.ops = &stm32_pcie_host_ops; 264 265 stm32_pcie->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg"); 266 if (IS_ERR(stm32_pcie->regmap)) 267 return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), 268 "No syscfg specified\n"); 269 270 stm32_pcie->clk = devm_clk_get(dev, NULL); 271 if (IS_ERR(stm32_pcie->clk)) 272 return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), 273 "Failed to get PCIe clock source\n"); 274 275 stm32_pcie->rst = devm_reset_control_get_exclusive(dev, NULL); 276 if (IS_ERR(stm32_pcie->rst)) 277 return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), 278 "Failed to get PCIe reset\n"); 279 280 ret = stm32_pcie_parse_port(stm32_pcie); 281 if (ret) 282 return ret; 283 284 platform_set_drvdata(pdev, stm32_pcie); 285 286 ret = stm32_add_pcie_port(stm32_pcie); 287 if (ret) 288 return ret; 289 290 reset_control_assert(stm32_pcie->rst); 291 reset_control_deassert(stm32_pcie->rst); 292 293 ret = clk_prepare_enable(stm32_pcie->clk); 294 if (ret) { 295 dev_err(dev, "Core clock enable failed %d\n", ret); 296 goto err_remove_port; 297 } 298 299 ret = pm_runtime_set_active(dev); 300 if (ret < 0) { 301 dev_err_probe(dev, ret, "Failed to activate runtime PM\n"); 302 goto err_disable_clk; 303 } 304 305 pm_runtime_no_callbacks(dev); 306 307 ret = devm_pm_runtime_enable(dev); 308 if (ret < 0) { 309 dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 310 goto err_disable_clk; 311 } 312 313 ret = dw_pcie_host_init(&stm32_pcie->pci.pp); 314 if (ret) 315 goto err_disable_clk; 316 317 if (stm32_pcie->wake_gpio) 318 device_init_wakeup(dev, true); 319 320 return 0; 321 322 err_disable_clk: 323 clk_disable_unprepare(stm32_pcie->clk); 324 325 err_remove_port: 326 stm32_remove_pcie_port(stm32_pcie); 327 328 return ret; 329 } 330 331 static void stm32_pcie_remove(struct platform_device *pdev) 332 { 333 struct stm32_pcie *stm32_pcie = platform_get_drvdata(pdev); 334 struct dw_pcie_rp *pp = &stm32_pcie->pci.pp; 335 336 if (stm32_pcie->wake_gpio) 337 device_init_wakeup(&pdev->dev, false); 338 339 dw_pcie_host_deinit(pp); 340 341 clk_disable_unprepare(stm32_pcie->clk); 342 343 stm32_remove_pcie_port(stm32_pcie); 344 345 pm_runtime_put_noidle(&pdev->dev); 346 } 347 348 static const struct of_device_id stm32_pcie_of_match[] = { 349 { .compatible = "st,stm32mp25-pcie-rc" }, 350 {}, 351 }; 352 353 static struct platform_driver stm32_pcie_driver = { 354 .probe = stm32_pcie_probe, 355 .remove = stm32_pcie_remove, 356 .driver = { 357 .name = "stm32-pcie", 358 .of_match_table = stm32_pcie_of_match, 359 .pm = &stm32_pcie_pm_ops, 360 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 361 }, 362 }; 363 364 module_platform_driver(stm32_pcie_driver); 365 366 MODULE_AUTHOR("Christian Bruel <christian.bruel@foss.st.com>"); 367 MODULE_DESCRIPTION("STM32MP25 PCIe Controller driver"); 368 MODULE_LICENSE("GPL"); 369 MODULE_DEVICE_TABLE(of, stm32_pcie_of_match); 370