1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs 4 * Copyright (C) 2022-2023 Renesas Electronics Corporation 5 * 6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be 7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not 8 * work. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/irqchip/arm-gic-v3.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/pci.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/reset.h> 25 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 /* Renesas-specific */ 30 /* PCIe Mode Setting Register 0 */ 31 #define PCIEMSR0 0x0000 32 #define APP_SRIS_MODE BIT(6) 33 #define DEVICE_TYPE_EP 0 34 #define DEVICE_TYPE_RC BIT(4) 35 #define BIFUR_MOD_SET_ON BIT(0) 36 37 /* MSI Capability */ 38 #define MSICAP0 0x0050 39 #define MSICAP0_MSIE BIT(16) 40 41 /* PCIe Interrupt Status 0 */ 42 #define PCIEINTSTS0 0x0084 43 44 /* PCIe Interrupt Status 0 Enable */ 45 #define PCIEINTSTS0EN 0x0310 46 #define MSI_CTRL_INT BIT(26) 47 #define SMLH_LINK_UP BIT(7) 48 #define RDLH_LINK_UP BIT(6) 49 50 /* PCIe DMA Interrupt Status Enable */ 51 #define PCIEDMAINTSTSEN 0x0314 52 #define PCIEDMAINTSTSEN_INIT GENMASK(15, 0) 53 54 /* Port Logic Registers 89 */ 55 #define PRTLGC89 0x0b70 56 57 /* Port Logic Registers 90 */ 58 #define PRTLGC90 0x0b74 59 60 /* PCIe Reset Control Register 1 */ 61 #define PCIERSTCTRL1 0x0014 62 #define APP_HOLD_PHY_RST BIT(16) 63 #define APP_LTSSM_ENABLE BIT(0) 64 65 /* INTC address */ 66 #define AXIINTCADDR 0x0a00 67 68 /* INTC control & mask */ 69 #define AXIINTCCONT 0x0a04 70 #define INTC_EN BIT(31) 71 #define INTC_MASK GENMASK(11, 3) 72 73 /* PCIe Power Management Control */ 74 #define PCIEPWRMNGCTRL 0x0070 75 #define APP_CLK_REQ_N BIT(11) 76 #define APP_CLK_PM_EN BIT(10) 77 78 #define RCAR_NUM_SPEED_CHANGE_RETRIES 10 79 #define RCAR_MAX_LINK_SPEED 4 80 81 #define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000 82 #define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800 83 84 #define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin" 85 #define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc000 86 MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); 87 88 struct rcar_gen4_pcie; 89 struct rcar_gen4_pcie_drvdata { 90 void (*additional_common_init)(struct rcar_gen4_pcie *rcar); 91 int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); 92 enum dw_pcie_device_mode mode; 93 }; 94 95 struct rcar_gen4_pcie { 96 struct dw_pcie dw; 97 void __iomem *base; 98 void __iomem *phy_base; 99 struct platform_device *pdev; 100 const struct rcar_gen4_pcie_drvdata *drvdata; 101 }; 102 #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) 103 104 /* Common */ 105 static bool rcar_gen4_pcie_link_up(struct dw_pcie *dw) 106 { 107 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 108 u32 val, mask; 109 110 val = readl(rcar->base + PCIEINTSTS0); 111 mask = RDLH_LINK_UP | SMLH_LINK_UP; 112 113 return (val & mask) == mask; 114 } 115 116 /* 117 * Manually initiate the speed change. Return 0 if change succeeded; otherwise 118 * -ETIMEDOUT. 119 */ 120 static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw) 121 { 122 u32 val; 123 int i; 124 125 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); 126 val &= ~PORT_LOGIC_SPEED_CHANGE; 127 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 128 129 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); 130 val |= PORT_LOGIC_SPEED_CHANGE; 131 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 132 133 for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) { 134 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); 135 if (!(val & PORT_LOGIC_SPEED_CHANGE)) 136 return 0; 137 usleep_range(10000, 11000); 138 } 139 140 return -ETIMEDOUT; 141 } 142 143 /* 144 * Enable LTSSM of this controller and manually initiate the speed change. 145 * Always return 0. 146 */ 147 static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) 148 { 149 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 150 int i, changes, ret; 151 152 if (rcar->drvdata->ltssm_control) { 153 ret = rcar->drvdata->ltssm_control(rcar, true); 154 if (ret) 155 return ret; 156 } 157 158 /* 159 * Require direct speed change with retrying here if the max_link_speed 160 * is PCIe Gen2 or higher. 161 */ 162 changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1; 163 164 /* 165 * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained. 166 * So, this needs remaining times for up to PCIe Gen4 if RC mode. 167 */ 168 if (changes && rcar->drvdata->mode == DW_PCIE_RC_TYPE) 169 changes--; 170 171 for (i = 0; i < changes; i++) { 172 /* It may not be connected in EP mode yet. So, break the loop */ 173 if (rcar_gen4_pcie_speed_change(dw)) 174 break; 175 } 176 177 return 0; 178 } 179 180 static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) 181 { 182 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 183 184 if (rcar->drvdata->ltssm_control) 185 rcar->drvdata->ltssm_control(rcar, false); 186 } 187 188 static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) 189 { 190 struct dw_pcie *dw = &rcar->dw; 191 u32 val; 192 int ret; 193 194 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); 195 if (ret) { 196 dev_err(dw->dev, "Enabling core clocks failed\n"); 197 return ret; 198 } 199 200 if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) { 201 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); 202 /* 203 * R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 204 * 21, 2025 page 585 Figure 9.3.2 Software Reset flow (B) 205 * indicates that for peripherals in HSC domain, after 206 * reset has been asserted by writing a matching reset bit 207 * into register SRCR, it is mandatory to wait 1ms. 208 */ 209 fsleep(1000); 210 } 211 212 val = readl(rcar->base + PCIEMSR0); 213 if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) { 214 val |= DEVICE_TYPE_RC; 215 } else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) { 216 val |= DEVICE_TYPE_EP; 217 } else { 218 ret = -EINVAL; 219 goto err_unprepare; 220 } 221 222 if (dw->num_lanes < 4) 223 val |= BIFUR_MOD_SET_ON; 224 225 writel(val, rcar->base + PCIEMSR0); 226 227 ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); 228 if (ret) 229 goto err_unprepare; 230 231 /* 232 * Assure the reset is latched and the core is ready for DBI access. 233 * On R-Car V4H, the PCIe reset is asynchronous and does not take 234 * effect immediately, but needs a short time to complete. In case 235 * DBI access happens in that short time, that access generates an 236 * SError. To make sure that condition can never happen, read back the 237 * state of the reset, which should turn the asynchronous reset into 238 * synchronous one, and wait a little over 1ms to add additional 239 * safety margin. 240 */ 241 reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc); 242 fsleep(1000); 243 244 if (rcar->drvdata->additional_common_init) 245 rcar->drvdata->additional_common_init(rcar); 246 247 return 0; 248 249 err_unprepare: 250 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); 251 252 return ret; 253 } 254 255 static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) 256 { 257 struct dw_pcie *dw = &rcar->dw; 258 259 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); 260 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks); 261 } 262 263 static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar) 264 { 265 struct device *dev = rcar->dw.dev; 266 int err; 267 268 pm_runtime_enable(dev); 269 err = pm_runtime_resume_and_get(dev); 270 if (err < 0) { 271 dev_err(dev, "Runtime resume failed\n"); 272 pm_runtime_disable(dev); 273 } 274 275 return err; 276 } 277 278 static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar) 279 { 280 struct device *dev = rcar->dw.dev; 281 282 pm_runtime_put(dev); 283 pm_runtime_disable(dev); 284 } 285 286 static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar) 287 { 288 rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy"); 289 if (IS_ERR(rcar->phy_base)) 290 return PTR_ERR(rcar->phy_base); 291 292 /* Renesas-specific registers */ 293 rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app"); 294 295 return PTR_ERR_OR_ZERO(rcar->base); 296 } 297 298 static const struct dw_pcie_ops dw_pcie_ops = { 299 .start_link = rcar_gen4_pcie_start_link, 300 .stop_link = rcar_gen4_pcie_stop_link, 301 .link_up = rcar_gen4_pcie_link_up, 302 }; 303 304 static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) 305 { 306 struct device *dev = &pdev->dev; 307 struct rcar_gen4_pcie *rcar; 308 309 rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL); 310 if (!rcar) 311 return ERR_PTR(-ENOMEM); 312 313 rcar->dw.ops = &dw_pcie_ops; 314 rcar->dw.dev = dev; 315 rcar->pdev = pdev; 316 rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; 317 dw_pcie_cap_set(&rcar->dw, REQ_RES); 318 platform_set_drvdata(pdev, rcar); 319 320 return rcar; 321 } 322 323 static int rcar_gen4_pcie_host_msi_addr(struct dw_pcie_rp *pp, u32 *msi_addr) 324 { 325 struct dw_pcie *dw = to_dw_pcie_from_pp(pp); 326 struct device_node *msi_node = NULL; 327 struct device *dev = dw->dev; 328 struct resource res; 329 u64 addr; 330 int ret; 331 332 /* 333 * Either the "msi-parent" or the "msi-map" phandle needs to exist 334 * to obtain the MSI node. 335 */ 336 of_msi_xlate(dev, &msi_node, 0); 337 if (!msi_node) 338 return -ENODEV; 339 340 /* Check if "msi-parent" or the "msi-map" points to ARM GICv3 ITS. */ 341 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) 342 return dev_err_probe(dev, -ENODEV, "Compatible MSI controller not found\n"); 343 344 /* Derive GITS_TRANSLATER address from GICv3 */ 345 ret = of_address_to_resource(msi_node, 0, &res); 346 if (ret < 0) 347 return dev_err_probe(dev, ret, "MSI controller resources not obtained\n"); 348 349 addr = res.start + GITS_TRANSLATER; 350 if (addr >= SZ_4G) 351 return dev_err_probe(dev, -EINVAL, "MSI controller address above 32bit range\n"); 352 353 *msi_addr = addr; 354 return 0; 355 } 356 357 static int rcar_gen4_pcie_host_msi_init(struct dw_pcie_rp *pp) 358 { 359 struct dw_pcie *dw = to_dw_pcie_from_pp(pp); 360 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 361 u32 val; 362 int ret; 363 364 /* Make sure MSICAP0 MSIE is configured. */ 365 val = dw_pcie_readl_dbi(dw, MSICAP0); 366 if (pci_msi_enabled()) 367 val |= MSICAP0_MSIE; 368 else 369 val &= ~MSICAP0_MSIE; 370 dw_pcie_writel_dbi(dw, MSICAP0, val); 371 372 if (!pci_msi_enabled() || pp->use_imsi_rx) { 373 /* Clear AXIINTC mapping. */ 374 writel(0, rcar->base + AXIINTCADDR); 375 writel(0, rcar->base + AXIINTCCONT); 376 } else { 377 ret = rcar_gen4_pcie_host_msi_addr(pp, &val); 378 if (ret) 379 goto err; 380 381 /* Point AXIINTC to GIC ITS and enable. */ 382 writel(val, rcar->base + AXIINTCADDR); 383 writel(INTC_EN | INTC_MASK, rcar->base + AXIINTCCONT); 384 } 385 386 /* Configure MSI interrupt signal */ 387 val = readl(rcar->base + PCIEINTSTS0EN); 388 if (pci_msi_enabled()) 389 val |= MSI_CTRL_INT; 390 else 391 val &= ~MSI_CTRL_INT; 392 writel(val, rcar->base + PCIEINTSTS0EN); 393 394 return 0; 395 396 err: 397 /* Deconfigure MSICAP0 MSIE. */ 398 val = dw_pcie_readl_dbi(dw, MSICAP0); 399 val &= ~MSICAP0_MSIE; 400 dw_pcie_writel_dbi(dw, MSICAP0, val); 401 402 /* Clear AXIINTC mapping. */ 403 writel(0, rcar->base + AXIINTCADDR); 404 writel(0, rcar->base + AXIINTCCONT); 405 406 /* Deconfigure MSI interrupt signal */ 407 val = readl(rcar->base + PCIEINTSTS0EN); 408 val &= ~MSI_CTRL_INT; 409 writel(val, rcar->base + PCIEINTSTS0EN); 410 411 return ret; 412 } 413 414 /* Host mode */ 415 static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) 416 { 417 struct dw_pcie *dw = to_dw_pcie_from_pp(pp); 418 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 419 int ret; 420 421 gpiod_set_value_cansleep(dw->pe_rst, 1); 422 423 ret = rcar_gen4_pcie_common_init(rcar); 424 if (ret) 425 return ret; 426 427 /* 428 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode 429 * Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we 430 * should disable two BARs to avoid unnecessary memory assignment 431 * during device enumeration. 432 */ 433 dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0); 434 dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0); 435 436 ret = rcar_gen4_pcie_host_msi_init(pp); 437 if (ret) 438 goto err; 439 440 msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */ 441 442 gpiod_set_value_cansleep(dw->pe_rst, 0); 443 444 return 0; 445 446 err: 447 rcar_gen4_pcie_common_deinit(rcar); 448 return ret; 449 } 450 451 static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp) 452 { 453 struct dw_pcie *dw = to_dw_pcie_from_pp(pp); 454 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 455 456 gpiod_set_value_cansleep(dw->pe_rst, 1); 457 rcar_gen4_pcie_common_deinit(rcar); 458 } 459 460 static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = { 461 .init = rcar_gen4_pcie_host_init, 462 .deinit = rcar_gen4_pcie_host_deinit, 463 }; 464 465 static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar) 466 { 467 struct dw_pcie_rp *pp = &rcar->dw.pp; 468 469 if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST)) 470 return -ENODEV; 471 472 pp->num_vectors = MAX_MSI_IRQS; 473 pp->ops = &rcar_gen4_pcie_host_ops; 474 475 return dw_pcie_host_init(pp); 476 } 477 478 static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar) 479 { 480 dw_pcie_host_deinit(&rcar->dw.pp); 481 } 482 483 /* Endpoint mode */ 484 static int rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep) 485 { 486 struct dw_pcie *dw = to_dw_pcie_from_ep(ep); 487 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); 488 int ret; 489 490 ret = rcar_gen4_pcie_common_init(rcar); 491 if (ret) 492 return ret; 493 494 writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN); 495 496 return 0; 497 } 498 499 static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar) 500 { 501 writel(0, rcar->base + PCIEDMAINTSTSEN); 502 rcar_gen4_pcie_common_deinit(rcar); 503 } 504 505 static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 506 unsigned int type, u16 interrupt_num) 507 { 508 struct dw_pcie *dw = to_dw_pcie_from_ep(ep); 509 510 switch (type) { 511 case PCI_IRQ_INTX: 512 return dw_pcie_ep_raise_intx_irq(ep, func_no); 513 case PCI_IRQ_MSI: 514 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 515 default: 516 dev_err(dw->dev, "Unknown IRQ type\n"); 517 return -EINVAL; 518 } 519 520 return 0; 521 } 522 523 static const struct pci_epc_features rcar_gen4_pcie_epc_features = { 524 DWC_EPC_COMMON_FEATURES, 525 .msi_capable = true, 526 .bar[BAR_0] = { .type = BAR_RESIZABLE, }, 527 .bar[BAR_1] = { .type = BAR_DISABLED, }, 528 .bar[BAR_2] = { .type = BAR_RESIZABLE, }, 529 .bar[BAR_3] = { .type = BAR_DISABLED, }, 530 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 }, 531 .bar[BAR_5] = { .type = BAR_DISABLED, }, 532 .align = SZ_4K, 533 }; 534 535 static const struct pci_epc_features* 536 rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep) 537 { 538 return &rcar_gen4_pcie_epc_features; 539 } 540 541 static unsigned int rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep, 542 u8 func_no) 543 { 544 return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET; 545 } 546 547 static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, 548 u8 func_no) 549 { 550 return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET; 551 } 552 553 static const struct dw_pcie_ep_ops pcie_ep_ops = { 554 .pre_init = rcar_gen4_pcie_ep_pre_init, 555 .raise_irq = rcar_gen4_pcie_ep_raise_irq, 556 .get_features = rcar_gen4_pcie_ep_get_features, 557 .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset, 558 .get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset, 559 }; 560 561 static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) 562 { 563 struct dw_pcie_ep *ep = &rcar->dw.ep; 564 struct device *dev = rcar->dw.dev; 565 int ret; 566 567 if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP)) 568 return -ENODEV; 569 570 ep->ops = &pcie_ep_ops; 571 572 ret = dw_pcie_ep_init(ep); 573 if (ret) { 574 rcar_gen4_pcie_ep_deinit(rcar); 575 return ret; 576 } 577 578 ret = dw_pcie_ep_init_registers(ep); 579 if (ret) { 580 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 581 dw_pcie_ep_deinit(ep); 582 rcar_gen4_pcie_ep_deinit(rcar); 583 } 584 585 pci_epc_init_notify(ep->epc); 586 587 return ret; 588 } 589 590 static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar) 591 { 592 dw_pcie_ep_deinit(&rcar->dw.ep); 593 rcar_gen4_pcie_ep_deinit(rcar); 594 } 595 596 /* Common */ 597 static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar) 598 { 599 rcar->drvdata = of_device_get_match_data(&rcar->pdev->dev); 600 if (!rcar->drvdata) 601 return -EINVAL; 602 603 switch (rcar->drvdata->mode) { 604 case DW_PCIE_RC_TYPE: 605 return rcar_gen4_add_dw_pcie_rp(rcar); 606 case DW_PCIE_EP_TYPE: 607 return rcar_gen4_add_dw_pcie_ep(rcar); 608 default: 609 return -EINVAL; 610 } 611 } 612 613 static int rcar_gen4_pcie_probe(struct platform_device *pdev) 614 { 615 struct rcar_gen4_pcie *rcar; 616 int err; 617 618 rcar = rcar_gen4_pcie_alloc(pdev); 619 if (IS_ERR(rcar)) 620 return PTR_ERR(rcar); 621 622 err = rcar_gen4_pcie_get_resources(rcar); 623 if (err) 624 return err; 625 626 err = rcar_gen4_pcie_prepare(rcar); 627 if (err) 628 return err; 629 630 err = rcar_gen4_add_dw_pcie(rcar); 631 if (err) 632 goto err_unprepare; 633 634 return 0; 635 636 err_unprepare: 637 rcar_gen4_pcie_unprepare(rcar); 638 639 return err; 640 } 641 642 static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar) 643 { 644 switch (rcar->drvdata->mode) { 645 case DW_PCIE_RC_TYPE: 646 rcar_gen4_remove_dw_pcie_rp(rcar); 647 break; 648 case DW_PCIE_EP_TYPE: 649 rcar_gen4_remove_dw_pcie_ep(rcar); 650 break; 651 default: 652 break; 653 } 654 } 655 656 static void rcar_gen4_pcie_remove(struct platform_device *pdev) 657 { 658 struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev); 659 660 rcar_gen4_remove_dw_pcie(rcar); 661 rcar_gen4_pcie_unprepare(rcar); 662 } 663 664 static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable) 665 { 666 u32 val; 667 668 val = readl(rcar->base + PCIERSTCTRL1); 669 if (enable) { 670 val |= APP_LTSSM_ENABLE; 671 val &= ~APP_HOLD_PHY_RST; 672 } else { 673 /* 674 * Since the datasheet of R-Car doesn't mention how to assert 675 * the APP_HOLD_PHY_RST, don't assert it again. Otherwise, 676 * hang-up issue happened in the dw_edma_core_off() when 677 * the controller didn't detect a PCI device. 678 */ 679 val &= ~APP_LTSSM_ENABLE; 680 } 681 writel(val, rcar->base + PCIERSTCTRL1); 682 683 return 0; 684 } 685 686 static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar) 687 { 688 struct dw_pcie *dw = &rcar->dw; 689 u32 val; 690 691 val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); 692 val &= ~PORT_LANE_SKEW_INSERT_MASK; 693 if (dw->num_lanes < 4) 694 val |= BIT(6); 695 dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); 696 697 val = readl(rcar->base + PCIEPWRMNGCTRL); 698 val |= APP_CLK_REQ_N | APP_CLK_PM_EN; 699 writel(val, rcar->base + PCIEPWRMNGCTRL); 700 } 701 702 static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, 703 u32 offset, u32 mask, u32 val) 704 { 705 u32 tmp; 706 707 tmp = readl(rcar->phy_base + offset); 708 tmp &= ~mask; 709 tmp |= val; 710 writel(tmp, rcar->phy_base + offset); 711 } 712 713 /* 714 * SoC datasheet suggests checking port logic register bits during firmware 715 * write. If read returns non-zero value, then this function returns -EAGAIN 716 * indicating that the write needs to be done again. If read returns zero, 717 * then return 0 to indicate success. 718 */ 719 static int rcar_gen4_pcie_reg_test_bit(struct rcar_gen4_pcie *rcar, 720 u32 offset, u32 mask) 721 { 722 struct dw_pcie *dw = &rcar->dw; 723 724 if (dw_pcie_readl_dbi(dw, offset) & mask) 725 return -EAGAIN; 726 727 return 0; 728 } 729 730 static int rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie *rcar) 731 { 732 /* The check_addr values are magical numbers in the datasheet */ 733 static const u32 check_addr[] = { 734 0x00101018, 735 0x00101118, 736 0x00101021, 737 0x00101121, 738 }; 739 struct dw_pcie *dw = &rcar->dw; 740 const struct firmware *fw; 741 unsigned int i, timeout; 742 u32 data; 743 int ret; 744 745 ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev); 746 if (ret) { 747 dev_err(dw->dev, "Failed to load firmware (%s): %d\n", 748 RCAR_GEN4_PCIE_FIRMWARE_NAME, ret); 749 return ret; 750 } 751 752 for (i = 0; i < (fw->size / 2); i++) { 753 data = fw->data[(i * 2) + 1] << 8 | fw->data[i * 2]; 754 timeout = 100; 755 do { 756 dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i); 757 dw_pcie_writel_dbi(dw, PRTLGC90, data); 758 if (!rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30))) 759 break; 760 if (!(--timeout)) { 761 ret = -ETIMEDOUT; 762 goto exit; 763 } 764 usleep_range(100, 200); 765 } while (1); 766 } 767 768 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(17), BIT(17)); 769 770 for (i = 0; i < ARRAY_SIZE(check_addr); i++) { 771 timeout = 100; 772 do { 773 dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]); 774 ret = rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30)); 775 ret |= rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC90, BIT(0)); 776 if (!ret) 777 break; 778 if (!(--timeout)) { 779 ret = -ETIMEDOUT; 780 goto exit; 781 } 782 usleep_range(100, 200); 783 } while (1); 784 } 785 786 exit: 787 release_firmware(fw); 788 789 return ret; 790 } 791 792 static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable) 793 { 794 struct dw_pcie *dw = &rcar->dw; 795 u32 val; 796 int ret; 797 798 if (!enable) { 799 val = readl(rcar->base + PCIERSTCTRL1); 800 val &= ~APP_LTSSM_ENABLE; 801 writel(val, rcar->base + PCIERSTCTRL1); 802 803 return 0; 804 } 805 806 val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE); 807 val |= PORT_FORCE_DO_DESKEW_FOR_SRIS; 808 dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val); 809 810 val = readl(rcar->base + PCIEMSR0); 811 val |= APP_SRIS_MODE; 812 writel(val, rcar->base + PCIEMSR0); 813 814 /* 815 * The R-Car Gen4 datasheet doesn't describe the PHY registers' name. 816 * But, the initialization procedure describes these offsets. So, 817 * this driver has magical offset numbers. 818 */ 819 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(28), 0); 820 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(20), 0); 821 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(12), 0); 822 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(4), 0); 823 824 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22)); 825 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16)); 826 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6)); 827 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(1, 0)); 828 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15)); 829 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x514, BIT(26), BIT(26)); 830 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(16), 0); 831 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(19), BIT(19)); 832 833 val = readl(rcar->base + PCIERSTCTRL1); 834 val &= ~APP_HOLD_PHY_RST; 835 writel(val, rcar->base + PCIERSTCTRL1); 836 837 ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 100, 10000); 838 if (ret < 0) 839 return ret; 840 841 ret = rcar_gen4_pcie_download_phy_firmware(rcar); 842 if (ret) 843 return ret; 844 845 val = readl(rcar->base + PCIERSTCTRL1); 846 val |= APP_LTSSM_ENABLE; 847 writel(val, rcar->base + PCIERSTCTRL1); 848 849 return 0; 850 } 851 852 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie = { 853 .ltssm_control = r8a779f0_pcie_ltssm_control, 854 .mode = DW_PCIE_RC_TYPE, 855 }; 856 857 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep = { 858 .ltssm_control = r8a779f0_pcie_ltssm_control, 859 .mode = DW_PCIE_EP_TYPE, 860 }; 861 862 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie = { 863 .additional_common_init = rcar_gen4_pcie_additional_common_init, 864 .ltssm_control = rcar_gen4_pcie_ltssm_control, 865 .mode = DW_PCIE_RC_TYPE, 866 }; 867 868 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep = { 869 .additional_common_init = rcar_gen4_pcie_additional_common_init, 870 .ltssm_control = rcar_gen4_pcie_ltssm_control, 871 .mode = DW_PCIE_EP_TYPE, 872 }; 873 874 static const struct of_device_id rcar_gen4_pcie_of_match[] = { 875 { 876 .compatible = "renesas,r8a779f0-pcie", 877 .data = &drvdata_r8a779f0_pcie, 878 }, 879 { 880 .compatible = "renesas,r8a779f0-pcie-ep", 881 .data = &drvdata_r8a779f0_pcie_ep, 882 }, 883 { 884 .compatible = "renesas,rcar-gen4-pcie", 885 .data = &drvdata_rcar_gen4_pcie, 886 }, 887 { 888 .compatible = "renesas,rcar-gen4-pcie-ep", 889 .data = &drvdata_rcar_gen4_pcie_ep, 890 }, 891 {}, 892 }; 893 MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match); 894 895 static struct platform_driver rcar_gen4_pcie_driver = { 896 .driver = { 897 .name = "pcie-rcar-gen4", 898 .of_match_table = rcar_gen4_pcie_of_match, 899 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 900 }, 901 .probe = rcar_gen4_pcie_probe, 902 .remove = rcar_gen4_pcie_remove, 903 }; 904 module_platform_driver(rcar_gen4_pcie_driver); 905 906 MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver"); 907 MODULE_LICENSE("GPL"); 908