1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe root complex driver 4 * 5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 * Copyright 2015 Linaro Limited. 7 * 8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/crc8.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/limits.h> 22 #include <linux/init.h> 23 #include <linux/of.h> 24 #include <linux/pci.h> 25 #include <linux/pm_opp.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/phy/pcie.h> 29 #include <linux/phy/phy.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/reset.h> 32 #include <linux/slab.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 36 #include "../../pci.h" 37 #include "pcie-designware.h" 38 #include "pcie-qcom-common.h" 39 40 /* PARF registers */ 41 #define PARF_SYS_CTRL 0x00 42 #define PARF_PM_CTRL 0x20 43 #define PARF_PCS_DEEMPH 0x34 44 #define PARF_PCS_SWING 0x38 45 #define PARF_PHY_CTRL 0x40 46 #define PARF_PHY_REFCLK 0x4c 47 #define PARF_CONFIG_BITS 0x50 48 #define PARF_DBI_BASE_ADDR 0x168 49 #define PARF_SLV_ADDR_SPACE_SIZE 0x16c 50 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 51 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 52 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 53 #define PARF_Q2A_FLUSH 0x1ac 54 #define PARF_LTSSM 0x1b0 55 #define PARF_INT_ALL_STATUS 0x224 56 #define PARF_INT_ALL_CLEAR 0x228 57 #define PARF_INT_ALL_MASK 0x22c 58 #define PARF_SID_OFFSET 0x234 59 #define PARF_BDF_TRANSLATE_CFG 0x24c 60 #define PARF_DBI_BASE_ADDR_V2 0x350 61 #define PARF_DBI_BASE_ADDR_V2_HI 0x354 62 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 63 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c 64 #define PARF_NO_SNOOP_OVERIDE 0x3d4 65 #define PARF_ATU_BASE_ADDR 0x634 66 #define PARF_ATU_BASE_ADDR_HI 0x638 67 #define PARF_DEVICE_TYPE 0x1000 68 #define PARF_BDF_TO_SID_TABLE_N 0x2000 69 #define PARF_BDF_TO_SID_CFG 0x2c00 70 71 /* ELBI registers */ 72 #define ELBI_SYS_CTRL 0x04 73 74 /* DBI registers */ 75 #define AXI_MSTR_RESP_COMP_CTRL0 0x818 76 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c 77 78 /* MHI registers */ 79 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 80 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 81 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 82 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 83 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 84 85 /* PARF_SYS_CTRL register fields */ 86 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 87 #define MST_WAKEUP_EN BIT(13) 88 #define SLV_WAKEUP_EN BIT(12) 89 #define MSTR_ACLK_CGC_DIS BIT(10) 90 #define SLV_ACLK_CGC_DIS BIT(9) 91 #define CORE_CLK_CGC_DIS BIT(6) 92 #define AUX_PWR_DET BIT(4) 93 #define L23_CLK_RMV_DIS BIT(2) 94 #define L1_CLK_RMV_DIS BIT(1) 95 96 /* PARF_PM_CTRL register fields */ 97 #define REQ_NOT_ENTR_L1 BIT(5) 98 99 /* PARF_PCS_DEEMPH register fields */ 100 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) 101 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) 102 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) 103 104 /* PARF_PCS_SWING register fields */ 105 #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) 106 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) 107 108 /* PARF_PHY_CTRL register fields */ 109 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) 110 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) 111 #define PHY_TEST_PWR_DOWN BIT(0) 112 113 /* PARF_PHY_REFCLK register fields */ 114 #define PHY_REFCLK_SSP_EN BIT(16) 115 #define PHY_REFCLK_USE_PAD BIT(12) 116 117 /* PARF_CONFIG_BITS register fields */ 118 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) 119 120 /* PARF_SLV_ADDR_SPACE_SIZE register value */ 121 #define SLV_ADDR_SPACE_SZ 0x80000000 122 123 /* PARF_MHI_CLOCK_RESET_CTRL register fields */ 124 #define AHB_CLK_EN BIT(0) 125 #define MSTR_AXI_CLK_EN BIT(1) 126 #define BYPASS BIT(4) 127 128 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 129 #define EN BIT(31) 130 131 /* PARF_LTSSM register fields */ 132 #define LTSSM_EN BIT(8) 133 134 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 135 #define PARF_INT_ALL_LINK_UP BIT(13) 136 137 /* PARF_NO_SNOOP_OVERIDE register fields */ 138 #define WR_NO_SNOOP_OVERIDE_EN BIT(1) 139 #define RD_NO_SNOOP_OVERIDE_EN BIT(3) 140 141 /* PARF_DEVICE_TYPE register fields */ 142 #define DEVICE_TYPE_RC 0x4 143 144 /* PARF_BDF_TO_SID_CFG fields */ 145 #define BDF_TO_SID_BYPASS BIT(0) 146 147 /* ELBI_SYS_CTRL register fields */ 148 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) 149 150 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ 151 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 152 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 153 154 /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ 155 #define CFG_BRIDGE_SB_INIT BIT(0) 156 157 /* PCI_EXP_SLTCAP register fields */ 158 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) 159 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) 160 #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ 161 PCI_EXP_SLTCAP_PCP | \ 162 PCI_EXP_SLTCAP_MRLSP | \ 163 PCI_EXP_SLTCAP_AIP | \ 164 PCI_EXP_SLTCAP_PIP | \ 165 PCI_EXP_SLTCAP_HPS | \ 166 PCI_EXP_SLTCAP_EIP | \ 167 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ 168 PCIE_CAP_SLOT_POWER_LIMIT_SCALE) 169 170 #define PERST_DELAY_US 1000 171 172 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 173 174 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 175 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) 176 177 struct qcom_pcie_resources_1_0_0 { 178 struct clk_bulk_data *clks; 179 int num_clks; 180 struct reset_control *core; 181 struct regulator *vdda; 182 }; 183 184 #define QCOM_PCIE_2_1_0_MAX_RESETS 6 185 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 186 struct qcom_pcie_resources_2_1_0 { 187 struct clk_bulk_data *clks; 188 int num_clks; 189 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; 190 int num_resets; 191 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; 192 }; 193 194 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 195 struct qcom_pcie_resources_2_3_2 { 196 struct clk_bulk_data *clks; 197 int num_clks; 198 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; 199 }; 200 201 #define QCOM_PCIE_2_3_3_MAX_RESETS 7 202 struct qcom_pcie_resources_2_3_3 { 203 struct clk_bulk_data *clks; 204 int num_clks; 205 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; 206 }; 207 208 #define QCOM_PCIE_2_4_0_MAX_RESETS 12 209 struct qcom_pcie_resources_2_4_0 { 210 struct clk_bulk_data *clks; 211 int num_clks; 212 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; 213 int num_resets; 214 }; 215 216 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 217 struct qcom_pcie_resources_2_7_0 { 218 struct clk_bulk_data *clks; 219 int num_clks; 220 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; 221 struct reset_control *rst; 222 }; 223 224 struct qcom_pcie_resources_2_9_0 { 225 struct clk_bulk_data *clks; 226 int num_clks; 227 struct reset_control *rst; 228 }; 229 230 union qcom_pcie_resources { 231 struct qcom_pcie_resources_1_0_0 v1_0_0; 232 struct qcom_pcie_resources_2_1_0 v2_1_0; 233 struct qcom_pcie_resources_2_3_2 v2_3_2; 234 struct qcom_pcie_resources_2_3_3 v2_3_3; 235 struct qcom_pcie_resources_2_4_0 v2_4_0; 236 struct qcom_pcie_resources_2_7_0 v2_7_0; 237 struct qcom_pcie_resources_2_9_0 v2_9_0; 238 }; 239 240 struct qcom_pcie; 241 242 struct qcom_pcie_ops { 243 int (*get_resources)(struct qcom_pcie *pcie); 244 int (*init)(struct qcom_pcie *pcie); 245 int (*post_init)(struct qcom_pcie *pcie); 246 void (*host_post_init)(struct qcom_pcie *pcie); 247 void (*deinit)(struct qcom_pcie *pcie); 248 void (*ltssm_enable)(struct qcom_pcie *pcie); 249 int (*config_sid)(struct qcom_pcie *pcie); 250 }; 251 252 /** 253 * struct qcom_pcie_cfg - Per SoC config struct 254 * @ops: qcom PCIe ops structure 255 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache 256 * snooping 257 */ 258 struct qcom_pcie_cfg { 259 const struct qcom_pcie_ops *ops; 260 bool override_no_snoop; 261 bool no_l0s; 262 }; 263 264 struct qcom_pcie { 265 struct dw_pcie *pci; 266 void __iomem *parf; /* DT parf */ 267 void __iomem *elbi; /* DT elbi */ 268 void __iomem *mhi; 269 union qcom_pcie_resources res; 270 struct phy *phy; 271 struct gpio_desc *reset; 272 struct icc_path *icc_mem; 273 struct icc_path *icc_cpu; 274 const struct qcom_pcie_cfg *cfg; 275 struct dentry *debugfs; 276 bool suspended; 277 bool use_pm_opp; 278 }; 279 280 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) 281 282 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 283 { 284 gpiod_set_value_cansleep(pcie->reset, 1); 285 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 286 } 287 288 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) 289 { 290 /* Ensure that PERST has been asserted for at least 100 ms */ 291 msleep(100); 292 gpiod_set_value_cansleep(pcie->reset, 0); 293 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 294 } 295 296 static int qcom_pcie_start_link(struct dw_pcie *pci) 297 { 298 struct qcom_pcie *pcie = to_qcom_pcie(pci); 299 300 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { 301 qcom_pcie_common_set_16gt_equalization(pci); 302 qcom_pcie_common_set_16gt_lane_margining(pci); 303 } 304 305 /* Enable Link Training state machine */ 306 if (pcie->cfg->ops->ltssm_enable) 307 pcie->cfg->ops->ltssm_enable(pcie); 308 309 return 0; 310 } 311 312 static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) 313 { 314 struct qcom_pcie *pcie = to_qcom_pcie(pci); 315 u16 offset; 316 u32 val; 317 318 if (!pcie->cfg->no_l0s) 319 return; 320 321 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 322 323 dw_pcie_dbi_ro_wr_en(pci); 324 325 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 326 val &= ~PCI_EXP_LNKCAP_ASPM_L0S; 327 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 328 329 dw_pcie_dbi_ro_wr_dis(pci); 330 } 331 332 static void qcom_pcie_clear_hpc(struct dw_pcie *pci) 333 { 334 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 335 u32 val; 336 337 dw_pcie_dbi_ro_wr_en(pci); 338 339 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); 340 val &= ~PCI_EXP_SLTCAP_HPC; 341 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); 342 343 dw_pcie_dbi_ro_wr_dis(pci); 344 } 345 346 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) 347 { 348 struct dw_pcie *pci = pcie->pci; 349 350 if (pci->dbi_phys_addr) { 351 /* 352 * PARF_DBI_BASE_ADDR register is in CPU domain and require to 353 * be programmed with CPU physical address. 354 */ 355 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 356 PARF_DBI_BASE_ADDR); 357 writel(SLV_ADDR_SPACE_SZ, pcie->parf + 358 PARF_SLV_ADDR_SPACE_SIZE); 359 } 360 } 361 362 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) 363 { 364 struct dw_pcie *pci = pcie->pci; 365 366 if (pci->dbi_phys_addr) { 367 /* 368 * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are 369 * in CPU domain and require to be programmed with CPU 370 * physical addresses. 371 */ 372 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 373 PARF_DBI_BASE_ADDR_V2); 374 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + 375 PARF_DBI_BASE_ADDR_V2_HI); 376 377 if (pci->atu_phys_addr) { 378 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + 379 PARF_ATU_BASE_ADDR); 380 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + 381 PARF_ATU_BASE_ADDR_HI); 382 } 383 384 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); 385 writel(SLV_ADDR_SPACE_SZ, pcie->parf + 386 PARF_SLV_ADDR_SPACE_SIZE_V2_HI); 387 } 388 } 389 390 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 391 { 392 u32 val; 393 394 /* enable link training */ 395 val = readl(pcie->elbi + ELBI_SYS_CTRL); 396 val |= ELBI_SYS_CTRL_LT_ENABLE; 397 writel(val, pcie->elbi + ELBI_SYS_CTRL); 398 } 399 400 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 401 { 402 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 403 struct dw_pcie *pci = pcie->pci; 404 struct device *dev = pci->dev; 405 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); 406 int ret; 407 408 res->supplies[0].supply = "vdda"; 409 res->supplies[1].supply = "vdda_phy"; 410 res->supplies[2].supply = "vdda_refclk"; 411 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 412 res->supplies); 413 if (ret) 414 return ret; 415 416 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 417 if (res->num_clks < 0) { 418 dev_err(dev, "Failed to get clocks\n"); 419 return res->num_clks; 420 } 421 422 res->resets[0].id = "pci"; 423 res->resets[1].id = "axi"; 424 res->resets[2].id = "ahb"; 425 res->resets[3].id = "por"; 426 res->resets[4].id = "phy"; 427 res->resets[5].id = "ext"; 428 429 /* ext is optional on APQ8016 */ 430 res->num_resets = is_apq ? 5 : 6; 431 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 432 if (ret < 0) 433 return ret; 434 435 return 0; 436 } 437 438 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 439 { 440 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 441 442 clk_bulk_disable_unprepare(res->num_clks, res->clks); 443 reset_control_bulk_assert(res->num_resets, res->resets); 444 445 writel(1, pcie->parf + PARF_PHY_CTRL); 446 447 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 448 } 449 450 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 451 { 452 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 453 struct dw_pcie *pci = pcie->pci; 454 struct device *dev = pci->dev; 455 int ret; 456 457 /* reset the PCIe interface as uboot can leave it undefined state */ 458 ret = reset_control_bulk_assert(res->num_resets, res->resets); 459 if (ret < 0) { 460 dev_err(dev, "cannot assert resets\n"); 461 return ret; 462 } 463 464 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 465 if (ret < 0) { 466 dev_err(dev, "cannot enable regulators\n"); 467 return ret; 468 } 469 470 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 471 if (ret < 0) { 472 dev_err(dev, "cannot deassert resets\n"); 473 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 474 return ret; 475 } 476 477 return 0; 478 } 479 480 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) 481 { 482 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 483 struct dw_pcie *pci = pcie->pci; 484 struct device *dev = pci->dev; 485 struct device_node *node = dev->of_node; 486 u32 val; 487 int ret; 488 489 /* enable PCIe clocks and resets */ 490 val = readl(pcie->parf + PARF_PHY_CTRL); 491 val &= ~PHY_TEST_PWR_DOWN; 492 writel(val, pcie->parf + PARF_PHY_CTRL); 493 494 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 495 if (ret) 496 return ret; 497 498 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || 499 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { 500 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | 501 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | 502 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), 503 pcie->parf + PARF_PCS_DEEMPH); 504 writel(PCS_SWING_TX_SWING_FULL(120) | 505 PCS_SWING_TX_SWING_LOW(120), 506 pcie->parf + PARF_PCS_SWING); 507 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); 508 } 509 510 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { 511 /* set TX termination offset */ 512 val = readl(pcie->parf + PARF_PHY_CTRL); 513 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; 514 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); 515 writel(val, pcie->parf + PARF_PHY_CTRL); 516 } 517 518 /* enable external reference clock */ 519 val = readl(pcie->parf + PARF_PHY_REFCLK); 520 /* USE_PAD is required only for ipq806x */ 521 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) 522 val &= ~PHY_REFCLK_USE_PAD; 523 val |= PHY_REFCLK_SSP_EN; 524 writel(val, pcie->parf + PARF_PHY_REFCLK); 525 526 /* wait for clock acquisition */ 527 usleep_range(1000, 1500); 528 529 /* Set the Max TLP size to 2K, instead of using default of 4K */ 530 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, 531 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); 532 writel(CFG_BRIDGE_SB_INIT, 533 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); 534 535 qcom_pcie_clear_hpc(pcie->pci); 536 537 return 0; 538 } 539 540 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) 541 { 542 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 543 struct dw_pcie *pci = pcie->pci; 544 struct device *dev = pci->dev; 545 546 res->vdda = devm_regulator_get(dev, "vdda"); 547 if (IS_ERR(res->vdda)) 548 return PTR_ERR(res->vdda); 549 550 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 551 if (res->num_clks < 0) { 552 dev_err(dev, "Failed to get clocks\n"); 553 return res->num_clks; 554 } 555 556 res->core = devm_reset_control_get_exclusive(dev, "core"); 557 return PTR_ERR_OR_ZERO(res->core); 558 } 559 560 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) 561 { 562 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 563 564 reset_control_assert(res->core); 565 clk_bulk_disable_unprepare(res->num_clks, res->clks); 566 regulator_disable(res->vdda); 567 } 568 569 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) 570 { 571 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 572 struct dw_pcie *pci = pcie->pci; 573 struct device *dev = pci->dev; 574 int ret; 575 576 ret = reset_control_deassert(res->core); 577 if (ret) { 578 dev_err(dev, "cannot deassert core reset\n"); 579 return ret; 580 } 581 582 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 583 if (ret) { 584 dev_err(dev, "cannot prepare/enable clocks\n"); 585 goto err_assert_reset; 586 } 587 588 ret = regulator_enable(res->vdda); 589 if (ret) { 590 dev_err(dev, "cannot enable vdda regulator\n"); 591 goto err_disable_clks; 592 } 593 594 return 0; 595 596 err_disable_clks: 597 clk_bulk_disable_unprepare(res->num_clks, res->clks); 598 err_assert_reset: 599 reset_control_assert(res->core); 600 601 return ret; 602 } 603 604 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 605 { 606 qcom_pcie_configure_dbi_base(pcie); 607 608 if (IS_ENABLED(CONFIG_PCI_MSI)) { 609 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 610 611 val |= EN; 612 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 613 } 614 615 qcom_pcie_clear_hpc(pcie->pci); 616 617 return 0; 618 } 619 620 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) 621 { 622 u32 val; 623 624 /* enable link training */ 625 val = readl(pcie->parf + PARF_LTSSM); 626 val |= LTSSM_EN; 627 writel(val, pcie->parf + PARF_LTSSM); 628 } 629 630 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 631 { 632 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 633 struct dw_pcie *pci = pcie->pci; 634 struct device *dev = pci->dev; 635 int ret; 636 637 res->supplies[0].supply = "vdda"; 638 res->supplies[1].supply = "vddpe-3v3"; 639 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 640 res->supplies); 641 if (ret) 642 return ret; 643 644 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 645 if (res->num_clks < 0) { 646 dev_err(dev, "Failed to get clocks\n"); 647 return res->num_clks; 648 } 649 650 return 0; 651 } 652 653 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 654 { 655 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 656 657 clk_bulk_disable_unprepare(res->num_clks, res->clks); 658 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 659 } 660 661 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 662 { 663 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 664 struct dw_pcie *pci = pcie->pci; 665 struct device *dev = pci->dev; 666 int ret; 667 668 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 669 if (ret < 0) { 670 dev_err(dev, "cannot enable regulators\n"); 671 return ret; 672 } 673 674 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 675 if (ret) { 676 dev_err(dev, "cannot prepare/enable clocks\n"); 677 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 678 return ret; 679 } 680 681 return 0; 682 } 683 684 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 685 { 686 u32 val; 687 688 /* enable PCIe clocks and resets */ 689 val = readl(pcie->parf + PARF_PHY_CTRL); 690 val &= ~PHY_TEST_PWR_DOWN; 691 writel(val, pcie->parf + PARF_PHY_CTRL); 692 693 qcom_pcie_configure_dbi_base(pcie); 694 695 /* MAC PHY_POWERDOWN MUX DISABLE */ 696 val = readl(pcie->parf + PARF_SYS_CTRL); 697 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 698 writel(val, pcie->parf + PARF_SYS_CTRL); 699 700 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 701 val |= BYPASS; 702 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 703 704 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 705 val |= EN; 706 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 707 708 qcom_pcie_clear_hpc(pcie->pci); 709 710 return 0; 711 } 712 713 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) 714 { 715 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 716 struct dw_pcie *pci = pcie->pci; 717 struct device *dev = pci->dev; 718 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); 719 int ret; 720 721 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 722 if (res->num_clks < 0) { 723 dev_err(dev, "Failed to get clocks\n"); 724 return res->num_clks; 725 } 726 727 res->resets[0].id = "axi_m"; 728 res->resets[1].id = "axi_s"; 729 res->resets[2].id = "axi_m_sticky"; 730 res->resets[3].id = "pipe_sticky"; 731 res->resets[4].id = "pwr"; 732 res->resets[5].id = "ahb"; 733 res->resets[6].id = "pipe"; 734 res->resets[7].id = "axi_m_vmid"; 735 res->resets[8].id = "axi_s_xpu"; 736 res->resets[9].id = "parf"; 737 res->resets[10].id = "phy"; 738 res->resets[11].id = "phy_ahb"; 739 740 res->num_resets = is_ipq ? 12 : 6; 741 742 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 743 if (ret < 0) 744 return ret; 745 746 return 0; 747 } 748 749 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) 750 { 751 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 752 753 reset_control_bulk_assert(res->num_resets, res->resets); 754 clk_bulk_disable_unprepare(res->num_clks, res->clks); 755 } 756 757 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 758 { 759 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 760 struct dw_pcie *pci = pcie->pci; 761 struct device *dev = pci->dev; 762 int ret; 763 764 ret = reset_control_bulk_assert(res->num_resets, res->resets); 765 if (ret < 0) { 766 dev_err(dev, "cannot assert resets\n"); 767 return ret; 768 } 769 770 usleep_range(10000, 12000); 771 772 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 773 if (ret < 0) { 774 dev_err(dev, "cannot deassert resets\n"); 775 return ret; 776 } 777 778 usleep_range(10000, 12000); 779 780 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 781 if (ret) { 782 reset_control_bulk_assert(res->num_resets, res->resets); 783 return ret; 784 } 785 786 return 0; 787 } 788 789 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) 790 { 791 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 792 struct dw_pcie *pci = pcie->pci; 793 struct device *dev = pci->dev; 794 int ret; 795 796 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 797 if (res->num_clks < 0) { 798 dev_err(dev, "Failed to get clocks\n"); 799 return res->num_clks; 800 } 801 802 res->rst[0].id = "axi_m"; 803 res->rst[1].id = "axi_s"; 804 res->rst[2].id = "pipe"; 805 res->rst[3].id = "axi_m_sticky"; 806 res->rst[4].id = "sticky"; 807 res->rst[5].id = "ahb"; 808 res->rst[6].id = "sleep"; 809 810 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); 811 if (ret < 0) 812 return ret; 813 814 return 0; 815 } 816 817 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) 818 { 819 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 820 821 clk_bulk_disable_unprepare(res->num_clks, res->clks); 822 } 823 824 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) 825 { 826 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 827 struct dw_pcie *pci = pcie->pci; 828 struct device *dev = pci->dev; 829 int ret; 830 831 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 832 if (ret < 0) { 833 dev_err(dev, "cannot assert resets\n"); 834 return ret; 835 } 836 837 usleep_range(2000, 2500); 838 839 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); 840 if (ret < 0) { 841 dev_err(dev, "cannot deassert resets\n"); 842 return ret; 843 } 844 845 /* 846 * Don't have a way to see if the reset has completed. 847 * Wait for some time. 848 */ 849 usleep_range(2000, 2500); 850 851 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 852 if (ret) { 853 dev_err(dev, "cannot prepare/enable clocks\n"); 854 goto err_assert_resets; 855 } 856 857 return 0; 858 859 err_assert_resets: 860 /* 861 * Not checking for failure, will anyway return 862 * the original failure in 'ret'. 863 */ 864 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 865 866 return ret; 867 } 868 869 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 870 { 871 struct dw_pcie *pci = pcie->pci; 872 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 873 u32 val; 874 875 val = readl(pcie->parf + PARF_PHY_CTRL); 876 val &= ~PHY_TEST_PWR_DOWN; 877 writel(val, pcie->parf + PARF_PHY_CTRL); 878 879 qcom_pcie_configure_dbi_atu_base(pcie); 880 881 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 882 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 883 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 884 pcie->parf + PARF_SYS_CTRL); 885 writel(0, pcie->parf + PARF_Q2A_FLUSH); 886 887 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); 888 889 dw_pcie_dbi_ro_wr_en(pci); 890 891 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 892 893 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 894 val &= ~PCI_EXP_LNKCAP_ASPMS; 895 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 896 897 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 898 PCI_EXP_DEVCTL2); 899 900 dw_pcie_dbi_ro_wr_dis(pci); 901 902 return 0; 903 } 904 905 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 906 { 907 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 908 struct dw_pcie *pci = pcie->pci; 909 struct device *dev = pci->dev; 910 int ret; 911 912 res->rst = devm_reset_control_array_get_exclusive(dev); 913 if (IS_ERR(res->rst)) 914 return PTR_ERR(res->rst); 915 916 res->supplies[0].supply = "vdda"; 917 res->supplies[1].supply = "vddpe-3v3"; 918 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 919 res->supplies); 920 if (ret) 921 return ret; 922 923 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 924 if (res->num_clks < 0) { 925 dev_err(dev, "Failed to get clocks\n"); 926 return res->num_clks; 927 } 928 929 return 0; 930 } 931 932 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 933 { 934 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 935 struct dw_pcie *pci = pcie->pci; 936 struct device *dev = pci->dev; 937 u32 val; 938 int ret; 939 940 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 941 if (ret < 0) { 942 dev_err(dev, "cannot enable regulators\n"); 943 return ret; 944 } 945 946 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 947 if (ret < 0) 948 goto err_disable_regulators; 949 950 ret = reset_control_assert(res->rst); 951 if (ret) { 952 dev_err(dev, "reset assert failed (%d)\n", ret); 953 goto err_disable_clocks; 954 } 955 956 usleep_range(1000, 1500); 957 958 ret = reset_control_deassert(res->rst); 959 if (ret) { 960 dev_err(dev, "reset deassert failed (%d)\n", ret); 961 goto err_disable_clocks; 962 } 963 964 /* Wait for reset to complete, required on SM8450 */ 965 usleep_range(1000, 1500); 966 967 /* configure PCIe to RC mode */ 968 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 969 970 /* enable PCIe clocks and resets */ 971 val = readl(pcie->parf + PARF_PHY_CTRL); 972 val &= ~PHY_TEST_PWR_DOWN; 973 writel(val, pcie->parf + PARF_PHY_CTRL); 974 975 qcom_pcie_configure_dbi_atu_base(pcie); 976 977 /* MAC PHY_POWERDOWN MUX DISABLE */ 978 val = readl(pcie->parf + PARF_SYS_CTRL); 979 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 980 writel(val, pcie->parf + PARF_SYS_CTRL); 981 982 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 983 val |= BYPASS; 984 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 985 986 /* Enable L1 and L1SS */ 987 val = readl(pcie->parf + PARF_PM_CTRL); 988 val &= ~REQ_NOT_ENTR_L1; 989 writel(val, pcie->parf + PARF_PM_CTRL); 990 991 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 992 val |= EN; 993 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 994 995 return 0; 996 err_disable_clocks: 997 clk_bulk_disable_unprepare(res->num_clks, res->clks); 998 err_disable_regulators: 999 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1000 1001 return ret; 1002 } 1003 1004 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) 1005 { 1006 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; 1007 1008 if (pcie_cfg->override_no_snoop) 1009 writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, 1010 pcie->parf + PARF_NO_SNOOP_OVERIDE); 1011 1012 qcom_pcie_clear_aspm_l0s(pcie->pci); 1013 qcom_pcie_clear_hpc(pcie->pci); 1014 1015 return 0; 1016 } 1017 1018 static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata) 1019 { 1020 /* 1021 * Downstream devices need to be in D0 state before enabling PCI PM 1022 * substates. 1023 */ 1024 pci_set_power_state_locked(pdev, PCI_D0); 1025 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 1026 1027 return 0; 1028 } 1029 1030 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) 1031 { 1032 struct dw_pcie_rp *pp = &pcie->pci->pp; 1033 1034 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); 1035 } 1036 1037 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) 1038 { 1039 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 1040 1041 clk_bulk_disable_unprepare(res->num_clks, res->clks); 1042 1043 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1044 } 1045 1046 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) 1047 { 1048 /* iommu map structure */ 1049 struct { 1050 u32 bdf; 1051 u32 phandle; 1052 u32 smmu_sid; 1053 u32 smmu_sid_len; 1054 } *map; 1055 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; 1056 struct device *dev = pcie->pci->dev; 1057 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 1058 int i, nr_map, size = 0; 1059 u32 smmu_sid_base; 1060 u32 val; 1061 1062 of_get_property(dev->of_node, "iommu-map", &size); 1063 if (!size) 1064 return 0; 1065 1066 /* Enable BDF to SID translation by disabling bypass mode (default) */ 1067 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); 1068 val &= ~BDF_TO_SID_BYPASS; 1069 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); 1070 1071 map = kzalloc(size, GFP_KERNEL); 1072 if (!map) 1073 return -ENOMEM; 1074 1075 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, 1076 size / sizeof(u32)); 1077 1078 nr_map = size / (sizeof(*map)); 1079 1080 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 1081 1082 /* Registers need to be zero out first */ 1083 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 1084 1085 /* Extract the SMMU SID base from the first entry of iommu-map */ 1086 smmu_sid_base = map[0].smmu_sid; 1087 1088 /* Look for an available entry to hold the mapping */ 1089 for (i = 0; i < nr_map; i++) { 1090 __be16 bdf_be = cpu_to_be16(map[i].bdf); 1091 u32 val; 1092 u8 hash; 1093 1094 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0); 1095 1096 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1097 1098 /* If the register is already populated, look for next available entry */ 1099 while (val) { 1100 u8 current_hash = hash++; 1101 u8 next_mask = 0xff; 1102 1103 /* If NEXT field is NULL then update it with next hash */ 1104 if (!(val & next_mask)) { 1105 val |= (u32)hash; 1106 writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 1107 } 1108 1109 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1110 } 1111 1112 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 1113 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 1114 writel(val, bdf_to_sid_base + hash * sizeof(u32)); 1115 } 1116 1117 kfree(map); 1118 1119 return 0; 1120 } 1121 1122 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) 1123 { 1124 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1125 struct dw_pcie *pci = pcie->pci; 1126 struct device *dev = pci->dev; 1127 1128 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 1129 if (res->num_clks < 0) { 1130 dev_err(dev, "Failed to get clocks\n"); 1131 return res->num_clks; 1132 } 1133 1134 res->rst = devm_reset_control_array_get_exclusive(dev); 1135 if (IS_ERR(res->rst)) 1136 return PTR_ERR(res->rst); 1137 1138 return 0; 1139 } 1140 1141 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) 1142 { 1143 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1144 1145 clk_bulk_disable_unprepare(res->num_clks, res->clks); 1146 } 1147 1148 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) 1149 { 1150 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1151 struct device *dev = pcie->pci->dev; 1152 int ret; 1153 1154 ret = reset_control_assert(res->rst); 1155 if (ret) { 1156 dev_err(dev, "reset assert failed (%d)\n", ret); 1157 return ret; 1158 } 1159 1160 /* 1161 * Delay periods before and after reset deassert are working values 1162 * from downstream Codeaurora kernel 1163 */ 1164 usleep_range(2000, 2500); 1165 1166 ret = reset_control_deassert(res->rst); 1167 if (ret) { 1168 dev_err(dev, "reset deassert failed (%d)\n", ret); 1169 return ret; 1170 } 1171 1172 usleep_range(2000, 2500); 1173 1174 return clk_bulk_prepare_enable(res->num_clks, res->clks); 1175 } 1176 1177 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) 1178 { 1179 struct dw_pcie *pci = pcie->pci; 1180 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1181 u32 val; 1182 int i; 1183 1184 val = readl(pcie->parf + PARF_PHY_CTRL); 1185 val &= ~PHY_TEST_PWR_DOWN; 1186 writel(val, pcie->parf + PARF_PHY_CTRL); 1187 1188 qcom_pcie_configure_dbi_atu_base(pcie); 1189 1190 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 1191 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, 1192 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 1193 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | 1194 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 1195 pci->dbi_base + GEN3_RELATED_OFF); 1196 1197 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | 1198 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 1199 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 1200 pcie->parf + PARF_SYS_CTRL); 1201 1202 writel(0, pcie->parf + PARF_Q2A_FLUSH); 1203 1204 dw_pcie_dbi_ro_wr_en(pci); 1205 1206 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 1207 1208 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 1209 val &= ~PCI_EXP_LNKCAP_ASPMS; 1210 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 1211 1212 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 1213 PCI_EXP_DEVCTL2); 1214 1215 dw_pcie_dbi_ro_wr_dis(pci); 1216 1217 for (i = 0; i < 256; i++) 1218 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); 1219 1220 return 0; 1221 } 1222 1223 static int qcom_pcie_link_up(struct dw_pcie *pci) 1224 { 1225 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1226 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1227 1228 return !!(val & PCI_EXP_LNKSTA_DLLLA); 1229 } 1230 1231 static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 1232 { 1233 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1234 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1235 int ret; 1236 1237 qcom_ep_reset_assert(pcie); 1238 1239 ret = pcie->cfg->ops->init(pcie); 1240 if (ret) 1241 return ret; 1242 1243 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1244 if (ret) 1245 goto err_deinit; 1246 1247 ret = phy_power_on(pcie->phy); 1248 if (ret) 1249 goto err_deinit; 1250 1251 if (pcie->cfg->ops->post_init) { 1252 ret = pcie->cfg->ops->post_init(pcie); 1253 if (ret) 1254 goto err_disable_phy; 1255 } 1256 1257 qcom_ep_reset_deassert(pcie); 1258 1259 if (pcie->cfg->ops->config_sid) { 1260 ret = pcie->cfg->ops->config_sid(pcie); 1261 if (ret) 1262 goto err_assert_reset; 1263 } 1264 1265 return 0; 1266 1267 err_assert_reset: 1268 qcom_ep_reset_assert(pcie); 1269 err_disable_phy: 1270 phy_power_off(pcie->phy); 1271 err_deinit: 1272 pcie->cfg->ops->deinit(pcie); 1273 1274 return ret; 1275 } 1276 1277 static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) 1278 { 1279 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1280 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1281 1282 qcom_ep_reset_assert(pcie); 1283 phy_power_off(pcie->phy); 1284 pcie->cfg->ops->deinit(pcie); 1285 } 1286 1287 static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) 1288 { 1289 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1290 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1291 1292 if (pcie->cfg->ops->host_post_init) 1293 pcie->cfg->ops->host_post_init(pcie); 1294 } 1295 1296 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 1297 .init = qcom_pcie_host_init, 1298 .deinit = qcom_pcie_host_deinit, 1299 .post_init = qcom_pcie_host_post_init, 1300 }; 1301 1302 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ 1303 static const struct qcom_pcie_ops ops_2_1_0 = { 1304 .get_resources = qcom_pcie_get_resources_2_1_0, 1305 .init = qcom_pcie_init_2_1_0, 1306 .post_init = qcom_pcie_post_init_2_1_0, 1307 .deinit = qcom_pcie_deinit_2_1_0, 1308 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1309 }; 1310 1311 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ 1312 static const struct qcom_pcie_ops ops_1_0_0 = { 1313 .get_resources = qcom_pcie_get_resources_1_0_0, 1314 .init = qcom_pcie_init_1_0_0, 1315 .post_init = qcom_pcie_post_init_1_0_0, 1316 .deinit = qcom_pcie_deinit_1_0_0, 1317 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1318 }; 1319 1320 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ 1321 static const struct qcom_pcie_ops ops_2_3_2 = { 1322 .get_resources = qcom_pcie_get_resources_2_3_2, 1323 .init = qcom_pcie_init_2_3_2, 1324 .post_init = qcom_pcie_post_init_2_3_2, 1325 .deinit = qcom_pcie_deinit_2_3_2, 1326 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1327 }; 1328 1329 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */ 1330 static const struct qcom_pcie_ops ops_2_4_0 = { 1331 .get_resources = qcom_pcie_get_resources_2_4_0, 1332 .init = qcom_pcie_init_2_4_0, 1333 .post_init = qcom_pcie_post_init_2_3_2, 1334 .deinit = qcom_pcie_deinit_2_4_0, 1335 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1336 }; 1337 1338 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */ 1339 static const struct qcom_pcie_ops ops_2_3_3 = { 1340 .get_resources = qcom_pcie_get_resources_2_3_3, 1341 .init = qcom_pcie_init_2_3_3, 1342 .post_init = qcom_pcie_post_init_2_3_3, 1343 .deinit = qcom_pcie_deinit_2_3_3, 1344 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1345 }; 1346 1347 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ 1348 static const struct qcom_pcie_ops ops_2_7_0 = { 1349 .get_resources = qcom_pcie_get_resources_2_7_0, 1350 .init = qcom_pcie_init_2_7_0, 1351 .post_init = qcom_pcie_post_init_2_7_0, 1352 .deinit = qcom_pcie_deinit_2_7_0, 1353 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1354 }; 1355 1356 /* Qcom IP rev.: 1.9.0 */ 1357 static const struct qcom_pcie_ops ops_1_9_0 = { 1358 .get_resources = qcom_pcie_get_resources_2_7_0, 1359 .init = qcom_pcie_init_2_7_0, 1360 .post_init = qcom_pcie_post_init_2_7_0, 1361 .host_post_init = qcom_pcie_host_post_init_2_7_0, 1362 .deinit = qcom_pcie_deinit_2_7_0, 1363 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1364 .config_sid = qcom_pcie_config_sid_1_9_0, 1365 }; 1366 1367 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ 1368 static const struct qcom_pcie_ops ops_2_9_0 = { 1369 .get_resources = qcom_pcie_get_resources_2_9_0, 1370 .init = qcom_pcie_init_2_9_0, 1371 .post_init = qcom_pcie_post_init_2_9_0, 1372 .deinit = qcom_pcie_deinit_2_9_0, 1373 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1374 }; 1375 1376 static const struct qcom_pcie_cfg cfg_1_0_0 = { 1377 .ops = &ops_1_0_0, 1378 }; 1379 1380 static const struct qcom_pcie_cfg cfg_1_9_0 = { 1381 .ops = &ops_1_9_0, 1382 }; 1383 1384 static const struct qcom_pcie_cfg cfg_1_34_0 = { 1385 .ops = &ops_1_9_0, 1386 .override_no_snoop = true, 1387 }; 1388 1389 static const struct qcom_pcie_cfg cfg_2_1_0 = { 1390 .ops = &ops_2_1_0, 1391 }; 1392 1393 static const struct qcom_pcie_cfg cfg_2_3_2 = { 1394 .ops = &ops_2_3_2, 1395 }; 1396 1397 static const struct qcom_pcie_cfg cfg_2_3_3 = { 1398 .ops = &ops_2_3_3, 1399 }; 1400 1401 static const struct qcom_pcie_cfg cfg_2_4_0 = { 1402 .ops = &ops_2_4_0, 1403 }; 1404 1405 static const struct qcom_pcie_cfg cfg_2_7_0 = { 1406 .ops = &ops_2_7_0, 1407 }; 1408 1409 static const struct qcom_pcie_cfg cfg_2_9_0 = { 1410 .ops = &ops_2_9_0, 1411 }; 1412 1413 static const struct qcom_pcie_cfg cfg_sc8280xp = { 1414 .ops = &ops_1_9_0, 1415 .no_l0s = true, 1416 }; 1417 1418 static const struct dw_pcie_ops dw_pcie_ops = { 1419 .link_up = qcom_pcie_link_up, 1420 .start_link = qcom_pcie_start_link, 1421 }; 1422 1423 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) 1424 { 1425 struct dw_pcie *pci = pcie->pci; 1426 int ret; 1427 1428 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); 1429 if (IS_ERR(pcie->icc_mem)) 1430 return PTR_ERR(pcie->icc_mem); 1431 1432 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); 1433 if (IS_ERR(pcie->icc_cpu)) 1434 return PTR_ERR(pcie->icc_cpu); 1435 /* 1436 * Some Qualcomm platforms require interconnect bandwidth constraints 1437 * to be set before enabling interconnect clocks. 1438 * 1439 * Set an initial peak bandwidth corresponding to single-lane Gen 1 1440 * for the pcie-mem path. 1441 */ 1442 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 1443 if (ret) { 1444 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1445 ret); 1446 return ret; 1447 } 1448 1449 /* 1450 * Since the CPU-PCIe path is only used for activities like register 1451 * access of the host controller and endpoint Config/BAR space access, 1452 * HW team has recommended to use a minimal bandwidth of 1KBps just to 1453 * keep the path active. 1454 */ 1455 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); 1456 if (ret) { 1457 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", 1458 ret); 1459 icc_set_bw(pcie->icc_mem, 0, 0); 1460 return ret; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) 1467 { 1468 u32 offset, status, width, speed; 1469 struct dw_pcie *pci = pcie->pci; 1470 unsigned long freq_kbps; 1471 struct dev_pm_opp *opp; 1472 int ret, freq_mbps; 1473 1474 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1475 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1476 1477 /* Only update constraints if link is up. */ 1478 if (!(status & PCI_EXP_LNKSTA_DLLLA)) 1479 return; 1480 1481 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 1482 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 1483 1484 if (pcie->icc_mem) { 1485 ret = icc_set_bw(pcie->icc_mem, 0, 1486 width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 1487 if (ret) { 1488 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1489 ret); 1490 } 1491 } else if (pcie->use_pm_opp) { 1492 freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]); 1493 if (freq_mbps < 0) 1494 return; 1495 1496 freq_kbps = freq_mbps * KILO; 1497 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, 1498 true); 1499 if (!IS_ERR(opp)) { 1500 ret = dev_pm_opp_set_opp(pci->dev, opp); 1501 if (ret) 1502 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", 1503 freq_kbps * width, ret); 1504 dev_pm_opp_put(opp); 1505 } 1506 } 1507 } 1508 1509 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) 1510 { 1511 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); 1512 1513 seq_printf(s, "L0s transition count: %u\n", 1514 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 1515 1516 seq_printf(s, "L1 transition count: %u\n", 1517 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 1518 1519 seq_printf(s, "L1.1 transition count: %u\n", 1520 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 1521 1522 seq_printf(s, "L1.2 transition count: %u\n", 1523 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 1524 1525 seq_printf(s, "L2 transition count: %u\n", 1526 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 1527 1528 return 0; 1529 } 1530 1531 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) 1532 { 1533 struct dw_pcie *pci = pcie->pci; 1534 struct device *dev = pci->dev; 1535 char *name; 1536 1537 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1538 if (!name) 1539 return; 1540 1541 pcie->debugfs = debugfs_create_dir(name, NULL); 1542 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, 1543 qcom_pcie_link_transition_count); 1544 } 1545 1546 static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) 1547 { 1548 struct qcom_pcie *pcie = data; 1549 struct dw_pcie_rp *pp = &pcie->pci->pp; 1550 struct device *dev = pcie->pci->dev; 1551 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); 1552 1553 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); 1554 1555 if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 1556 dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); 1557 /* Rescan the bus to enumerate endpoint devices */ 1558 pci_lock_rescan_remove(); 1559 pci_rescan_bus(pp->bridge->bus); 1560 pci_unlock_rescan_remove(); 1561 } else { 1562 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", 1563 status); 1564 } 1565 1566 return IRQ_HANDLED; 1567 } 1568 1569 static int qcom_pcie_probe(struct platform_device *pdev) 1570 { 1571 const struct qcom_pcie_cfg *pcie_cfg; 1572 unsigned long max_freq = ULONG_MAX; 1573 struct device *dev = &pdev->dev; 1574 struct dev_pm_opp *opp; 1575 struct qcom_pcie *pcie; 1576 struct dw_pcie_rp *pp; 1577 struct resource *res; 1578 struct dw_pcie *pci; 1579 int ret, irq; 1580 char *name; 1581 1582 pcie_cfg = of_device_get_match_data(dev); 1583 if (!pcie_cfg || !pcie_cfg->ops) { 1584 dev_err(dev, "Invalid platform data\n"); 1585 return -EINVAL; 1586 } 1587 1588 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1589 if (!pcie) 1590 return -ENOMEM; 1591 1592 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1593 if (!pci) 1594 return -ENOMEM; 1595 1596 pm_runtime_enable(dev); 1597 ret = pm_runtime_get_sync(dev); 1598 if (ret < 0) 1599 goto err_pm_runtime_put; 1600 1601 pci->dev = dev; 1602 pci->ops = &dw_pcie_ops; 1603 pp = &pci->pp; 1604 1605 pcie->pci = pci; 1606 1607 pcie->cfg = pcie_cfg; 1608 1609 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 1610 if (IS_ERR(pcie->reset)) { 1611 ret = PTR_ERR(pcie->reset); 1612 goto err_pm_runtime_put; 1613 } 1614 1615 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 1616 if (IS_ERR(pcie->parf)) { 1617 ret = PTR_ERR(pcie->parf); 1618 goto err_pm_runtime_put; 1619 } 1620 1621 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 1622 if (IS_ERR(pcie->elbi)) { 1623 ret = PTR_ERR(pcie->elbi); 1624 goto err_pm_runtime_put; 1625 } 1626 1627 /* MHI region is optional */ 1628 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi"); 1629 if (res) { 1630 pcie->mhi = devm_ioremap_resource(dev, res); 1631 if (IS_ERR(pcie->mhi)) { 1632 ret = PTR_ERR(pcie->mhi); 1633 goto err_pm_runtime_put; 1634 } 1635 } 1636 1637 pcie->phy = devm_phy_optional_get(dev, "pciephy"); 1638 if (IS_ERR(pcie->phy)) { 1639 ret = PTR_ERR(pcie->phy); 1640 goto err_pm_runtime_put; 1641 } 1642 1643 /* OPP table is optional */ 1644 ret = devm_pm_opp_of_add_table(dev); 1645 if (ret && ret != -ENODEV) { 1646 dev_err_probe(dev, ret, "Failed to add OPP table\n"); 1647 goto err_pm_runtime_put; 1648 } 1649 1650 /* 1651 * Before the PCIe link is initialized, vote for highest OPP in the OPP 1652 * table, so that we are voting for maximum voltage corner for the 1653 * link to come up in maximum supported speed. At the end of the 1654 * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). 1655 */ 1656 if (!ret) { 1657 opp = dev_pm_opp_find_freq_floor(dev, &max_freq); 1658 if (IS_ERR(opp)) { 1659 ret = PTR_ERR(opp); 1660 dev_err_probe(pci->dev, ret, 1661 "Unable to find max freq OPP\n"); 1662 goto err_pm_runtime_put; 1663 } else { 1664 ret = dev_pm_opp_set_opp(dev, opp); 1665 } 1666 1667 dev_pm_opp_put(opp); 1668 if (ret) { 1669 dev_err_probe(pci->dev, ret, 1670 "Failed to set OPP for freq %lu\n", 1671 max_freq); 1672 goto err_pm_runtime_put; 1673 } 1674 1675 pcie->use_pm_opp = true; 1676 } else { 1677 /* Skip ICC init if OPP is supported as it is handled by OPP */ 1678 ret = qcom_pcie_icc_init(pcie); 1679 if (ret) 1680 goto err_pm_runtime_put; 1681 } 1682 1683 ret = pcie->cfg->ops->get_resources(pcie); 1684 if (ret) 1685 goto err_pm_runtime_put; 1686 1687 pp->ops = &qcom_pcie_dw_ops; 1688 1689 ret = phy_init(pcie->phy); 1690 if (ret) 1691 goto err_pm_runtime_put; 1692 1693 platform_set_drvdata(pdev, pcie); 1694 1695 ret = dw_pcie_host_init(pp); 1696 if (ret) { 1697 dev_err(dev, "cannot initialize host\n"); 1698 goto err_phy_exit; 1699 } 1700 1701 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", 1702 pci_domain_nr(pp->bridge->bus)); 1703 if (!name) { 1704 ret = -ENOMEM; 1705 goto err_host_deinit; 1706 } 1707 1708 irq = platform_get_irq_byname_optional(pdev, "global"); 1709 if (irq > 0) { 1710 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1711 qcom_pcie_global_irq_thread, 1712 IRQF_ONESHOT, name, pcie); 1713 if (ret) { 1714 dev_err_probe(&pdev->dev, ret, 1715 "Failed to request Global IRQ\n"); 1716 goto err_host_deinit; 1717 } 1718 1719 writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); 1720 } 1721 1722 qcom_pcie_icc_opp_update(pcie); 1723 1724 if (pcie->mhi) 1725 qcom_pcie_init_debugfs(pcie); 1726 1727 return 0; 1728 1729 err_host_deinit: 1730 dw_pcie_host_deinit(pp); 1731 err_phy_exit: 1732 phy_exit(pcie->phy); 1733 err_pm_runtime_put: 1734 pm_runtime_put(dev); 1735 pm_runtime_disable(dev); 1736 1737 return ret; 1738 } 1739 1740 static int qcom_pcie_suspend_noirq(struct device *dev) 1741 { 1742 struct qcom_pcie *pcie = dev_get_drvdata(dev); 1743 int ret = 0; 1744 1745 /* 1746 * Set minimum bandwidth required to keep data path functional during 1747 * suspend. 1748 */ 1749 if (pcie->icc_mem) { 1750 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); 1751 if (ret) { 1752 dev_err(dev, 1753 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1754 ret); 1755 return ret; 1756 } 1757 } 1758 1759 /* 1760 * Turn OFF the resources only for controllers without active PCIe 1761 * devices. For controllers with active devices, the resources are kept 1762 * ON and the link is expected to be in L0/L1 (sub)states. 1763 * 1764 * Turning OFF the resources for controllers with active PCIe devices 1765 * will trigger access violation during the end of the suspend cycle, 1766 * as kernel tries to access the PCIe devices config space for masking 1767 * MSIs. 1768 * 1769 * Also, it is not desirable to put the link into L2/L3 state as that 1770 * implies VDD supply will be removed and the devices may go into 1771 * powerdown state. This will affect the lifetime of the storage devices 1772 * like NVMe. 1773 */ 1774 if (!dw_pcie_link_up(pcie->pci)) { 1775 qcom_pcie_host_deinit(&pcie->pci->pp); 1776 pcie->suspended = true; 1777 } 1778 1779 /* 1780 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. 1781 * Because on some platforms, DBI access can happen very late during the 1782 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC 1783 * error. 1784 */ 1785 if (pm_suspend_target_state != PM_SUSPEND_MEM) { 1786 ret = icc_disable(pcie->icc_cpu); 1787 if (ret) 1788 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); 1789 1790 if (pcie->use_pm_opp) 1791 dev_pm_opp_set_opp(pcie->pci->dev, NULL); 1792 } 1793 return ret; 1794 } 1795 1796 static int qcom_pcie_resume_noirq(struct device *dev) 1797 { 1798 struct qcom_pcie *pcie = dev_get_drvdata(dev); 1799 int ret; 1800 1801 if (pm_suspend_target_state != PM_SUSPEND_MEM) { 1802 ret = icc_enable(pcie->icc_cpu); 1803 if (ret) { 1804 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); 1805 return ret; 1806 } 1807 } 1808 1809 if (pcie->suspended) { 1810 ret = qcom_pcie_host_init(&pcie->pci->pp); 1811 if (ret) 1812 return ret; 1813 1814 pcie->suspended = false; 1815 } 1816 1817 qcom_pcie_icc_opp_update(pcie); 1818 1819 return 0; 1820 } 1821 1822 static const struct of_device_id qcom_pcie_match[] = { 1823 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, 1824 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, 1825 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, 1826 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, 1827 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, 1828 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, 1829 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, 1830 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, 1831 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, 1832 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, 1833 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, 1834 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0}, 1835 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, 1836 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, 1837 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp }, 1838 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, 1839 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, 1840 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, 1841 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, 1842 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, 1843 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, 1844 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, 1845 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, 1846 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, 1847 { } 1848 }; 1849 1850 static void qcom_fixup_class(struct pci_dev *dev) 1851 { 1852 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 1853 } 1854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); 1855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); 1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); 1857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); 1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); 1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); 1860 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); 1861 1862 static const struct dev_pm_ops qcom_pcie_pm_ops = { 1863 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq) 1864 }; 1865 1866 static struct platform_driver qcom_pcie_driver = { 1867 .probe = qcom_pcie_probe, 1868 .driver = { 1869 .name = "qcom-pcie", 1870 .suppress_bind_attrs = true, 1871 .of_match_table = qcom_pcie_match, 1872 .pm = &qcom_pcie_pm_ops, 1873 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1874 }, 1875 }; 1876 builtin_platform_driver(qcom_pcie_driver); 1877