1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe root complex driver 4 * 5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 * Copyright 2015 Linaro Limited. 7 * 8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/crc8.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pci.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/platform_device.h> 27 #include <linux/phy/pcie.h> 28 #include <linux/phy/phy.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 #include <linux/types.h> 33 34 #include "../../pci.h" 35 #include "pcie-designware.h" 36 37 /* PARF registers */ 38 #define PARF_SYS_CTRL 0x00 39 #define PARF_PM_CTRL 0x20 40 #define PARF_PCS_DEEMPH 0x34 41 #define PARF_PCS_SWING 0x38 42 #define PARF_PHY_CTRL 0x40 43 #define PARF_PHY_REFCLK 0x4c 44 #define PARF_CONFIG_BITS 0x50 45 #define PARF_DBI_BASE_ADDR 0x168 46 #define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ 47 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 48 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 49 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 50 #define PARF_Q2A_FLUSH 0x1ac 51 #define PARF_LTSSM 0x1b0 52 #define PARF_SID_OFFSET 0x234 53 #define PARF_BDF_TRANSLATE_CFG 0x24c 54 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 55 #define PARF_DEVICE_TYPE 0x1000 56 #define PARF_BDF_TO_SID_TABLE_N 0x2000 57 58 /* ELBI registers */ 59 #define ELBI_SYS_CTRL 0x04 60 61 /* DBI registers */ 62 #define AXI_MSTR_RESP_COMP_CTRL0 0x818 63 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c 64 #define MISC_CONTROL_1_REG 0x8bc 65 66 /* MHI registers */ 67 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 68 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 69 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 70 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 71 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 72 73 /* PARF_SYS_CTRL register fields */ 74 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 75 #define MST_WAKEUP_EN BIT(13) 76 #define SLV_WAKEUP_EN BIT(12) 77 #define MSTR_ACLK_CGC_DIS BIT(10) 78 #define SLV_ACLK_CGC_DIS BIT(9) 79 #define CORE_CLK_CGC_DIS BIT(6) 80 #define AUX_PWR_DET BIT(4) 81 #define L23_CLK_RMV_DIS BIT(2) 82 #define L1_CLK_RMV_DIS BIT(1) 83 84 /* PARF_PM_CTRL register fields */ 85 #define REQ_NOT_ENTR_L1 BIT(5) 86 87 /* PARF_PCS_DEEMPH register fields */ 88 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) 89 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) 90 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) 91 92 /* PARF_PCS_SWING register fields */ 93 #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) 94 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) 95 96 /* PARF_PHY_CTRL register fields */ 97 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) 98 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) 99 #define PHY_TEST_PWR_DOWN BIT(0) 100 101 /* PARF_PHY_REFCLK register fields */ 102 #define PHY_REFCLK_SSP_EN BIT(16) 103 #define PHY_REFCLK_USE_PAD BIT(12) 104 105 /* PARF_CONFIG_BITS register fields */ 106 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) 107 108 /* PARF_SLV_ADDR_SPACE_SIZE register value */ 109 #define SLV_ADDR_SPACE_SZ 0x10000000 110 111 /* PARF_MHI_CLOCK_RESET_CTRL register fields */ 112 #define AHB_CLK_EN BIT(0) 113 #define MSTR_AXI_CLK_EN BIT(1) 114 #define BYPASS BIT(4) 115 116 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 117 #define EN BIT(31) 118 119 /* PARF_LTSSM register fields */ 120 #define LTSSM_EN BIT(8) 121 122 /* PARF_DEVICE_TYPE register fields */ 123 #define DEVICE_TYPE_RC 0x4 124 125 /* ELBI_SYS_CTRL register fields */ 126 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) 127 128 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ 129 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 130 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 131 132 /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ 133 #define CFG_BRIDGE_SB_INIT BIT(0) 134 135 /* MISC_CONTROL_1_REG register fields */ 136 #define DBI_RO_WR_EN 1 137 138 /* PCI_EXP_SLTCAP register fields */ 139 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) 140 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) 141 #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ 142 PCI_EXP_SLTCAP_PCP | \ 143 PCI_EXP_SLTCAP_MRLSP | \ 144 PCI_EXP_SLTCAP_AIP | \ 145 PCI_EXP_SLTCAP_PIP | \ 146 PCI_EXP_SLTCAP_HPS | \ 147 PCI_EXP_SLTCAP_HPC | \ 148 PCI_EXP_SLTCAP_EIP | \ 149 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ 150 PCIE_CAP_SLOT_POWER_LIMIT_SCALE) 151 152 #define PERST_DELAY_US 1000 153 154 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 155 156 #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 157 struct qcom_pcie_resources_1_0_0 { 158 struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; 159 struct reset_control *core; 160 struct regulator *vdda; 161 }; 162 163 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 164 #define QCOM_PCIE_2_1_0_MAX_RESETS 6 165 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 166 struct qcom_pcie_resources_2_1_0 { 167 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; 168 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; 169 int num_resets; 170 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; 171 }; 172 173 #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 174 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 175 struct qcom_pcie_resources_2_3_2 { 176 struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; 177 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; 178 }; 179 180 #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 181 #define QCOM_PCIE_2_3_3_MAX_RESETS 7 182 struct qcom_pcie_resources_2_3_3 { 183 struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; 184 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; 185 }; 186 187 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 188 #define QCOM_PCIE_2_4_0_MAX_RESETS 12 189 struct qcom_pcie_resources_2_4_0 { 190 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; 191 int num_clks; 192 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; 193 int num_resets; 194 }; 195 196 #define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 197 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 198 struct qcom_pcie_resources_2_7_0 { 199 struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; 200 int num_clks; 201 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; 202 struct reset_control *rst; 203 }; 204 205 #define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 206 struct qcom_pcie_resources_2_9_0 { 207 struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; 208 struct reset_control *rst; 209 }; 210 211 union qcom_pcie_resources { 212 struct qcom_pcie_resources_1_0_0 v1_0_0; 213 struct qcom_pcie_resources_2_1_0 v2_1_0; 214 struct qcom_pcie_resources_2_3_2 v2_3_2; 215 struct qcom_pcie_resources_2_3_3 v2_3_3; 216 struct qcom_pcie_resources_2_4_0 v2_4_0; 217 struct qcom_pcie_resources_2_7_0 v2_7_0; 218 struct qcom_pcie_resources_2_9_0 v2_9_0; 219 }; 220 221 struct qcom_pcie; 222 223 struct qcom_pcie_ops { 224 int (*get_resources)(struct qcom_pcie *pcie); 225 int (*init)(struct qcom_pcie *pcie); 226 int (*post_init)(struct qcom_pcie *pcie); 227 void (*deinit)(struct qcom_pcie *pcie); 228 void (*ltssm_enable)(struct qcom_pcie *pcie); 229 int (*config_sid)(struct qcom_pcie *pcie); 230 }; 231 232 struct qcom_pcie_cfg { 233 const struct qcom_pcie_ops *ops; 234 }; 235 236 struct qcom_pcie { 237 struct dw_pcie *pci; 238 void __iomem *parf; /* DT parf */ 239 void __iomem *elbi; /* DT elbi */ 240 void __iomem *mhi; 241 union qcom_pcie_resources res; 242 struct phy *phy; 243 struct gpio_desc *reset; 244 struct icc_path *icc_mem; 245 const struct qcom_pcie_cfg *cfg; 246 struct dentry *debugfs; 247 bool suspended; 248 }; 249 250 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) 251 252 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 253 { 254 gpiod_set_value_cansleep(pcie->reset, 1); 255 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 256 } 257 258 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) 259 { 260 /* Ensure that PERST has been asserted for at least 100 ms */ 261 msleep(100); 262 gpiod_set_value_cansleep(pcie->reset, 0); 263 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 264 } 265 266 static int qcom_pcie_start_link(struct dw_pcie *pci) 267 { 268 struct qcom_pcie *pcie = to_qcom_pcie(pci); 269 270 /* Enable Link Training state machine */ 271 if (pcie->cfg->ops->ltssm_enable) 272 pcie->cfg->ops->ltssm_enable(pcie); 273 274 return 0; 275 } 276 277 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 278 { 279 u32 val; 280 281 /* enable link training */ 282 val = readl(pcie->elbi + ELBI_SYS_CTRL); 283 val |= ELBI_SYS_CTRL_LT_ENABLE; 284 writel(val, pcie->elbi + ELBI_SYS_CTRL); 285 } 286 287 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 288 { 289 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 290 struct dw_pcie *pci = pcie->pci; 291 struct device *dev = pci->dev; 292 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); 293 int ret; 294 295 res->supplies[0].supply = "vdda"; 296 res->supplies[1].supply = "vdda_phy"; 297 res->supplies[2].supply = "vdda_refclk"; 298 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 299 res->supplies); 300 if (ret) 301 return ret; 302 303 res->clks[0].id = "iface"; 304 res->clks[1].id = "core"; 305 res->clks[2].id = "phy"; 306 res->clks[3].id = "aux"; 307 res->clks[4].id = "ref"; 308 309 /* iface, core, phy are required */ 310 ret = devm_clk_bulk_get(dev, 3, res->clks); 311 if (ret < 0) 312 return ret; 313 314 /* aux, ref are optional */ 315 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); 316 if (ret < 0) 317 return ret; 318 319 res->resets[0].id = "pci"; 320 res->resets[1].id = "axi"; 321 res->resets[2].id = "ahb"; 322 res->resets[3].id = "por"; 323 res->resets[4].id = "phy"; 324 res->resets[5].id = "ext"; 325 326 /* ext is optional on APQ8016 */ 327 res->num_resets = is_apq ? 5 : 6; 328 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 329 if (ret < 0) 330 return ret; 331 332 return 0; 333 } 334 335 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 336 { 337 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 338 339 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 340 reset_control_bulk_assert(res->num_resets, res->resets); 341 342 writel(1, pcie->parf + PARF_PHY_CTRL); 343 344 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 345 } 346 347 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 348 { 349 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 350 struct dw_pcie *pci = pcie->pci; 351 struct device *dev = pci->dev; 352 int ret; 353 354 /* reset the PCIe interface as uboot can leave it undefined state */ 355 ret = reset_control_bulk_assert(res->num_resets, res->resets); 356 if (ret < 0) { 357 dev_err(dev, "cannot assert resets\n"); 358 return ret; 359 } 360 361 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 362 if (ret < 0) { 363 dev_err(dev, "cannot enable regulators\n"); 364 return ret; 365 } 366 367 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 368 if (ret < 0) { 369 dev_err(dev, "cannot deassert resets\n"); 370 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 371 return ret; 372 } 373 374 return 0; 375 } 376 377 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) 378 { 379 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 380 struct dw_pcie *pci = pcie->pci; 381 struct device *dev = pci->dev; 382 struct device_node *node = dev->of_node; 383 u32 val; 384 int ret; 385 386 /* enable PCIe clocks and resets */ 387 val = readl(pcie->parf + PARF_PHY_CTRL); 388 val &= ~PHY_TEST_PWR_DOWN; 389 writel(val, pcie->parf + PARF_PHY_CTRL); 390 391 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 392 if (ret) 393 return ret; 394 395 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || 396 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { 397 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | 398 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | 399 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), 400 pcie->parf + PARF_PCS_DEEMPH); 401 writel(PCS_SWING_TX_SWING_FULL(120) | 402 PCS_SWING_TX_SWING_LOW(120), 403 pcie->parf + PARF_PCS_SWING); 404 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); 405 } 406 407 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { 408 /* set TX termination offset */ 409 val = readl(pcie->parf + PARF_PHY_CTRL); 410 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; 411 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); 412 writel(val, pcie->parf + PARF_PHY_CTRL); 413 } 414 415 /* enable external reference clock */ 416 val = readl(pcie->parf + PARF_PHY_REFCLK); 417 /* USE_PAD is required only for ipq806x */ 418 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) 419 val &= ~PHY_REFCLK_USE_PAD; 420 val |= PHY_REFCLK_SSP_EN; 421 writel(val, pcie->parf + PARF_PHY_REFCLK); 422 423 /* wait for clock acquisition */ 424 usleep_range(1000, 1500); 425 426 /* Set the Max TLP size to 2K, instead of using default of 4K */ 427 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, 428 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); 429 writel(CFG_BRIDGE_SB_INIT, 430 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); 431 432 return 0; 433 } 434 435 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) 436 { 437 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 438 struct dw_pcie *pci = pcie->pci; 439 struct device *dev = pci->dev; 440 int ret; 441 442 res->vdda = devm_regulator_get(dev, "vdda"); 443 if (IS_ERR(res->vdda)) 444 return PTR_ERR(res->vdda); 445 446 res->clks[0].id = "iface"; 447 res->clks[1].id = "aux"; 448 res->clks[2].id = "master_bus"; 449 res->clks[3].id = "slave_bus"; 450 451 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 452 if (ret < 0) 453 return ret; 454 455 res->core = devm_reset_control_get_exclusive(dev, "core"); 456 return PTR_ERR_OR_ZERO(res->core); 457 } 458 459 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) 460 { 461 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 462 463 reset_control_assert(res->core); 464 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 465 regulator_disable(res->vdda); 466 } 467 468 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) 469 { 470 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 471 struct dw_pcie *pci = pcie->pci; 472 struct device *dev = pci->dev; 473 int ret; 474 475 ret = reset_control_deassert(res->core); 476 if (ret) { 477 dev_err(dev, "cannot deassert core reset\n"); 478 return ret; 479 } 480 481 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 482 if (ret) { 483 dev_err(dev, "cannot prepare/enable clocks\n"); 484 goto err_assert_reset; 485 } 486 487 ret = regulator_enable(res->vdda); 488 if (ret) { 489 dev_err(dev, "cannot enable vdda regulator\n"); 490 goto err_disable_clks; 491 } 492 493 return 0; 494 495 err_disable_clks: 496 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 497 err_assert_reset: 498 reset_control_assert(res->core); 499 500 return ret; 501 } 502 503 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 504 { 505 /* change DBI base address */ 506 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 507 508 if (IS_ENABLED(CONFIG_PCI_MSI)) { 509 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 510 511 val |= EN; 512 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 513 } 514 515 return 0; 516 } 517 518 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) 519 { 520 u32 val; 521 522 /* enable link training */ 523 val = readl(pcie->parf + PARF_LTSSM); 524 val |= LTSSM_EN; 525 writel(val, pcie->parf + PARF_LTSSM); 526 } 527 528 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 529 { 530 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 531 struct dw_pcie *pci = pcie->pci; 532 struct device *dev = pci->dev; 533 int ret; 534 535 res->supplies[0].supply = "vdda"; 536 res->supplies[1].supply = "vddpe-3v3"; 537 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 538 res->supplies); 539 if (ret) 540 return ret; 541 542 res->clks[0].id = "aux"; 543 res->clks[1].id = "cfg"; 544 res->clks[2].id = "bus_master"; 545 res->clks[3].id = "bus_slave"; 546 547 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 548 if (ret < 0) 549 return ret; 550 551 return 0; 552 } 553 554 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 555 { 556 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 557 558 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 559 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 560 } 561 562 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 563 { 564 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 565 struct dw_pcie *pci = pcie->pci; 566 struct device *dev = pci->dev; 567 int ret; 568 569 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 570 if (ret < 0) { 571 dev_err(dev, "cannot enable regulators\n"); 572 return ret; 573 } 574 575 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 576 if (ret) { 577 dev_err(dev, "cannot prepare/enable clocks\n"); 578 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 579 return ret; 580 } 581 582 return 0; 583 } 584 585 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 586 { 587 u32 val; 588 589 /* enable PCIe clocks and resets */ 590 val = readl(pcie->parf + PARF_PHY_CTRL); 591 val &= ~PHY_TEST_PWR_DOWN; 592 writel(val, pcie->parf + PARF_PHY_CTRL); 593 594 /* change DBI base address */ 595 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 596 597 /* MAC PHY_POWERDOWN MUX DISABLE */ 598 val = readl(pcie->parf + PARF_SYS_CTRL); 599 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 600 writel(val, pcie->parf + PARF_SYS_CTRL); 601 602 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 603 val |= BYPASS; 604 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 605 606 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 607 val |= EN; 608 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 609 610 return 0; 611 } 612 613 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) 614 { 615 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 616 struct dw_pcie *pci = pcie->pci; 617 struct device *dev = pci->dev; 618 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); 619 int ret; 620 621 res->clks[0].id = "aux"; 622 res->clks[1].id = "master_bus"; 623 res->clks[2].id = "slave_bus"; 624 res->clks[3].id = "iface"; 625 626 /* qcom,pcie-ipq4019 is defined without "iface" */ 627 res->num_clks = is_ipq ? 3 : 4; 628 629 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); 630 if (ret < 0) 631 return ret; 632 633 res->resets[0].id = "axi_m"; 634 res->resets[1].id = "axi_s"; 635 res->resets[2].id = "axi_m_sticky"; 636 res->resets[3].id = "pipe_sticky"; 637 res->resets[4].id = "pwr"; 638 res->resets[5].id = "ahb"; 639 res->resets[6].id = "pipe"; 640 res->resets[7].id = "axi_m_vmid"; 641 res->resets[8].id = "axi_s_xpu"; 642 res->resets[9].id = "parf"; 643 res->resets[10].id = "phy"; 644 res->resets[11].id = "phy_ahb"; 645 646 res->num_resets = is_ipq ? 12 : 6; 647 648 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 649 if (ret < 0) 650 return ret; 651 652 return 0; 653 } 654 655 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) 656 { 657 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 658 659 reset_control_bulk_assert(res->num_resets, res->resets); 660 clk_bulk_disable_unprepare(res->num_clks, res->clks); 661 } 662 663 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 664 { 665 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 666 struct dw_pcie *pci = pcie->pci; 667 struct device *dev = pci->dev; 668 int ret; 669 670 ret = reset_control_bulk_assert(res->num_resets, res->resets); 671 if (ret < 0) { 672 dev_err(dev, "cannot assert resets\n"); 673 return ret; 674 } 675 676 usleep_range(10000, 12000); 677 678 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 679 if (ret < 0) { 680 dev_err(dev, "cannot deassert resets\n"); 681 return ret; 682 } 683 684 usleep_range(10000, 12000); 685 686 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 687 if (ret) { 688 reset_control_bulk_assert(res->num_resets, res->resets); 689 return ret; 690 } 691 692 return 0; 693 } 694 695 static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) 696 { 697 u32 val; 698 699 /* enable PCIe clocks and resets */ 700 val = readl(pcie->parf + PARF_PHY_CTRL); 701 val &= ~PHY_TEST_PWR_DOWN; 702 writel(val, pcie->parf + PARF_PHY_CTRL); 703 704 /* change DBI base address */ 705 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 706 707 /* MAC PHY_POWERDOWN MUX DISABLE */ 708 val = readl(pcie->parf + PARF_SYS_CTRL); 709 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 710 writel(val, pcie->parf + PARF_SYS_CTRL); 711 712 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 713 val |= BYPASS; 714 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 715 716 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 717 val |= EN; 718 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 719 720 return 0; 721 } 722 723 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) 724 { 725 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 726 struct dw_pcie *pci = pcie->pci; 727 struct device *dev = pci->dev; 728 int ret; 729 730 res->clks[0].id = "iface"; 731 res->clks[1].id = "axi_m"; 732 res->clks[2].id = "axi_s"; 733 res->clks[3].id = "ahb"; 734 res->clks[4].id = "aux"; 735 736 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 737 if (ret < 0) 738 return ret; 739 740 res->rst[0].id = "axi_m"; 741 res->rst[1].id = "axi_s"; 742 res->rst[2].id = "pipe"; 743 res->rst[3].id = "axi_m_sticky"; 744 res->rst[4].id = "sticky"; 745 res->rst[5].id = "ahb"; 746 res->rst[6].id = "sleep"; 747 748 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); 749 if (ret < 0) 750 return ret; 751 752 return 0; 753 } 754 755 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) 756 { 757 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 758 759 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 760 } 761 762 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) 763 { 764 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 765 struct dw_pcie *pci = pcie->pci; 766 struct device *dev = pci->dev; 767 int ret; 768 769 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 770 if (ret < 0) { 771 dev_err(dev, "cannot assert resets\n"); 772 return ret; 773 } 774 775 usleep_range(2000, 2500); 776 777 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); 778 if (ret < 0) { 779 dev_err(dev, "cannot deassert resets\n"); 780 return ret; 781 } 782 783 /* 784 * Don't have a way to see if the reset has completed. 785 * Wait for some time. 786 */ 787 usleep_range(2000, 2500); 788 789 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 790 if (ret) { 791 dev_err(dev, "cannot prepare/enable clocks\n"); 792 goto err_assert_resets; 793 } 794 795 return 0; 796 797 err_assert_resets: 798 /* 799 * Not checking for failure, will anyway return 800 * the original failure in 'ret'. 801 */ 802 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 803 804 return ret; 805 } 806 807 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 808 { 809 struct dw_pcie *pci = pcie->pci; 810 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 811 u32 val; 812 813 writel(SLV_ADDR_SPACE_SZ, 814 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); 815 816 val = readl(pcie->parf + PARF_PHY_CTRL); 817 val &= ~PHY_TEST_PWR_DOWN; 818 writel(val, pcie->parf + PARF_PHY_CTRL); 819 820 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 821 822 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 823 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 824 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 825 pcie->parf + PARF_SYS_CTRL); 826 writel(0, pcie->parf + PARF_Q2A_FLUSH); 827 828 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); 829 writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); 830 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 831 832 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 833 val &= ~PCI_EXP_LNKCAP_ASPMS; 834 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 835 836 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 837 PCI_EXP_DEVCTL2); 838 839 return 0; 840 } 841 842 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 843 { 844 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 845 struct dw_pcie *pci = pcie->pci; 846 struct device *dev = pci->dev; 847 unsigned int num_clks, num_opt_clks; 848 unsigned int idx; 849 int ret; 850 851 res->rst = devm_reset_control_array_get_exclusive(dev); 852 if (IS_ERR(res->rst)) 853 return PTR_ERR(res->rst); 854 855 res->supplies[0].supply = "vdda"; 856 res->supplies[1].supply = "vddpe-3v3"; 857 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 858 res->supplies); 859 if (ret) 860 return ret; 861 862 idx = 0; 863 res->clks[idx++].id = "aux"; 864 res->clks[idx++].id = "cfg"; 865 res->clks[idx++].id = "bus_master"; 866 res->clks[idx++].id = "bus_slave"; 867 res->clks[idx++].id = "slave_q2a"; 868 869 num_clks = idx; 870 871 ret = devm_clk_bulk_get(dev, num_clks, res->clks); 872 if (ret < 0) 873 return ret; 874 875 res->clks[idx++].id = "tbu"; 876 res->clks[idx++].id = "ddrss_sf_tbu"; 877 res->clks[idx++].id = "aggre0"; 878 res->clks[idx++].id = "aggre1"; 879 res->clks[idx++].id = "noc_aggr"; 880 res->clks[idx++].id = "noc_aggr_4"; 881 res->clks[idx++].id = "noc_aggr_south_sf"; 882 res->clks[idx++].id = "cnoc_qx"; 883 res->clks[idx++].id = "sleep"; 884 res->clks[idx++].id = "cnoc_sf_axi"; 885 886 num_opt_clks = idx - num_clks; 887 res->num_clks = idx; 888 889 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); 890 if (ret < 0) 891 return ret; 892 893 return 0; 894 } 895 896 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 897 { 898 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 899 struct dw_pcie *pci = pcie->pci; 900 struct device *dev = pci->dev; 901 u32 val; 902 int ret; 903 904 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 905 if (ret < 0) { 906 dev_err(dev, "cannot enable regulators\n"); 907 return ret; 908 } 909 910 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 911 if (ret < 0) 912 goto err_disable_regulators; 913 914 ret = reset_control_assert(res->rst); 915 if (ret) { 916 dev_err(dev, "reset assert failed (%d)\n", ret); 917 goto err_disable_clocks; 918 } 919 920 usleep_range(1000, 1500); 921 922 ret = reset_control_deassert(res->rst); 923 if (ret) { 924 dev_err(dev, "reset deassert failed (%d)\n", ret); 925 goto err_disable_clocks; 926 } 927 928 /* Wait for reset to complete, required on SM8450 */ 929 usleep_range(1000, 1500); 930 931 /* configure PCIe to RC mode */ 932 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 933 934 /* enable PCIe clocks and resets */ 935 val = readl(pcie->parf + PARF_PHY_CTRL); 936 val &= ~PHY_TEST_PWR_DOWN; 937 writel(val, pcie->parf + PARF_PHY_CTRL); 938 939 /* change DBI base address */ 940 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 941 942 /* MAC PHY_POWERDOWN MUX DISABLE */ 943 val = readl(pcie->parf + PARF_SYS_CTRL); 944 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 945 writel(val, pcie->parf + PARF_SYS_CTRL); 946 947 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 948 val |= BYPASS; 949 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 950 951 /* Enable L1 and L1SS */ 952 val = readl(pcie->parf + PARF_PM_CTRL); 953 val &= ~REQ_NOT_ENTR_L1; 954 writel(val, pcie->parf + PARF_PM_CTRL); 955 956 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 957 val |= EN; 958 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 959 960 return 0; 961 err_disable_clocks: 962 clk_bulk_disable_unprepare(res->num_clks, res->clks); 963 err_disable_regulators: 964 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 965 966 return ret; 967 } 968 969 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) 970 { 971 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 972 973 clk_bulk_disable_unprepare(res->num_clks, res->clks); 974 975 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 976 } 977 978 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) 979 { 980 /* iommu map structure */ 981 struct { 982 u32 bdf; 983 u32 phandle; 984 u32 smmu_sid; 985 u32 smmu_sid_len; 986 } *map; 987 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; 988 struct device *dev = pcie->pci->dev; 989 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 990 int i, nr_map, size = 0; 991 u32 smmu_sid_base; 992 993 of_get_property(dev->of_node, "iommu-map", &size); 994 if (!size) 995 return 0; 996 997 map = kzalloc(size, GFP_KERNEL); 998 if (!map) 999 return -ENOMEM; 1000 1001 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, 1002 size / sizeof(u32)); 1003 1004 nr_map = size / (sizeof(*map)); 1005 1006 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 1007 1008 /* Registers need to be zero out first */ 1009 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 1010 1011 /* Extract the SMMU SID base from the first entry of iommu-map */ 1012 smmu_sid_base = map[0].smmu_sid; 1013 1014 /* Look for an available entry to hold the mapping */ 1015 for (i = 0; i < nr_map; i++) { 1016 __be16 bdf_be = cpu_to_be16(map[i].bdf); 1017 u32 val; 1018 u8 hash; 1019 1020 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0); 1021 1022 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1023 1024 /* If the register is already populated, look for next available entry */ 1025 while (val) { 1026 u8 current_hash = hash++; 1027 u8 next_mask = 0xff; 1028 1029 /* If NEXT field is NULL then update it with next hash */ 1030 if (!(val & next_mask)) { 1031 val |= (u32)hash; 1032 writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 1033 } 1034 1035 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1036 } 1037 1038 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 1039 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 1040 writel(val, bdf_to_sid_base + hash * sizeof(u32)); 1041 } 1042 1043 kfree(map); 1044 1045 return 0; 1046 } 1047 1048 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) 1049 { 1050 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1051 struct dw_pcie *pci = pcie->pci; 1052 struct device *dev = pci->dev; 1053 int ret; 1054 1055 res->clks[0].id = "iface"; 1056 res->clks[1].id = "axi_m"; 1057 res->clks[2].id = "axi_s"; 1058 res->clks[3].id = "axi_bridge"; 1059 res->clks[4].id = "rchng"; 1060 1061 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); 1062 if (ret < 0) 1063 return ret; 1064 1065 res->rst = devm_reset_control_array_get_exclusive(dev); 1066 if (IS_ERR(res->rst)) 1067 return PTR_ERR(res->rst); 1068 1069 return 0; 1070 } 1071 1072 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) 1073 { 1074 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1075 1076 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); 1077 } 1078 1079 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) 1080 { 1081 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1082 struct device *dev = pcie->pci->dev; 1083 int ret; 1084 1085 ret = reset_control_assert(res->rst); 1086 if (ret) { 1087 dev_err(dev, "reset assert failed (%d)\n", ret); 1088 return ret; 1089 } 1090 1091 /* 1092 * Delay periods before and after reset deassert are working values 1093 * from downstream Codeaurora kernel 1094 */ 1095 usleep_range(2000, 2500); 1096 1097 ret = reset_control_deassert(res->rst); 1098 if (ret) { 1099 dev_err(dev, "reset deassert failed (%d)\n", ret); 1100 return ret; 1101 } 1102 1103 usleep_range(2000, 2500); 1104 1105 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); 1106 } 1107 1108 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) 1109 { 1110 struct dw_pcie *pci = pcie->pci; 1111 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1112 u32 val; 1113 int i; 1114 1115 writel(SLV_ADDR_SPACE_SZ, 1116 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); 1117 1118 val = readl(pcie->parf + PARF_PHY_CTRL); 1119 val &= ~PHY_TEST_PWR_DOWN; 1120 writel(val, pcie->parf + PARF_PHY_CTRL); 1121 1122 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); 1123 1124 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 1125 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, 1126 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 1127 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | 1128 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 1129 pci->dbi_base + GEN3_RELATED_OFF); 1130 1131 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | 1132 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 1133 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 1134 pcie->parf + PARF_SYS_CTRL); 1135 1136 writel(0, pcie->parf + PARF_Q2A_FLUSH); 1137 1138 dw_pcie_dbi_ro_wr_en(pci); 1139 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 1140 1141 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 1142 val &= ~PCI_EXP_LNKCAP_ASPMS; 1143 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 1144 1145 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 1146 PCI_EXP_DEVCTL2); 1147 1148 for (i = 0; i < 256; i++) 1149 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); 1150 1151 return 0; 1152 } 1153 1154 static int qcom_pcie_link_up(struct dw_pcie *pci) 1155 { 1156 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1157 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1158 1159 return !!(val & PCI_EXP_LNKSTA_DLLLA); 1160 } 1161 1162 static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 1163 { 1164 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1165 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1166 int ret; 1167 1168 qcom_ep_reset_assert(pcie); 1169 1170 ret = pcie->cfg->ops->init(pcie); 1171 if (ret) 1172 return ret; 1173 1174 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1175 if (ret) 1176 goto err_deinit; 1177 1178 ret = phy_power_on(pcie->phy); 1179 if (ret) 1180 goto err_deinit; 1181 1182 if (pcie->cfg->ops->post_init) { 1183 ret = pcie->cfg->ops->post_init(pcie); 1184 if (ret) 1185 goto err_disable_phy; 1186 } 1187 1188 qcom_ep_reset_deassert(pcie); 1189 1190 if (pcie->cfg->ops->config_sid) { 1191 ret = pcie->cfg->ops->config_sid(pcie); 1192 if (ret) 1193 goto err_assert_reset; 1194 } 1195 1196 return 0; 1197 1198 err_assert_reset: 1199 qcom_ep_reset_assert(pcie); 1200 err_disable_phy: 1201 phy_power_off(pcie->phy); 1202 err_deinit: 1203 pcie->cfg->ops->deinit(pcie); 1204 1205 return ret; 1206 } 1207 1208 static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) 1209 { 1210 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1211 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1212 1213 qcom_ep_reset_assert(pcie); 1214 phy_power_off(pcie->phy); 1215 pcie->cfg->ops->deinit(pcie); 1216 } 1217 1218 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 1219 .host_init = qcom_pcie_host_init, 1220 .host_deinit = qcom_pcie_host_deinit, 1221 }; 1222 1223 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ 1224 static const struct qcom_pcie_ops ops_2_1_0 = { 1225 .get_resources = qcom_pcie_get_resources_2_1_0, 1226 .init = qcom_pcie_init_2_1_0, 1227 .post_init = qcom_pcie_post_init_2_1_0, 1228 .deinit = qcom_pcie_deinit_2_1_0, 1229 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1230 }; 1231 1232 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ 1233 static const struct qcom_pcie_ops ops_1_0_0 = { 1234 .get_resources = qcom_pcie_get_resources_1_0_0, 1235 .init = qcom_pcie_init_1_0_0, 1236 .post_init = qcom_pcie_post_init_1_0_0, 1237 .deinit = qcom_pcie_deinit_1_0_0, 1238 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1239 }; 1240 1241 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ 1242 static const struct qcom_pcie_ops ops_2_3_2 = { 1243 .get_resources = qcom_pcie_get_resources_2_3_2, 1244 .init = qcom_pcie_init_2_3_2, 1245 .post_init = qcom_pcie_post_init_2_3_2, 1246 .deinit = qcom_pcie_deinit_2_3_2, 1247 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1248 }; 1249 1250 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */ 1251 static const struct qcom_pcie_ops ops_2_4_0 = { 1252 .get_resources = qcom_pcie_get_resources_2_4_0, 1253 .init = qcom_pcie_init_2_4_0, 1254 .post_init = qcom_pcie_post_init_2_4_0, 1255 .deinit = qcom_pcie_deinit_2_4_0, 1256 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1257 }; 1258 1259 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */ 1260 static const struct qcom_pcie_ops ops_2_3_3 = { 1261 .get_resources = qcom_pcie_get_resources_2_3_3, 1262 .init = qcom_pcie_init_2_3_3, 1263 .post_init = qcom_pcie_post_init_2_3_3, 1264 .deinit = qcom_pcie_deinit_2_3_3, 1265 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1266 }; 1267 1268 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ 1269 static const struct qcom_pcie_ops ops_2_7_0 = { 1270 .get_resources = qcom_pcie_get_resources_2_7_0, 1271 .init = qcom_pcie_init_2_7_0, 1272 .deinit = qcom_pcie_deinit_2_7_0, 1273 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1274 }; 1275 1276 /* Qcom IP rev.: 1.9.0 */ 1277 static const struct qcom_pcie_ops ops_1_9_0 = { 1278 .get_resources = qcom_pcie_get_resources_2_7_0, 1279 .init = qcom_pcie_init_2_7_0, 1280 .deinit = qcom_pcie_deinit_2_7_0, 1281 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1282 .config_sid = qcom_pcie_config_sid_1_9_0, 1283 }; 1284 1285 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ 1286 static const struct qcom_pcie_ops ops_2_9_0 = { 1287 .get_resources = qcom_pcie_get_resources_2_9_0, 1288 .init = qcom_pcie_init_2_9_0, 1289 .post_init = qcom_pcie_post_init_2_9_0, 1290 .deinit = qcom_pcie_deinit_2_9_0, 1291 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1292 }; 1293 1294 static const struct qcom_pcie_cfg cfg_1_0_0 = { 1295 .ops = &ops_1_0_0, 1296 }; 1297 1298 static const struct qcom_pcie_cfg cfg_1_9_0 = { 1299 .ops = &ops_1_9_0, 1300 }; 1301 1302 static const struct qcom_pcie_cfg cfg_2_1_0 = { 1303 .ops = &ops_2_1_0, 1304 }; 1305 1306 static const struct qcom_pcie_cfg cfg_2_3_2 = { 1307 .ops = &ops_2_3_2, 1308 }; 1309 1310 static const struct qcom_pcie_cfg cfg_2_3_3 = { 1311 .ops = &ops_2_3_3, 1312 }; 1313 1314 static const struct qcom_pcie_cfg cfg_2_4_0 = { 1315 .ops = &ops_2_4_0, 1316 }; 1317 1318 static const struct qcom_pcie_cfg cfg_2_7_0 = { 1319 .ops = &ops_2_7_0, 1320 }; 1321 1322 static const struct qcom_pcie_cfg cfg_2_9_0 = { 1323 .ops = &ops_2_9_0, 1324 }; 1325 1326 static const struct dw_pcie_ops dw_pcie_ops = { 1327 .link_up = qcom_pcie_link_up, 1328 .start_link = qcom_pcie_start_link, 1329 }; 1330 1331 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) 1332 { 1333 struct dw_pcie *pci = pcie->pci; 1334 int ret; 1335 1336 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); 1337 if (IS_ERR(pcie->icc_mem)) 1338 return PTR_ERR(pcie->icc_mem); 1339 1340 /* 1341 * Some Qualcomm platforms require interconnect bandwidth constraints 1342 * to be set before enabling interconnect clocks. 1343 * 1344 * Set an initial peak bandwidth corresponding to single-lane Gen 1 1345 * for the pcie-mem path. 1346 */ 1347 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); 1348 if (ret) { 1349 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 1350 ret); 1351 return ret; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static void qcom_pcie_icc_update(struct qcom_pcie *pcie) 1358 { 1359 struct dw_pcie *pci = pcie->pci; 1360 u32 offset, status, bw; 1361 int speed, width; 1362 int ret; 1363 1364 if (!pcie->icc_mem) 1365 return; 1366 1367 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1368 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1369 1370 /* Only update constraints if link is up. */ 1371 if (!(status & PCI_EXP_LNKSTA_DLLLA)) 1372 return; 1373 1374 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 1375 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 1376 1377 switch (speed) { 1378 case 1: 1379 bw = MBps_to_icc(250); 1380 break; 1381 case 2: 1382 bw = MBps_to_icc(500); 1383 break; 1384 default: 1385 WARN_ON_ONCE(1); 1386 fallthrough; 1387 case 3: 1388 bw = MBps_to_icc(985); 1389 break; 1390 } 1391 1392 ret = icc_set_bw(pcie->icc_mem, 0, width * bw); 1393 if (ret) { 1394 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 1395 ret); 1396 } 1397 } 1398 1399 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) 1400 { 1401 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); 1402 1403 seq_printf(s, "L0s transition count: %u\n", 1404 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 1405 1406 seq_printf(s, "L1 transition count: %u\n", 1407 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 1408 1409 seq_printf(s, "L1.1 transition count: %u\n", 1410 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 1411 1412 seq_printf(s, "L1.2 transition count: %u\n", 1413 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 1414 1415 seq_printf(s, "L2 transition count: %u\n", 1416 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 1417 1418 return 0; 1419 } 1420 1421 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) 1422 { 1423 struct dw_pcie *pci = pcie->pci; 1424 struct device *dev = pci->dev; 1425 char *name; 1426 1427 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1428 if (!name) 1429 return; 1430 1431 pcie->debugfs = debugfs_create_dir(name, NULL); 1432 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, 1433 qcom_pcie_link_transition_count); 1434 } 1435 1436 static int qcom_pcie_probe(struct platform_device *pdev) 1437 { 1438 const struct qcom_pcie_cfg *pcie_cfg; 1439 struct device *dev = &pdev->dev; 1440 struct qcom_pcie *pcie; 1441 struct dw_pcie_rp *pp; 1442 struct resource *res; 1443 struct dw_pcie *pci; 1444 int ret; 1445 1446 pcie_cfg = of_device_get_match_data(dev); 1447 if (!pcie_cfg || !pcie_cfg->ops) { 1448 dev_err(dev, "Invalid platform data\n"); 1449 return -EINVAL; 1450 } 1451 1452 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1453 if (!pcie) 1454 return -ENOMEM; 1455 1456 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1457 if (!pci) 1458 return -ENOMEM; 1459 1460 pm_runtime_enable(dev); 1461 ret = pm_runtime_get_sync(dev); 1462 if (ret < 0) 1463 goto err_pm_runtime_put; 1464 1465 pci->dev = dev; 1466 pci->ops = &dw_pcie_ops; 1467 pp = &pci->pp; 1468 1469 pcie->pci = pci; 1470 1471 pcie->cfg = pcie_cfg; 1472 1473 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 1474 if (IS_ERR(pcie->reset)) { 1475 ret = PTR_ERR(pcie->reset); 1476 goto err_pm_runtime_put; 1477 } 1478 1479 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 1480 if (IS_ERR(pcie->parf)) { 1481 ret = PTR_ERR(pcie->parf); 1482 goto err_pm_runtime_put; 1483 } 1484 1485 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 1486 if (IS_ERR(pcie->elbi)) { 1487 ret = PTR_ERR(pcie->elbi); 1488 goto err_pm_runtime_put; 1489 } 1490 1491 /* MHI region is optional */ 1492 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi"); 1493 if (res) { 1494 pcie->mhi = devm_ioremap_resource(dev, res); 1495 if (IS_ERR(pcie->mhi)) { 1496 ret = PTR_ERR(pcie->mhi); 1497 goto err_pm_runtime_put; 1498 } 1499 } 1500 1501 pcie->phy = devm_phy_optional_get(dev, "pciephy"); 1502 if (IS_ERR(pcie->phy)) { 1503 ret = PTR_ERR(pcie->phy); 1504 goto err_pm_runtime_put; 1505 } 1506 1507 ret = qcom_pcie_icc_init(pcie); 1508 if (ret) 1509 goto err_pm_runtime_put; 1510 1511 ret = pcie->cfg->ops->get_resources(pcie); 1512 if (ret) 1513 goto err_pm_runtime_put; 1514 1515 pp->ops = &qcom_pcie_dw_ops; 1516 1517 ret = phy_init(pcie->phy); 1518 if (ret) 1519 goto err_pm_runtime_put; 1520 1521 platform_set_drvdata(pdev, pcie); 1522 1523 ret = dw_pcie_host_init(pp); 1524 if (ret) { 1525 dev_err(dev, "cannot initialize host\n"); 1526 goto err_phy_exit; 1527 } 1528 1529 qcom_pcie_icc_update(pcie); 1530 1531 if (pcie->mhi) 1532 qcom_pcie_init_debugfs(pcie); 1533 1534 return 0; 1535 1536 err_phy_exit: 1537 phy_exit(pcie->phy); 1538 err_pm_runtime_put: 1539 pm_runtime_put(dev); 1540 pm_runtime_disable(dev); 1541 1542 return ret; 1543 } 1544 1545 static int qcom_pcie_suspend_noirq(struct device *dev) 1546 { 1547 struct qcom_pcie *pcie = dev_get_drvdata(dev); 1548 int ret; 1549 1550 /* 1551 * Set minimum bandwidth required to keep data path functional during 1552 * suspend. 1553 */ 1554 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); 1555 if (ret) { 1556 dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); 1557 return ret; 1558 } 1559 1560 /* 1561 * Turn OFF the resources only for controllers without active PCIe 1562 * devices. For controllers with active devices, the resources are kept 1563 * ON and the link is expected to be in L0/L1 (sub)states. 1564 * 1565 * Turning OFF the resources for controllers with active PCIe devices 1566 * will trigger access violation during the end of the suspend cycle, 1567 * as kernel tries to access the PCIe devices config space for masking 1568 * MSIs. 1569 * 1570 * Also, it is not desirable to put the link into L2/L3 state as that 1571 * implies VDD supply will be removed and the devices may go into 1572 * powerdown state. This will affect the lifetime of the storage devices 1573 * like NVMe. 1574 */ 1575 if (!dw_pcie_link_up(pcie->pci)) { 1576 qcom_pcie_host_deinit(&pcie->pci->pp); 1577 pcie->suspended = true; 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int qcom_pcie_resume_noirq(struct device *dev) 1584 { 1585 struct qcom_pcie *pcie = dev_get_drvdata(dev); 1586 int ret; 1587 1588 if (pcie->suspended) { 1589 ret = qcom_pcie_host_init(&pcie->pci->pp); 1590 if (ret) 1591 return ret; 1592 1593 pcie->suspended = false; 1594 } 1595 1596 qcom_pcie_icc_update(pcie); 1597 1598 return 0; 1599 } 1600 1601 static const struct of_device_id qcom_pcie_match[] = { 1602 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, 1603 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, 1604 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, 1605 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, 1606 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, 1607 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, 1608 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, 1609 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, 1610 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, 1611 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, 1612 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, 1613 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, 1614 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, 1615 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, 1616 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, 1617 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, 1618 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, 1619 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, 1620 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, 1621 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, 1622 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, 1623 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, 1624 { } 1625 }; 1626 1627 static void qcom_fixup_class(struct pci_dev *dev) 1628 { 1629 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 1630 } 1631 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); 1632 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); 1633 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); 1634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); 1635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); 1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); 1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); 1638 1639 static const struct dev_pm_ops qcom_pcie_pm_ops = { 1640 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq) 1641 }; 1642 1643 static struct platform_driver qcom_pcie_driver = { 1644 .probe = qcom_pcie_probe, 1645 .driver = { 1646 .name = "qcom-pcie", 1647 .suppress_bind_attrs = true, 1648 .of_match_table = qcom_pcie_match, 1649 .pm = &qcom_pcie_pm_ops, 1650 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1651 }, 1652 }; 1653 builtin_platform_driver(qcom_pcie_driver); 1654