1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/module.h> 25 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 #include "pcie-qcom-common.h" 29 30 /* PARF registers */ 31 #define PARF_SYS_CTRL 0x00 32 #define PARF_DB_CTRL 0x10 33 #define PARF_PM_CTRL 0x20 34 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 35 #define PARF_MHI_BASE_ADDR_LOWER 0x178 36 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 37 #define PARF_DEBUG_INT_EN 0x190 38 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 39 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 40 #define PARF_Q2A_FLUSH 0x1ac 41 #define PARF_LTSSM 0x1b0 42 #define PARF_CFG_BITS 0x210 43 #define PARF_INT_ALL_STATUS 0x224 44 #define PARF_INT_ALL_CLEAR 0x228 45 #define PARF_INT_ALL_MASK 0x22c 46 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 47 #define PARF_DBI_BASE_ADDR 0x350 48 #define PARF_DBI_BASE_ADDR_HI 0x354 49 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 50 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 51 #define PARF_NO_SNOOP_OVERRIDE 0x3d4 52 #define PARF_ATU_BASE_ADDR 0x634 53 #define PARF_ATU_BASE_ADDR_HI 0x638 54 #define PARF_SRIS_MODE 0x644 55 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 57 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 59 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 60 #define PARF_DEVICE_TYPE 0x1000 61 #define PARF_BDF_TO_SID_CFG 0x2c00 62 #define PARF_INT_ALL_5_MASK 0x2dcc 63 #define PARF_INT_ALL_3_MASK 0x2e18 64 65 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 66 #define PARF_INT_ALL_LINK_DOWN BIT(1) 67 #define PARF_INT_ALL_BME BIT(2) 68 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 69 #define PARF_INT_ALL_DEBUG BIT(4) 70 #define PARF_INT_ALL_LTR BIT(5) 71 #define PARF_INT_ALL_MHI_Q6 BIT(6) 72 #define PARF_INT_ALL_MHI_A7 BIT(7) 73 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 74 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 75 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 76 #define PARF_INT_ALL_CFG_WRITE BIT(11) 77 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 78 #define PARF_INT_ALL_LINK_UP BIT(13) 79 #define PARF_INT_ALL_AER_LEGACY BIT(14) 80 #define PARF_INT_ALL_PLS_ERR BIT(15) 81 #define PARF_INT_ALL_PME_LEGACY BIT(16) 82 #define PARF_INT_ALL_PLS_PME BIT(17) 83 #define PARF_INT_ALL_EDMA BIT(22) 84 85 /* PARF_BDF_TO_SID_CFG register fields */ 86 #define PARF_BDF_TO_SID_BYPASS BIT(0) 87 88 /* PARF_DEBUG_INT_EN register fields */ 89 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 90 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 91 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 92 93 /* PARF_NO_SNOOP_OVERRIDE register fields */ 94 #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) 95 #define RD_NO_SNOOP_OVERRIDE_EN BIT(3) 96 97 /* PARF_DEVICE_TYPE register fields */ 98 #define PARF_DEVICE_TYPE_EP 0x0 99 100 /* PARF_PM_CTRL register fields */ 101 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 102 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 103 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 104 105 /* PARF_MHI_CLOCK_RESET_CTRL fields */ 106 #define PARF_MSTR_AXI_CLK_EN BIT(1) 107 108 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 109 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 110 111 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 112 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 113 114 /* PARF_Q2A_FLUSH register fields */ 115 #define PARF_Q2A_FLUSH_EN BIT(16) 116 117 /* PARF_SYS_CTRL register fields */ 118 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 119 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 120 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) 121 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 122 123 /* PARF_DB_CTRL register fields */ 124 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 125 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 126 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 127 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 128 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 129 130 /* PARF_CFG_BITS register fields */ 131 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 132 133 /* PARF_INT_ALL_5_MASK fields */ 134 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) 135 136 /* PARF_INT_ALL_3_MASK fields */ 137 #define PARF_INT_ALL_3_PTM_UPDATING BIT(4) 138 139 /* ELBI registers */ 140 #define ELBI_SYS_STTS 0x08 141 #define ELBI_CS2_ENABLE 0xa4 142 143 /* DBI registers */ 144 #define DBI_CON_STATUS 0x44 145 146 /* DBI register fields */ 147 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 148 149 #define XMLH_LINK_UP 0x400 150 #define CORE_RESET_TIME_US_MIN 1000 151 #define CORE_RESET_TIME_US_MAX 1005 152 #define WAKE_DELAY_US 2000 /* 2 ms */ 153 154 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 155 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) 156 157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 158 159 enum qcom_pcie_ep_link_status { 160 QCOM_PCIE_EP_LINK_DISABLED, 161 QCOM_PCIE_EP_LINK_ENABLED, 162 QCOM_PCIE_EP_LINK_UP, 163 QCOM_PCIE_EP_LINK_DOWN, 164 }; 165 166 /** 167 * struct qcom_pcie_ep_cfg - Per SoC config struct 168 * @hdma_support: HDMA support on this SoC 169 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 170 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check 171 * @firmware_managed: Set if the controller is firmware managed 172 */ 173 struct qcom_pcie_ep_cfg { 174 bool hdma_support; 175 bool override_no_snoop; 176 bool disable_mhi_ram_parity_check; 177 bool firmware_managed; 178 }; 179 180 /** 181 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 182 * @pci: Designware PCIe controller struct 183 * @parf: Qualcomm PCIe specific PARF register base 184 * @mmio: MMIO register base 185 * @perst_map: PERST regmap 186 * @mmio_res: MMIO region resource 187 * @core_reset: PCIe Endpoint core reset 188 * @reset: PERST# GPIO 189 * @wake: WAKE# GPIO 190 * @phy: PHY controller block 191 * @debugfs: PCIe Endpoint Debugfs directory 192 * @icc_mem: Handle to an interconnect path between PCIe and MEM 193 * @clks: PCIe clocks 194 * @num_clks: PCIe clocks count 195 * @perst_en: Flag for PERST enable 196 * @perst_sep_en: Flag for PERST separation enable 197 * @cfg: PCIe EP config struct 198 * @link_status: PCIe Link status 199 * @global_irq: Qualcomm PCIe specific Global IRQ 200 * @perst_irq: PERST# IRQ 201 */ 202 struct qcom_pcie_ep { 203 struct dw_pcie pci; 204 205 void __iomem *parf; 206 void __iomem *mmio; 207 struct regmap *perst_map; 208 struct resource *mmio_res; 209 210 struct reset_control *core_reset; 211 struct gpio_desc *reset; 212 struct gpio_desc *wake; 213 struct phy *phy; 214 struct dentry *debugfs; 215 216 struct icc_path *icc_mem; 217 218 struct clk_bulk_data *clks; 219 int num_clks; 220 221 u32 perst_en; 222 u32 perst_sep_en; 223 224 const struct qcom_pcie_ep_cfg *cfg; 225 enum qcom_pcie_ep_link_status link_status; 226 int global_irq; 227 int perst_irq; 228 }; 229 230 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 231 { 232 struct dw_pcie *pci = &pcie_ep->pci; 233 struct device *dev = pci->dev; 234 int ret; 235 236 ret = reset_control_assert(pcie_ep->core_reset); 237 if (ret) { 238 dev_err(dev, "Cannot assert core reset\n"); 239 return ret; 240 } 241 242 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 243 244 ret = reset_control_deassert(pcie_ep->core_reset); 245 if (ret) { 246 dev_err(dev, "Cannot de-assert core reset\n"); 247 return ret; 248 } 249 250 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 251 252 return 0; 253 } 254 255 /* 256 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 257 * device reset during host reboot and hibernation. The driver is 258 * expected to handle this situation. 259 */ 260 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 261 { 262 if (pcie_ep->perst_map) { 263 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 264 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 265 } 266 } 267 268 static bool qcom_pcie_dw_link_up(struct dw_pcie *pci) 269 { 270 u32 reg; 271 272 reg = readl_relaxed(pci->elbi_base + ELBI_SYS_STTS); 273 274 return reg & XMLH_LINK_UP; 275 } 276 277 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 278 { 279 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 280 281 enable_irq(pcie_ep->perst_irq); 282 283 return 0; 284 } 285 286 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 287 { 288 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 289 290 disable_irq(pcie_ep->perst_irq); 291 } 292 293 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, 294 u32 reg, size_t size, u32 val) 295 { 296 int ret; 297 298 writel(1, pci->elbi_base + ELBI_CS2_ENABLE); 299 300 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 301 if (ret) 302 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); 303 304 writel(0, pci->elbi_base + ELBI_CS2_ENABLE); 305 } 306 307 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) 308 { 309 struct dw_pcie *pci = &pcie_ep->pci; 310 u32 offset, status; 311 int speed, width; 312 int ret; 313 314 if (!pcie_ep->icc_mem) 315 return; 316 317 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 318 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 319 320 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 321 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 322 323 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 324 if (ret) 325 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 326 ret); 327 } 328 329 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 330 { 331 struct dw_pcie *pci = &pcie_ep->pci; 332 int ret; 333 334 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); 335 if (ret) 336 return ret; 337 338 ret = qcom_pcie_ep_core_reset(pcie_ep); 339 if (ret) 340 goto err_disable_clk; 341 342 ret = phy_init(pcie_ep->phy); 343 if (ret) 344 goto err_disable_clk; 345 346 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); 347 if (ret) 348 goto err_phy_exit; 349 350 ret = phy_power_on(pcie_ep->phy); 351 if (ret) 352 goto err_phy_exit; 353 354 /* 355 * Some Qualcomm platforms require interconnect bandwidth constraints 356 * to be set before enabling interconnect clocks. 357 * 358 * Set an initial peak bandwidth corresponding to single-lane Gen 1 359 * for the pcie-mem path. 360 */ 361 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 362 if (ret) { 363 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 364 ret); 365 goto err_phy_off; 366 } 367 368 return 0; 369 370 err_phy_off: 371 phy_power_off(pcie_ep->phy); 372 err_phy_exit: 373 phy_exit(pcie_ep->phy); 374 err_disable_clk: 375 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 376 377 return ret; 378 } 379 380 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 381 { 382 struct device *dev = pcie_ep->pci.dev; 383 384 pm_runtime_put(dev); 385 386 /* Skip resource disablement if controller is firmware-managed */ 387 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 388 return; 389 390 icc_set_bw(pcie_ep->icc_mem, 0, 0); 391 phy_power_off(pcie_ep->phy); 392 phy_exit(pcie_ep->phy); 393 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 394 } 395 396 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 397 { 398 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 399 struct device *dev = pci->dev; 400 u32 val, offset; 401 int ret; 402 403 ret = pm_runtime_resume_and_get(dev); 404 if (ret < 0) { 405 dev_err(dev, "Failed to enable device: %d\n", ret); 406 return ret; 407 } 408 409 /* Skip resource enablement if controller is firmware-managed */ 410 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 411 goto skip_resources_enable; 412 413 ret = qcom_pcie_enable_resources(pcie_ep); 414 if (ret) { 415 dev_err(dev, "Failed to enable resources: %d\n", ret); 416 pm_runtime_put(dev); 417 return ret; 418 } 419 420 skip_resources_enable: 421 /* Perform cleanup that requires refclk */ 422 pci_epc_deinit_notify(pci->ep.epc); 423 dw_pcie_ep_cleanup(&pci->ep); 424 425 /* Assert WAKE# to RC to indicate device is ready */ 426 gpiod_set_value_cansleep(pcie_ep->wake, 1); 427 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 428 gpiod_set_value_cansleep(pcie_ep->wake, 0); 429 430 qcom_pcie_ep_configure_tcsr(pcie_ep); 431 432 /* Disable BDF to SID mapping */ 433 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 434 val |= PARF_BDF_TO_SID_BYPASS; 435 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 436 437 /* Enable debug IRQ */ 438 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 439 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 440 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 441 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 442 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 443 444 /* Configure PCIe to endpoint mode */ 445 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 446 447 /* Allow entering L1 state */ 448 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 449 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 450 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 451 452 /* Read halts write */ 453 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 454 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 455 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 456 457 /* Write after write halt */ 458 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 459 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 460 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 461 462 /* Q2A flush disable */ 463 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 464 val &= ~PARF_Q2A_FLUSH_EN; 465 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 466 467 /* 468 * Disable Master AXI clock during idle. Do not allow DBI access 469 * to take the core out of L1. Disable core clock gating that 470 * gates PIPE clock from propagating to core clock. Report to the 471 * host that Vaux is present. 472 */ 473 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 474 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; 475 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 476 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 477 PARF_SYS_CTRL_AUX_PWR_DET; 478 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 479 480 /* Disable the debouncers */ 481 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 482 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 483 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 484 PARF_DB_CTRL_MST_WKP_BLOCK; 485 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 486 487 /* Request to exit from L1SS for MSI and LTR MSG */ 488 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 489 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 490 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 491 492 dw_pcie_dbi_ro_wr_en(pci); 493 494 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 495 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 496 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 497 val &= ~PCI_EXP_LNKCAP_L0SEL; 498 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 499 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 500 501 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 502 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 503 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 504 val &= ~PCI_EXP_LNKCAP_L1EL; 505 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 506 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 507 508 dw_pcie_dbi_ro_wr_dis(pci); 509 510 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 511 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 512 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 513 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; 514 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 515 516 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) { 517 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK); 518 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR; 519 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); 520 } 521 522 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK); 523 val &= ~PARF_INT_ALL_3_PTM_UPDATING; 524 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK); 525 526 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); 527 if (ret) { 528 dev_err(dev, "Failed to complete initialization: %d\n", ret); 529 goto err_disable_resources; 530 } 531 532 qcom_pcie_common_set_equalization(pci); 533 534 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) 535 qcom_pcie_common_set_16gt_lane_margining(pci); 536 537 /* 538 * The physical address of the MMIO region which is exposed as the BAR 539 * should be written to MHI BASE registers. 540 */ 541 writel_relaxed(pcie_ep->mmio_res->start, 542 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 543 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 544 545 /* Gate Master AXI clock to MHI bus during L1SS */ 546 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 547 val &= ~PARF_MSTR_AXI_CLK_EN; 548 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 549 550 pci_epc_init_notify(pcie_ep->pci.ep.epc); 551 552 /* Enable LTSSM */ 553 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 554 val |= BIT(8); 555 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 556 557 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop) 558 writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, 559 pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE); 560 561 return 0; 562 563 err_disable_resources: 564 qcom_pcie_disable_resources(pcie_ep); 565 566 return ret; 567 } 568 569 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 570 { 571 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 572 573 qcom_pcie_disable_resources(pcie_ep); 574 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 575 } 576 577 /* Common DWC controller ops */ 578 static const struct dw_pcie_ops pci_ops = { 579 .link_up = qcom_pcie_dw_link_up, 580 .start_link = qcom_pcie_dw_start_link, 581 .stop_link = qcom_pcie_dw_stop_link, 582 .write_dbi2 = qcom_pcie_dw_write_dbi2, 583 }; 584 585 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 586 struct qcom_pcie_ep *pcie_ep) 587 { 588 struct device *dev = &pdev->dev; 589 struct dw_pcie *pci = &pcie_ep->pci; 590 struct device_node *syscon; 591 struct resource *res; 592 int ret; 593 594 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 595 if (IS_ERR(pcie_ep->parf)) 596 return PTR_ERR(pcie_ep->parf); 597 598 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 599 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 600 if (IS_ERR(pci->dbi_base)) 601 return PTR_ERR(pci->dbi_base); 602 pci->dbi_base2 = pci->dbi_base; 603 604 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 605 "mmio"); 606 if (!pcie_ep->mmio_res) { 607 dev_err(dev, "Failed to get mmio resource\n"); 608 return -EINVAL; 609 } 610 611 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); 612 if (IS_ERR(pcie_ep->mmio)) 613 return PTR_ERR(pcie_ep->mmio); 614 615 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 616 if (!syscon) { 617 dev_dbg(dev, "PERST separation not available\n"); 618 return 0; 619 } 620 621 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 622 of_node_put(syscon); 623 if (IS_ERR(pcie_ep->perst_map)) 624 return PTR_ERR(pcie_ep->perst_map); 625 626 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 627 1, &pcie_ep->perst_en); 628 if (ret < 0) { 629 dev_err(dev, "No Perst Enable offset in syscon\n"); 630 return ret; 631 } 632 633 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 634 2, &pcie_ep->perst_sep_en); 635 if (ret < 0) { 636 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 637 return ret; 638 } 639 640 return 0; 641 } 642 643 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 644 struct qcom_pcie_ep *pcie_ep) 645 { 646 struct device *dev = &pdev->dev; 647 int ret; 648 649 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 650 if (ret) { 651 dev_err(dev, "Failed to get io resources %d\n", ret); 652 return ret; 653 } 654 655 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 656 if (IS_ERR(pcie_ep->reset)) 657 return PTR_ERR(pcie_ep->reset); 658 659 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 660 if (IS_ERR(pcie_ep->wake)) 661 return PTR_ERR(pcie_ep->wake); 662 663 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 664 return 0; 665 666 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 667 if (pcie_ep->num_clks < 0) { 668 dev_err(dev, "Failed to get clocks\n"); 669 return pcie_ep->num_clks; 670 } 671 672 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 673 if (IS_ERR(pcie_ep->core_reset)) 674 return PTR_ERR(pcie_ep->core_reset); 675 676 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 677 if (IS_ERR(pcie_ep->phy)) 678 ret = PTR_ERR(pcie_ep->phy); 679 680 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); 681 if (IS_ERR(pcie_ep->icc_mem)) 682 ret = PTR_ERR(pcie_ep->icc_mem); 683 684 return ret; 685 } 686 687 /* TODO: Notify clients about PCIe state change */ 688 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 689 { 690 struct qcom_pcie_ep *pcie_ep = data; 691 struct dw_pcie *pci = &pcie_ep->pci; 692 struct device *dev = pci->dev; 693 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 694 u32 dstate, val; 695 696 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 697 698 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 699 dev_dbg(dev, "Received Linkdown event\n"); 700 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 701 dw_pcie_ep_linkdown(&pci->ep); 702 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 703 dev_dbg(dev, "Received Bus Master Enable event\n"); 704 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 705 qcom_pcie_ep_icc_update(pcie_ep); 706 pci_epc_bus_master_enable_notify(pci->ep.epc); 707 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 708 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 709 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 710 val |= PARF_PM_CTRL_READY_ENTR_L23; 711 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 712 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 713 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 714 DBI_CON_STATUS_POWER_STATE_MASK; 715 dev_dbg(dev, "Received D%d state event\n", dstate); 716 if (dstate == 3) { 717 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 718 val |= PARF_PM_CTRL_REQ_EXIT_L1; 719 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 720 } 721 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 722 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 723 dw_pcie_ep_linkup(&pci->ep); 724 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 725 } else { 726 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", 727 status); 728 } 729 730 return IRQ_HANDLED; 731 } 732 733 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 734 { 735 struct qcom_pcie_ep *pcie_ep = data; 736 struct dw_pcie *pci = &pcie_ep->pci; 737 struct device *dev = pci->dev; 738 u32 perst; 739 740 perst = gpiod_get_value(pcie_ep->reset); 741 if (perst) { 742 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 743 qcom_pcie_perst_assert(pci); 744 } else { 745 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 746 qcom_pcie_perst_deassert(pci); 747 } 748 749 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 750 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 751 752 return IRQ_HANDLED; 753 } 754 755 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 756 struct qcom_pcie_ep *pcie_ep) 757 { 758 struct device *dev = pcie_ep->pci.dev; 759 char *name; 760 int ret; 761 762 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", 763 pcie_ep->pci.ep.epc->domain_nr); 764 if (!name) 765 return -ENOMEM; 766 767 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 768 if (pcie_ep->global_irq < 0) 769 return pcie_ep->global_irq; 770 771 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 772 qcom_pcie_ep_global_irq_thread, 773 IRQF_ONESHOT, 774 name, pcie_ep); 775 if (ret) { 776 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 777 return ret; 778 } 779 780 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", 781 pcie_ep->pci.ep.epc->domain_nr); 782 if (!name) 783 return -ENOMEM; 784 785 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 786 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 787 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 788 qcom_pcie_ep_perst_irq_thread, 789 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 790 name, pcie_ep); 791 if (ret) { 792 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 793 disable_irq(pcie_ep->global_irq); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 801 unsigned int type, u16 interrupt_num) 802 { 803 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 804 805 switch (type) { 806 case PCI_IRQ_INTX: 807 return dw_pcie_ep_raise_intx_irq(ep, func_no); 808 case PCI_IRQ_MSI: 809 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 810 default: 811 dev_err(pci->dev, "Unknown IRQ type\n"); 812 return -EINVAL; 813 } 814 } 815 816 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) 817 { 818 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) 819 dev_get_drvdata(s->private); 820 821 seq_printf(s, "L0s transition count: %u\n", 822 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 823 824 seq_printf(s, "L1 transition count: %u\n", 825 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 826 827 seq_printf(s, "L1.1 transition count: %u\n", 828 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 829 830 seq_printf(s, "L1.2 transition count: %u\n", 831 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 832 833 seq_printf(s, "L2 transition count: %u\n", 834 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 835 836 return 0; 837 } 838 839 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) 840 { 841 struct dw_pcie *pci = &pcie_ep->pci; 842 843 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, 844 qcom_pcie_ep_link_transition_count); 845 } 846 847 static const struct pci_epc_features qcom_pcie_epc_features = { 848 DWC_EPC_COMMON_FEATURES, 849 .linkup_notifier = true, 850 .msi_capable = true, 851 .align = SZ_4K, 852 .bar[BAR_0] = { .only_64bit = true, }, 853 .bar[BAR_1] = { .type = BAR_RESERVED, }, 854 .bar[BAR_2] = { .only_64bit = true, }, 855 .bar[BAR_3] = { .type = BAR_RESERVED, }, 856 }; 857 858 static const struct pci_epc_features * 859 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 860 { 861 return &qcom_pcie_epc_features; 862 } 863 864 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 865 { 866 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 867 enum pci_barno bar; 868 869 for (bar = BAR_0; bar <= BAR_5; bar++) 870 dw_pcie_ep_reset_bar(pci, bar); 871 } 872 873 static const struct dw_pcie_ep_ops pci_ep_ops = { 874 .init = qcom_pcie_ep_init, 875 .raise_irq = qcom_pcie_ep_raise_irq, 876 .get_features = qcom_pcie_epc_get_features, 877 }; 878 879 static int qcom_pcie_ep_probe(struct platform_device *pdev) 880 { 881 struct device *dev = &pdev->dev; 882 struct qcom_pcie_ep *pcie_ep; 883 char *name; 884 int ret; 885 886 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 887 if (!pcie_ep) 888 return -ENOMEM; 889 890 pcie_ep->pci.dev = dev; 891 pcie_ep->pci.ops = &pci_ops; 892 pcie_ep->pci.ep.ops = &pci_ep_ops; 893 894 pcie_ep->cfg = of_device_get_match_data(dev); 895 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) { 896 pcie_ep->pci.edma.ll_wr_cnt = 8; 897 pcie_ep->pci.edma.ll_rd_cnt = 8; 898 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; 899 } 900 901 platform_set_drvdata(pdev, pcie_ep); 902 903 pm_runtime_get_noresume(dev); 904 pm_runtime_set_active(dev); 905 ret = devm_pm_runtime_enable(dev); 906 if (ret) 907 return ret; 908 909 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 910 if (ret) 911 return ret; 912 913 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 914 if (ret) { 915 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 916 return ret; 917 } 918 919 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 920 if (ret) 921 goto err_ep_deinit; 922 923 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 924 if (!name) { 925 ret = -ENOMEM; 926 goto err_disable_irqs; 927 } 928 929 ret = pm_runtime_put_sync(dev); 930 if (ret < 0) { 931 dev_err(dev, "Failed to suspend device: %d\n", ret); 932 goto err_disable_irqs; 933 } 934 935 pcie_ep->debugfs = debugfs_create_dir(name, NULL); 936 qcom_pcie_ep_init_debugfs(pcie_ep); 937 938 return 0; 939 940 err_disable_irqs: 941 disable_irq(pcie_ep->global_irq); 942 disable_irq(pcie_ep->perst_irq); 943 944 err_ep_deinit: 945 dw_pcie_ep_deinit(&pcie_ep->pci.ep); 946 947 return ret; 948 } 949 950 static void qcom_pcie_ep_remove(struct platform_device *pdev) 951 { 952 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 953 954 disable_irq(pcie_ep->global_irq); 955 disable_irq(pcie_ep->perst_irq); 956 957 debugfs_remove_recursive(pcie_ep->debugfs); 958 959 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 960 return; 961 962 qcom_pcie_disable_resources(pcie_ep); 963 } 964 965 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { 966 .hdma_support = true, 967 .override_no_snoop = true, 968 .disable_mhi_ram_parity_check = true, 969 }; 970 971 static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed = { 972 .hdma_support = true, 973 .override_no_snoop = true, 974 .disable_mhi_ram_parity_check = true, 975 .firmware_managed = true, 976 }; 977 978 static const struct of_device_id qcom_pcie_ep_match[] = { 979 { .compatible = "qcom,sa8255p-pcie-ep", .data = &cfg_1_34_0_fw_managed}, 980 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, 981 { .compatible = "qcom,sdx55-pcie-ep", }, 982 { .compatible = "qcom,sm8450-pcie-ep", }, 983 { .compatible = "qcom,sar2130p-pcie-ep", }, 984 { } 985 }; 986 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); 987 988 static struct platform_driver qcom_pcie_ep_driver = { 989 .probe = qcom_pcie_ep_probe, 990 .remove = qcom_pcie_ep_remove, 991 .driver = { 992 .name = "qcom-pcie-ep", 993 .of_match_table = qcom_pcie_ep_match, 994 }, 995 }; 996 builtin_platform_driver(qcom_pcie_ep_driver); 997 998 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 999 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1000 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 1001 MODULE_LICENSE("GPL v2"); 1002