1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/module.h> 25 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 /* PARF registers */ 30 #define PARF_SYS_CTRL 0x00 31 #define PARF_DB_CTRL 0x10 32 #define PARF_PM_CTRL 0x20 33 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 34 #define PARF_MHI_BASE_ADDR_LOWER 0x178 35 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 36 #define PARF_DEBUG_INT_EN 0x190 37 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 38 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 39 #define PARF_Q2A_FLUSH 0x1ac 40 #define PARF_LTSSM 0x1b0 41 #define PARF_CFG_BITS 0x210 42 #define PARF_INT_ALL_STATUS 0x224 43 #define PARF_INT_ALL_CLEAR 0x228 44 #define PARF_INT_ALL_MASK 0x22c 45 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 46 #define PARF_DBI_BASE_ADDR 0x350 47 #define PARF_DBI_BASE_ADDR_HI 0x354 48 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 49 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 50 #define PARF_NO_SNOOP_OVERIDE 0x3d4 51 #define PARF_ATU_BASE_ADDR 0x634 52 #define PARF_ATU_BASE_ADDR_HI 0x638 53 #define PARF_SRIS_MODE 0x644 54 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 55 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 57 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 59 #define PARF_DEVICE_TYPE 0x1000 60 #define PARF_BDF_TO_SID_CFG 0x2c00 61 #define PARF_INT_ALL_5_MASK 0x2dcc 62 63 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 64 #define PARF_INT_ALL_LINK_DOWN BIT(1) 65 #define PARF_INT_ALL_BME BIT(2) 66 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 67 #define PARF_INT_ALL_DEBUG BIT(4) 68 #define PARF_INT_ALL_LTR BIT(5) 69 #define PARF_INT_ALL_MHI_Q6 BIT(6) 70 #define PARF_INT_ALL_MHI_A7 BIT(7) 71 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 72 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 73 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 74 #define PARF_INT_ALL_CFG_WRITE BIT(11) 75 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 76 #define PARF_INT_ALL_LINK_UP BIT(13) 77 #define PARF_INT_ALL_AER_LEGACY BIT(14) 78 #define PARF_INT_ALL_PLS_ERR BIT(15) 79 #define PARF_INT_ALL_PME_LEGACY BIT(16) 80 #define PARF_INT_ALL_PLS_PME BIT(17) 81 #define PARF_INT_ALL_EDMA BIT(22) 82 83 /* PARF_BDF_TO_SID_CFG register fields */ 84 #define PARF_BDF_TO_SID_BYPASS BIT(0) 85 86 /* PARF_DEBUG_INT_EN register fields */ 87 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 88 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 89 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 90 91 /* PARF_NO_SNOOP_OVERIDE register fields */ 92 #define WR_NO_SNOOP_OVERIDE_EN BIT(1) 93 #define RD_NO_SNOOP_OVERIDE_EN BIT(3) 94 95 /* PARF_DEVICE_TYPE register fields */ 96 #define PARF_DEVICE_TYPE_EP 0x0 97 98 /* PARF_PM_CTRL register fields */ 99 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 100 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 101 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 102 103 /* PARF_MHI_CLOCK_RESET_CTRL fields */ 104 #define PARF_MSTR_AXI_CLK_EN BIT(1) 105 106 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 107 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 108 109 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 110 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 111 112 /* PARF_Q2A_FLUSH register fields */ 113 #define PARF_Q2A_FLUSH_EN BIT(16) 114 115 /* PARF_SYS_CTRL register fields */ 116 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 117 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 118 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) 119 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 120 121 /* PARF_DB_CTRL register fields */ 122 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 123 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 124 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 125 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 126 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 127 128 /* PARF_CFG_BITS register fields */ 129 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 130 131 /* PARF_INT_ALL_5_MASK fields */ 132 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) 133 134 /* ELBI registers */ 135 #define ELBI_SYS_STTS 0x08 136 #define ELBI_CS2_ENABLE 0xa4 137 138 /* DBI registers */ 139 #define DBI_CON_STATUS 0x44 140 141 /* DBI register fields */ 142 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 143 144 #define XMLH_LINK_UP 0x400 145 #define CORE_RESET_TIME_US_MIN 1000 146 #define CORE_RESET_TIME_US_MAX 1005 147 #define WAKE_DELAY_US 2000 /* 2 ms */ 148 149 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 150 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) 151 152 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 153 154 enum qcom_pcie_ep_link_status { 155 QCOM_PCIE_EP_LINK_DISABLED, 156 QCOM_PCIE_EP_LINK_ENABLED, 157 QCOM_PCIE_EP_LINK_UP, 158 QCOM_PCIE_EP_LINK_DOWN, 159 }; 160 161 /** 162 * struct qcom_pcie_ep_cfg - Per SoC config struct 163 * @hdma_support: HDMA support on this SoC 164 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 165 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check 166 */ 167 struct qcom_pcie_ep_cfg { 168 bool hdma_support; 169 bool override_no_snoop; 170 bool disable_mhi_ram_parity_check; 171 }; 172 173 /** 174 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 175 * @pci: Designware PCIe controller struct 176 * @parf: Qualcomm PCIe specific PARF register base 177 * @elbi: Designware PCIe specific ELBI register base 178 * @mmio: MMIO register base 179 * @perst_map: PERST regmap 180 * @mmio_res: MMIO region resource 181 * @core_reset: PCIe Endpoint core reset 182 * @reset: PERST# GPIO 183 * @wake: WAKE# GPIO 184 * @phy: PHY controller block 185 * @debugfs: PCIe Endpoint Debugfs directory 186 * @icc_mem: Handle to an interconnect path between PCIe and MEM 187 * @clks: PCIe clocks 188 * @num_clks: PCIe clocks count 189 * @perst_en: Flag for PERST enable 190 * @perst_sep_en: Flag for PERST separation enable 191 * @cfg: PCIe EP config struct 192 * @link_status: PCIe Link status 193 * @global_irq: Qualcomm PCIe specific Global IRQ 194 * @perst_irq: PERST# IRQ 195 */ 196 struct qcom_pcie_ep { 197 struct dw_pcie pci; 198 199 void __iomem *parf; 200 void __iomem *elbi; 201 void __iomem *mmio; 202 struct regmap *perst_map; 203 struct resource *mmio_res; 204 205 struct reset_control *core_reset; 206 struct gpio_desc *reset; 207 struct gpio_desc *wake; 208 struct phy *phy; 209 struct dentry *debugfs; 210 211 struct icc_path *icc_mem; 212 213 struct clk_bulk_data *clks; 214 int num_clks; 215 216 u32 perst_en; 217 u32 perst_sep_en; 218 219 const struct qcom_pcie_ep_cfg *cfg; 220 enum qcom_pcie_ep_link_status link_status; 221 int global_irq; 222 int perst_irq; 223 }; 224 225 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 226 { 227 struct dw_pcie *pci = &pcie_ep->pci; 228 struct device *dev = pci->dev; 229 int ret; 230 231 ret = reset_control_assert(pcie_ep->core_reset); 232 if (ret) { 233 dev_err(dev, "Cannot assert core reset\n"); 234 return ret; 235 } 236 237 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 238 239 ret = reset_control_deassert(pcie_ep->core_reset); 240 if (ret) { 241 dev_err(dev, "Cannot de-assert core reset\n"); 242 return ret; 243 } 244 245 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 246 247 return 0; 248 } 249 250 /* 251 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 252 * device reset during host reboot and hibernation. The driver is 253 * expected to handle this situation. 254 */ 255 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 256 { 257 if (pcie_ep->perst_map) { 258 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 259 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 260 } 261 } 262 263 static int qcom_pcie_dw_link_up(struct dw_pcie *pci) 264 { 265 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 266 u32 reg; 267 268 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 269 270 return reg & XMLH_LINK_UP; 271 } 272 273 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 274 { 275 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 276 277 enable_irq(pcie_ep->perst_irq); 278 279 return 0; 280 } 281 282 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 283 { 284 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 285 286 disable_irq(pcie_ep->perst_irq); 287 } 288 289 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, 290 u32 reg, size_t size, u32 val) 291 { 292 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 293 int ret; 294 295 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE); 296 297 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 298 if (ret) 299 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); 300 301 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); 302 } 303 304 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) 305 { 306 struct dw_pcie *pci = &pcie_ep->pci; 307 u32 offset, status; 308 int speed, width; 309 int ret; 310 311 if (!pcie_ep->icc_mem) 312 return; 313 314 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 315 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 316 317 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 318 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 319 320 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 321 if (ret) 322 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 323 ret); 324 } 325 326 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 327 { 328 struct dw_pcie *pci = &pcie_ep->pci; 329 int ret; 330 331 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); 332 if (ret) 333 return ret; 334 335 ret = qcom_pcie_ep_core_reset(pcie_ep); 336 if (ret) 337 goto err_disable_clk; 338 339 ret = phy_init(pcie_ep->phy); 340 if (ret) 341 goto err_disable_clk; 342 343 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); 344 if (ret) 345 goto err_phy_exit; 346 347 ret = phy_power_on(pcie_ep->phy); 348 if (ret) 349 goto err_phy_exit; 350 351 /* 352 * Some Qualcomm platforms require interconnect bandwidth constraints 353 * to be set before enabling interconnect clocks. 354 * 355 * Set an initial peak bandwidth corresponding to single-lane Gen 1 356 * for the pcie-mem path. 357 */ 358 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 359 if (ret) { 360 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 361 ret); 362 goto err_phy_off; 363 } 364 365 return 0; 366 367 err_phy_off: 368 phy_power_off(pcie_ep->phy); 369 err_phy_exit: 370 phy_exit(pcie_ep->phy); 371 err_disable_clk: 372 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 373 374 return ret; 375 } 376 377 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 378 { 379 icc_set_bw(pcie_ep->icc_mem, 0, 0); 380 phy_power_off(pcie_ep->phy); 381 phy_exit(pcie_ep->phy); 382 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 383 } 384 385 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 386 { 387 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 388 struct device *dev = pci->dev; 389 u32 val, offset; 390 int ret; 391 392 ret = qcom_pcie_enable_resources(pcie_ep); 393 if (ret) { 394 dev_err(dev, "Failed to enable resources: %d\n", ret); 395 return ret; 396 } 397 398 /* Assert WAKE# to RC to indicate device is ready */ 399 gpiod_set_value_cansleep(pcie_ep->wake, 1); 400 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 401 gpiod_set_value_cansleep(pcie_ep->wake, 0); 402 403 qcom_pcie_ep_configure_tcsr(pcie_ep); 404 405 /* Disable BDF to SID mapping */ 406 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 407 val |= PARF_BDF_TO_SID_BYPASS; 408 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 409 410 /* Enable debug IRQ */ 411 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 412 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 413 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 414 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 415 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 416 417 /* Configure PCIe to endpoint mode */ 418 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 419 420 /* Allow entering L1 state */ 421 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 422 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 423 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 424 425 /* Read halts write */ 426 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 427 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 428 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 429 430 /* Write after write halt */ 431 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 432 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 433 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 434 435 /* Q2A flush disable */ 436 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 437 val &= ~PARF_Q2A_FLUSH_EN; 438 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 439 440 /* 441 * Disable Master AXI clock during idle. Do not allow DBI access 442 * to take the core out of L1. Disable core clock gating that 443 * gates PIPE clock from propagating to core clock. Report to the 444 * host that Vaux is present. 445 */ 446 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 447 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; 448 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 449 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 450 PARF_SYS_CTRL_AUX_PWR_DET; 451 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 452 453 /* Disable the debouncers */ 454 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 455 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 456 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 457 PARF_DB_CTRL_MST_WKP_BLOCK; 458 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 459 460 /* Request to exit from L1SS for MSI and LTR MSG */ 461 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 462 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 463 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 464 465 dw_pcie_dbi_ro_wr_en(pci); 466 467 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 468 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 469 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 470 val &= ~PCI_EXP_LNKCAP_L0SEL; 471 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 472 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 473 474 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 475 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 476 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 477 val &= ~PCI_EXP_LNKCAP_L1EL; 478 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 479 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 480 481 dw_pcie_dbi_ro_wr_dis(pci); 482 483 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 484 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 485 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 486 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; 487 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 488 489 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) { 490 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK); 491 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR; 492 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); 493 } 494 495 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); 496 if (ret) { 497 dev_err(dev, "Failed to complete initialization: %d\n", ret); 498 goto err_disable_resources; 499 } 500 501 /* 502 * The physical address of the MMIO region which is exposed as the BAR 503 * should be written to MHI BASE registers. 504 */ 505 writel_relaxed(pcie_ep->mmio_res->start, 506 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 507 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 508 509 /* Gate Master AXI clock to MHI bus during L1SS */ 510 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 511 val &= ~PARF_MSTR_AXI_CLK_EN; 512 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 513 514 pci_epc_init_notify(pcie_ep->pci.ep.epc); 515 516 /* Enable LTSSM */ 517 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 518 val |= BIT(8); 519 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 520 521 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop) 522 writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, 523 pcie_ep->parf + PARF_NO_SNOOP_OVERIDE); 524 525 return 0; 526 527 err_disable_resources: 528 qcom_pcie_disable_resources(pcie_ep); 529 530 return ret; 531 } 532 533 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 534 { 535 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 536 537 pci_epc_deinit_notify(pci->ep.epc); 538 dw_pcie_ep_cleanup(&pci->ep); 539 qcom_pcie_disable_resources(pcie_ep); 540 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 541 } 542 543 /* Common DWC controller ops */ 544 static const struct dw_pcie_ops pci_ops = { 545 .link_up = qcom_pcie_dw_link_up, 546 .start_link = qcom_pcie_dw_start_link, 547 .stop_link = qcom_pcie_dw_stop_link, 548 .write_dbi2 = qcom_pcie_dw_write_dbi2, 549 }; 550 551 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 552 struct qcom_pcie_ep *pcie_ep) 553 { 554 struct device *dev = &pdev->dev; 555 struct dw_pcie *pci = &pcie_ep->pci; 556 struct device_node *syscon; 557 struct resource *res; 558 int ret; 559 560 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 561 if (IS_ERR(pcie_ep->parf)) 562 return PTR_ERR(pcie_ep->parf); 563 564 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 565 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 566 if (IS_ERR(pci->dbi_base)) 567 return PTR_ERR(pci->dbi_base); 568 pci->dbi_base2 = pci->dbi_base; 569 570 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 571 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 572 if (IS_ERR(pcie_ep->elbi)) 573 return PTR_ERR(pcie_ep->elbi); 574 575 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 576 "mmio"); 577 if (!pcie_ep->mmio_res) { 578 dev_err(dev, "Failed to get mmio resource\n"); 579 return -EINVAL; 580 } 581 582 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); 583 if (IS_ERR(pcie_ep->mmio)) 584 return PTR_ERR(pcie_ep->mmio); 585 586 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 587 if (!syscon) { 588 dev_dbg(dev, "PERST separation not available\n"); 589 return 0; 590 } 591 592 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 593 of_node_put(syscon); 594 if (IS_ERR(pcie_ep->perst_map)) 595 return PTR_ERR(pcie_ep->perst_map); 596 597 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 598 1, &pcie_ep->perst_en); 599 if (ret < 0) { 600 dev_err(dev, "No Perst Enable offset in syscon\n"); 601 return ret; 602 } 603 604 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 605 2, &pcie_ep->perst_sep_en); 606 if (ret < 0) { 607 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 608 return ret; 609 } 610 611 return 0; 612 } 613 614 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 615 struct qcom_pcie_ep *pcie_ep) 616 { 617 struct device *dev = &pdev->dev; 618 int ret; 619 620 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 621 if (ret) { 622 dev_err(dev, "Failed to get io resources %d\n", ret); 623 return ret; 624 } 625 626 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 627 if (pcie_ep->num_clks < 0) { 628 dev_err(dev, "Failed to get clocks\n"); 629 return pcie_ep->num_clks; 630 } 631 632 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 633 if (IS_ERR(pcie_ep->core_reset)) 634 return PTR_ERR(pcie_ep->core_reset); 635 636 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 637 if (IS_ERR(pcie_ep->reset)) 638 return PTR_ERR(pcie_ep->reset); 639 640 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 641 if (IS_ERR(pcie_ep->wake)) 642 return PTR_ERR(pcie_ep->wake); 643 644 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 645 if (IS_ERR(pcie_ep->phy)) 646 ret = PTR_ERR(pcie_ep->phy); 647 648 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); 649 if (IS_ERR(pcie_ep->icc_mem)) 650 ret = PTR_ERR(pcie_ep->icc_mem); 651 652 return ret; 653 } 654 655 /* TODO: Notify clients about PCIe state change */ 656 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 657 { 658 struct qcom_pcie_ep *pcie_ep = data; 659 struct dw_pcie *pci = &pcie_ep->pci; 660 struct device *dev = pci->dev; 661 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 662 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 663 u32 dstate, val; 664 665 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 666 status &= mask; 667 668 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 669 dev_dbg(dev, "Received Linkdown event\n"); 670 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 671 dw_pcie_ep_linkdown(&pci->ep); 672 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 673 dev_dbg(dev, "Received Bus Master Enable event\n"); 674 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 675 qcom_pcie_ep_icc_update(pcie_ep); 676 pci_epc_bus_master_enable_notify(pci->ep.epc); 677 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 678 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 679 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 680 val |= PARF_PM_CTRL_READY_ENTR_L23; 681 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 682 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 683 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 684 DBI_CON_STATUS_POWER_STATE_MASK; 685 dev_dbg(dev, "Received D%d state event\n", dstate); 686 if (dstate == 3) { 687 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 688 val |= PARF_PM_CTRL_REQ_EXIT_L1; 689 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 690 } 691 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 692 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 693 dw_pcie_ep_linkup(&pci->ep); 694 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 695 } else { 696 dev_err(dev, "Received unknown event: %d\n", status); 697 } 698 699 return IRQ_HANDLED; 700 } 701 702 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 703 { 704 struct qcom_pcie_ep *pcie_ep = data; 705 struct dw_pcie *pci = &pcie_ep->pci; 706 struct device *dev = pci->dev; 707 u32 perst; 708 709 perst = gpiod_get_value(pcie_ep->reset); 710 if (perst) { 711 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 712 qcom_pcie_perst_assert(pci); 713 } else { 714 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 715 qcom_pcie_perst_deassert(pci); 716 } 717 718 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 719 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 720 721 return IRQ_HANDLED; 722 } 723 724 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 725 struct qcom_pcie_ep *pcie_ep) 726 { 727 int ret; 728 729 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 730 if (pcie_ep->global_irq < 0) 731 return pcie_ep->global_irq; 732 733 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 734 qcom_pcie_ep_global_irq_thread, 735 IRQF_ONESHOT, 736 "global_irq", pcie_ep); 737 if (ret) { 738 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 739 return ret; 740 } 741 742 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 743 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 744 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 745 qcom_pcie_ep_perst_irq_thread, 746 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 747 "perst_irq", pcie_ep); 748 if (ret) { 749 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 750 disable_irq(pcie_ep->global_irq); 751 return ret; 752 } 753 754 return 0; 755 } 756 757 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 758 unsigned int type, u16 interrupt_num) 759 { 760 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 761 762 switch (type) { 763 case PCI_IRQ_INTX: 764 return dw_pcie_ep_raise_intx_irq(ep, func_no); 765 case PCI_IRQ_MSI: 766 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 767 default: 768 dev_err(pci->dev, "Unknown IRQ type\n"); 769 return -EINVAL; 770 } 771 } 772 773 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) 774 { 775 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) 776 dev_get_drvdata(s->private); 777 778 seq_printf(s, "L0s transition count: %u\n", 779 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 780 781 seq_printf(s, "L1 transition count: %u\n", 782 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 783 784 seq_printf(s, "L1.1 transition count: %u\n", 785 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 786 787 seq_printf(s, "L1.2 transition count: %u\n", 788 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 789 790 seq_printf(s, "L2 transition count: %u\n", 791 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 792 793 return 0; 794 } 795 796 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) 797 { 798 struct dw_pcie *pci = &pcie_ep->pci; 799 800 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, 801 qcom_pcie_ep_link_transition_count); 802 } 803 804 static const struct pci_epc_features qcom_pcie_epc_features = { 805 .linkup_notifier = true, 806 .msi_capable = true, 807 .msix_capable = false, 808 .align = SZ_4K, 809 }; 810 811 static const struct pci_epc_features * 812 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 813 { 814 return &qcom_pcie_epc_features; 815 } 816 817 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 818 { 819 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 820 enum pci_barno bar; 821 822 for (bar = BAR_0; bar <= BAR_5; bar++) 823 dw_pcie_ep_reset_bar(pci, bar); 824 } 825 826 static const struct dw_pcie_ep_ops pci_ep_ops = { 827 .init = qcom_pcie_ep_init, 828 .raise_irq = qcom_pcie_ep_raise_irq, 829 .get_features = qcom_pcie_epc_get_features, 830 }; 831 832 static int qcom_pcie_ep_probe(struct platform_device *pdev) 833 { 834 struct device *dev = &pdev->dev; 835 struct qcom_pcie_ep *pcie_ep; 836 char *name; 837 int ret; 838 839 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 840 if (!pcie_ep) 841 return -ENOMEM; 842 843 pcie_ep->pci.dev = dev; 844 pcie_ep->pci.ops = &pci_ops; 845 pcie_ep->pci.ep.ops = &pci_ep_ops; 846 pcie_ep->pci.edma.nr_irqs = 1; 847 848 pcie_ep->cfg = of_device_get_match_data(dev); 849 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) { 850 pcie_ep->pci.edma.ll_wr_cnt = 8; 851 pcie_ep->pci.edma.ll_rd_cnt = 8; 852 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; 853 } 854 855 platform_set_drvdata(pdev, pcie_ep); 856 857 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 858 if (ret) 859 return ret; 860 861 ret = qcom_pcie_enable_resources(pcie_ep); 862 if (ret) { 863 dev_err(dev, "Failed to enable resources: %d\n", ret); 864 return ret; 865 } 866 867 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 868 if (ret) { 869 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 870 goto err_disable_resources; 871 } 872 873 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 874 if (ret) 875 goto err_disable_resources; 876 877 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 878 if (!name) { 879 ret = -ENOMEM; 880 goto err_disable_irqs; 881 } 882 883 pcie_ep->debugfs = debugfs_create_dir(name, NULL); 884 qcom_pcie_ep_init_debugfs(pcie_ep); 885 886 return 0; 887 888 err_disable_irqs: 889 disable_irq(pcie_ep->global_irq); 890 disable_irq(pcie_ep->perst_irq); 891 892 err_disable_resources: 893 qcom_pcie_disable_resources(pcie_ep); 894 895 return ret; 896 } 897 898 static void qcom_pcie_ep_remove(struct platform_device *pdev) 899 { 900 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 901 902 disable_irq(pcie_ep->global_irq); 903 disable_irq(pcie_ep->perst_irq); 904 905 debugfs_remove_recursive(pcie_ep->debugfs); 906 907 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 908 return; 909 910 qcom_pcie_disable_resources(pcie_ep); 911 } 912 913 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { 914 .hdma_support = true, 915 .override_no_snoop = true, 916 .disable_mhi_ram_parity_check = true, 917 }; 918 919 static const struct of_device_id qcom_pcie_ep_match[] = { 920 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, 921 { .compatible = "qcom,sdx55-pcie-ep", }, 922 { .compatible = "qcom,sm8450-pcie-ep", }, 923 { } 924 }; 925 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); 926 927 static struct platform_driver qcom_pcie_ep_driver = { 928 .probe = qcom_pcie_ep_probe, 929 .remove_new = qcom_pcie_ep_remove, 930 .driver = { 931 .name = "qcom-pcie-ep", 932 .of_match_table = qcom_pcie_ep_match, 933 }, 934 }; 935 builtin_platform_driver(qcom_pcie_ep_driver); 936 937 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 938 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 939 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 940 MODULE_LICENSE("GPL v2"); 941