1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/module.h> 25 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 /* PARF registers */ 30 #define PARF_SYS_CTRL 0x00 31 #define PARF_DB_CTRL 0x10 32 #define PARF_PM_CTRL 0x20 33 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 34 #define PARF_MHI_BASE_ADDR_LOWER 0x178 35 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 36 #define PARF_DEBUG_INT_EN 0x190 37 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 38 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 39 #define PARF_Q2A_FLUSH 0x1ac 40 #define PARF_LTSSM 0x1b0 41 #define PARF_CFG_BITS 0x210 42 #define PARF_INT_ALL_STATUS 0x224 43 #define PARF_INT_ALL_CLEAR 0x228 44 #define PARF_INT_ALL_MASK 0x22c 45 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 46 #define PARF_DBI_BASE_ADDR 0x350 47 #define PARF_DBI_BASE_ADDR_HI 0x354 48 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 49 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 50 #define PARF_NO_SNOOP_OVERIDE 0x3d4 51 #define PARF_ATU_BASE_ADDR 0x634 52 #define PARF_ATU_BASE_ADDR_HI 0x638 53 #define PARF_SRIS_MODE 0x644 54 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 55 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 57 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 59 #define PARF_DEVICE_TYPE 0x1000 60 #define PARF_BDF_TO_SID_CFG 0x2c00 61 62 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 63 #define PARF_INT_ALL_LINK_DOWN BIT(1) 64 #define PARF_INT_ALL_BME BIT(2) 65 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 66 #define PARF_INT_ALL_DEBUG BIT(4) 67 #define PARF_INT_ALL_LTR BIT(5) 68 #define PARF_INT_ALL_MHI_Q6 BIT(6) 69 #define PARF_INT_ALL_MHI_A7 BIT(7) 70 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 71 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 72 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 73 #define PARF_INT_ALL_CFG_WRITE BIT(11) 74 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 75 #define PARF_INT_ALL_LINK_UP BIT(13) 76 #define PARF_INT_ALL_AER_LEGACY BIT(14) 77 #define PARF_INT_ALL_PLS_ERR BIT(15) 78 #define PARF_INT_ALL_PME_LEGACY BIT(16) 79 #define PARF_INT_ALL_PLS_PME BIT(17) 80 #define PARF_INT_ALL_EDMA BIT(22) 81 82 /* PARF_BDF_TO_SID_CFG register fields */ 83 #define PARF_BDF_TO_SID_BYPASS BIT(0) 84 85 /* PARF_DEBUG_INT_EN register fields */ 86 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 87 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 88 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 89 90 /* PARF_NO_SNOOP_OVERIDE register fields */ 91 #define WR_NO_SNOOP_OVERIDE_EN BIT(1) 92 #define RD_NO_SNOOP_OVERIDE_EN BIT(3) 93 94 /* PARF_DEVICE_TYPE register fields */ 95 #define PARF_DEVICE_TYPE_EP 0x0 96 97 /* PARF_PM_CTRL register fields */ 98 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 99 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 100 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 101 102 /* PARF_MHI_CLOCK_RESET_CTRL fields */ 103 #define PARF_MSTR_AXI_CLK_EN BIT(1) 104 105 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 106 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 107 108 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 109 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 110 111 /* PARF_Q2A_FLUSH register fields */ 112 #define PARF_Q2A_FLUSH_EN BIT(16) 113 114 /* PARF_SYS_CTRL register fields */ 115 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 116 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 117 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) 118 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 119 120 /* PARF_DB_CTRL register fields */ 121 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 122 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 123 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 124 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 125 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 126 127 /* PARF_CFG_BITS register fields */ 128 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 129 130 /* ELBI registers */ 131 #define ELBI_SYS_STTS 0x08 132 #define ELBI_CS2_ENABLE 0xa4 133 134 /* DBI registers */ 135 #define DBI_CON_STATUS 0x44 136 137 /* DBI register fields */ 138 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 139 140 #define XMLH_LINK_UP 0x400 141 #define CORE_RESET_TIME_US_MIN 1000 142 #define CORE_RESET_TIME_US_MAX 1005 143 #define WAKE_DELAY_US 2000 /* 2 ms */ 144 145 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 146 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) 147 148 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 149 150 enum qcom_pcie_ep_link_status { 151 QCOM_PCIE_EP_LINK_DISABLED, 152 QCOM_PCIE_EP_LINK_ENABLED, 153 QCOM_PCIE_EP_LINK_UP, 154 QCOM_PCIE_EP_LINK_DOWN, 155 }; 156 157 /** 158 * struct qcom_pcie_ep_cfg - Per SoC config struct 159 * @hdma_support: HDMA support on this SoC 160 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 161 */ 162 struct qcom_pcie_ep_cfg { 163 bool hdma_support; 164 bool override_no_snoop; 165 }; 166 167 /** 168 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 169 * @pci: Designware PCIe controller struct 170 * @parf: Qualcomm PCIe specific PARF register base 171 * @elbi: Designware PCIe specific ELBI register base 172 * @mmio: MMIO register base 173 * @perst_map: PERST regmap 174 * @mmio_res: MMIO region resource 175 * @core_reset: PCIe Endpoint core reset 176 * @reset: PERST# GPIO 177 * @wake: WAKE# GPIO 178 * @phy: PHY controller block 179 * @debugfs: PCIe Endpoint Debugfs directory 180 * @icc_mem: Handle to an interconnect path between PCIe and MEM 181 * @clks: PCIe clocks 182 * @num_clks: PCIe clocks count 183 * @perst_en: Flag for PERST enable 184 * @perst_sep_en: Flag for PERST separation enable 185 * @cfg: PCIe EP config struct 186 * @link_status: PCIe Link status 187 * @global_irq: Qualcomm PCIe specific Global IRQ 188 * @perst_irq: PERST# IRQ 189 */ 190 struct qcom_pcie_ep { 191 struct dw_pcie pci; 192 193 void __iomem *parf; 194 void __iomem *elbi; 195 void __iomem *mmio; 196 struct regmap *perst_map; 197 struct resource *mmio_res; 198 199 struct reset_control *core_reset; 200 struct gpio_desc *reset; 201 struct gpio_desc *wake; 202 struct phy *phy; 203 struct dentry *debugfs; 204 205 struct icc_path *icc_mem; 206 207 struct clk_bulk_data *clks; 208 int num_clks; 209 210 u32 perst_en; 211 u32 perst_sep_en; 212 213 const struct qcom_pcie_ep_cfg *cfg; 214 enum qcom_pcie_ep_link_status link_status; 215 int global_irq; 216 int perst_irq; 217 }; 218 219 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 220 { 221 struct dw_pcie *pci = &pcie_ep->pci; 222 struct device *dev = pci->dev; 223 int ret; 224 225 ret = reset_control_assert(pcie_ep->core_reset); 226 if (ret) { 227 dev_err(dev, "Cannot assert core reset\n"); 228 return ret; 229 } 230 231 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 232 233 ret = reset_control_deassert(pcie_ep->core_reset); 234 if (ret) { 235 dev_err(dev, "Cannot de-assert core reset\n"); 236 return ret; 237 } 238 239 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 240 241 return 0; 242 } 243 244 /* 245 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 246 * device reset during host reboot and hibernation. The driver is 247 * expected to handle this situation. 248 */ 249 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 250 { 251 if (pcie_ep->perst_map) { 252 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 253 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 254 } 255 } 256 257 static int qcom_pcie_dw_link_up(struct dw_pcie *pci) 258 { 259 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 260 u32 reg; 261 262 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 263 264 return reg & XMLH_LINK_UP; 265 } 266 267 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 268 { 269 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 270 271 enable_irq(pcie_ep->perst_irq); 272 273 return 0; 274 } 275 276 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 277 { 278 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 279 280 disable_irq(pcie_ep->perst_irq); 281 } 282 283 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, 284 u32 reg, size_t size, u32 val) 285 { 286 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 287 int ret; 288 289 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE); 290 291 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 292 if (ret) 293 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); 294 295 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); 296 } 297 298 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) 299 { 300 struct dw_pcie *pci = &pcie_ep->pci; 301 u32 offset, status; 302 int speed, width; 303 int ret; 304 305 if (!pcie_ep->icc_mem) 306 return; 307 308 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 309 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 310 311 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 312 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 313 314 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 315 if (ret) 316 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 317 ret); 318 } 319 320 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 321 { 322 struct dw_pcie *pci = &pcie_ep->pci; 323 int ret; 324 325 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); 326 if (ret) 327 return ret; 328 329 ret = qcom_pcie_ep_core_reset(pcie_ep); 330 if (ret) 331 goto err_disable_clk; 332 333 ret = phy_init(pcie_ep->phy); 334 if (ret) 335 goto err_disable_clk; 336 337 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); 338 if (ret) 339 goto err_phy_exit; 340 341 ret = phy_power_on(pcie_ep->phy); 342 if (ret) 343 goto err_phy_exit; 344 345 /* 346 * Some Qualcomm platforms require interconnect bandwidth constraints 347 * to be set before enabling interconnect clocks. 348 * 349 * Set an initial peak bandwidth corresponding to single-lane Gen 1 350 * for the pcie-mem path. 351 */ 352 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 353 if (ret) { 354 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 355 ret); 356 goto err_phy_off; 357 } 358 359 return 0; 360 361 err_phy_off: 362 phy_power_off(pcie_ep->phy); 363 err_phy_exit: 364 phy_exit(pcie_ep->phy); 365 err_disable_clk: 366 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 367 368 return ret; 369 } 370 371 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 372 { 373 icc_set_bw(pcie_ep->icc_mem, 0, 0); 374 phy_power_off(pcie_ep->phy); 375 phy_exit(pcie_ep->phy); 376 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 377 } 378 379 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 380 { 381 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 382 struct device *dev = pci->dev; 383 u32 val, offset; 384 int ret; 385 386 ret = qcom_pcie_enable_resources(pcie_ep); 387 if (ret) { 388 dev_err(dev, "Failed to enable resources: %d\n", ret); 389 return ret; 390 } 391 392 /* Assert WAKE# to RC to indicate device is ready */ 393 gpiod_set_value_cansleep(pcie_ep->wake, 1); 394 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 395 gpiod_set_value_cansleep(pcie_ep->wake, 0); 396 397 qcom_pcie_ep_configure_tcsr(pcie_ep); 398 399 /* Disable BDF to SID mapping */ 400 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 401 val |= PARF_BDF_TO_SID_BYPASS; 402 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 403 404 /* Enable debug IRQ */ 405 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 406 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 407 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 408 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 409 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 410 411 /* Configure PCIe to endpoint mode */ 412 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 413 414 /* Allow entering L1 state */ 415 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 416 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 417 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 418 419 /* Read halts write */ 420 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 421 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 422 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 423 424 /* Write after write halt */ 425 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 426 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 427 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 428 429 /* Q2A flush disable */ 430 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 431 val &= ~PARF_Q2A_FLUSH_EN; 432 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 433 434 /* 435 * Disable Master AXI clock during idle. Do not allow DBI access 436 * to take the core out of L1. Disable core clock gating that 437 * gates PIPE clock from propagating to core clock. Report to the 438 * host that Vaux is present. 439 */ 440 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 441 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; 442 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 443 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 444 PARF_SYS_CTRL_AUX_PWR_DET; 445 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 446 447 /* Disable the debouncers */ 448 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 449 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 450 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 451 PARF_DB_CTRL_MST_WKP_BLOCK; 452 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 453 454 /* Request to exit from L1SS for MSI and LTR MSG */ 455 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 456 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 457 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 458 459 dw_pcie_dbi_ro_wr_en(pci); 460 461 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 462 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 463 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 464 val &= ~PCI_EXP_LNKCAP_L0SEL; 465 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); 466 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 467 468 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 469 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 470 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 471 val &= ~PCI_EXP_LNKCAP_L1EL; 472 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); 473 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 474 475 dw_pcie_dbi_ro_wr_dis(pci); 476 477 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 478 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 479 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 480 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; 481 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 482 483 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); 484 if (ret) { 485 dev_err(dev, "Failed to complete initialization: %d\n", ret); 486 goto err_disable_resources; 487 } 488 489 /* 490 * The physical address of the MMIO region which is exposed as the BAR 491 * should be written to MHI BASE registers. 492 */ 493 writel_relaxed(pcie_ep->mmio_res->start, 494 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 495 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 496 497 /* Gate Master AXI clock to MHI bus during L1SS */ 498 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 499 val &= ~PARF_MSTR_AXI_CLK_EN; 500 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 501 502 pci_epc_init_notify(pcie_ep->pci.ep.epc); 503 504 /* Enable LTSSM */ 505 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 506 val |= BIT(8); 507 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 508 509 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop) 510 writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, 511 pcie_ep->parf + PARF_NO_SNOOP_OVERIDE); 512 513 return 0; 514 515 err_disable_resources: 516 qcom_pcie_disable_resources(pcie_ep); 517 518 return ret; 519 } 520 521 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 522 { 523 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 524 525 pci_epc_deinit_notify(pci->ep.epc); 526 dw_pcie_ep_cleanup(&pci->ep); 527 qcom_pcie_disable_resources(pcie_ep); 528 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 529 } 530 531 /* Common DWC controller ops */ 532 static const struct dw_pcie_ops pci_ops = { 533 .link_up = qcom_pcie_dw_link_up, 534 .start_link = qcom_pcie_dw_start_link, 535 .stop_link = qcom_pcie_dw_stop_link, 536 .write_dbi2 = qcom_pcie_dw_write_dbi2, 537 }; 538 539 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 540 struct qcom_pcie_ep *pcie_ep) 541 { 542 struct device *dev = &pdev->dev; 543 struct dw_pcie *pci = &pcie_ep->pci; 544 struct device_node *syscon; 545 struct resource *res; 546 int ret; 547 548 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 549 if (IS_ERR(pcie_ep->parf)) 550 return PTR_ERR(pcie_ep->parf); 551 552 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 553 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 554 if (IS_ERR(pci->dbi_base)) 555 return PTR_ERR(pci->dbi_base); 556 pci->dbi_base2 = pci->dbi_base; 557 558 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 559 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 560 if (IS_ERR(pcie_ep->elbi)) 561 return PTR_ERR(pcie_ep->elbi); 562 563 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 564 "mmio"); 565 if (!pcie_ep->mmio_res) { 566 dev_err(dev, "Failed to get mmio resource\n"); 567 return -EINVAL; 568 } 569 570 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); 571 if (IS_ERR(pcie_ep->mmio)) 572 return PTR_ERR(pcie_ep->mmio); 573 574 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 575 if (!syscon) { 576 dev_dbg(dev, "PERST separation not available\n"); 577 return 0; 578 } 579 580 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 581 of_node_put(syscon); 582 if (IS_ERR(pcie_ep->perst_map)) 583 return PTR_ERR(pcie_ep->perst_map); 584 585 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 586 1, &pcie_ep->perst_en); 587 if (ret < 0) { 588 dev_err(dev, "No Perst Enable offset in syscon\n"); 589 return ret; 590 } 591 592 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 593 2, &pcie_ep->perst_sep_en); 594 if (ret < 0) { 595 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 596 return ret; 597 } 598 599 return 0; 600 } 601 602 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 603 struct qcom_pcie_ep *pcie_ep) 604 { 605 struct device *dev = &pdev->dev; 606 int ret; 607 608 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 609 if (ret) { 610 dev_err(dev, "Failed to get io resources %d\n", ret); 611 return ret; 612 } 613 614 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 615 if (pcie_ep->num_clks < 0) { 616 dev_err(dev, "Failed to get clocks\n"); 617 return pcie_ep->num_clks; 618 } 619 620 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 621 if (IS_ERR(pcie_ep->core_reset)) 622 return PTR_ERR(pcie_ep->core_reset); 623 624 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 625 if (IS_ERR(pcie_ep->reset)) 626 return PTR_ERR(pcie_ep->reset); 627 628 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 629 if (IS_ERR(pcie_ep->wake)) 630 return PTR_ERR(pcie_ep->wake); 631 632 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 633 if (IS_ERR(pcie_ep->phy)) 634 ret = PTR_ERR(pcie_ep->phy); 635 636 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); 637 if (IS_ERR(pcie_ep->icc_mem)) 638 ret = PTR_ERR(pcie_ep->icc_mem); 639 640 return ret; 641 } 642 643 /* TODO: Notify clients about PCIe state change */ 644 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 645 { 646 struct qcom_pcie_ep *pcie_ep = data; 647 struct dw_pcie *pci = &pcie_ep->pci; 648 struct device *dev = pci->dev; 649 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 650 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 651 u32 dstate, val; 652 653 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 654 status &= mask; 655 656 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 657 dev_dbg(dev, "Received Linkdown event\n"); 658 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 659 dw_pcie_ep_linkdown(&pci->ep); 660 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 661 dev_dbg(dev, "Received Bus Master Enable event\n"); 662 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 663 qcom_pcie_ep_icc_update(pcie_ep); 664 pci_epc_bus_master_enable_notify(pci->ep.epc); 665 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 666 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 667 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 668 val |= PARF_PM_CTRL_READY_ENTR_L23; 669 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 670 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 671 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 672 DBI_CON_STATUS_POWER_STATE_MASK; 673 dev_dbg(dev, "Received D%d state event\n", dstate); 674 if (dstate == 3) { 675 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 676 val |= PARF_PM_CTRL_REQ_EXIT_L1; 677 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 678 } 679 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 680 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 681 dw_pcie_ep_linkup(&pci->ep); 682 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 683 } else { 684 dev_err(dev, "Received unknown event: %d\n", status); 685 } 686 687 return IRQ_HANDLED; 688 } 689 690 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 691 { 692 struct qcom_pcie_ep *pcie_ep = data; 693 struct dw_pcie *pci = &pcie_ep->pci; 694 struct device *dev = pci->dev; 695 u32 perst; 696 697 perst = gpiod_get_value(pcie_ep->reset); 698 if (perst) { 699 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 700 qcom_pcie_perst_assert(pci); 701 } else { 702 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 703 qcom_pcie_perst_deassert(pci); 704 } 705 706 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 707 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 708 709 return IRQ_HANDLED; 710 } 711 712 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 713 struct qcom_pcie_ep *pcie_ep) 714 { 715 int ret; 716 717 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 718 if (pcie_ep->global_irq < 0) 719 return pcie_ep->global_irq; 720 721 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 722 qcom_pcie_ep_global_irq_thread, 723 IRQF_ONESHOT, 724 "global_irq", pcie_ep); 725 if (ret) { 726 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 727 return ret; 728 } 729 730 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 731 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 732 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 733 qcom_pcie_ep_perst_irq_thread, 734 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 735 "perst_irq", pcie_ep); 736 if (ret) { 737 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 738 disable_irq(pcie_ep->global_irq); 739 return ret; 740 } 741 742 return 0; 743 } 744 745 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 746 unsigned int type, u16 interrupt_num) 747 { 748 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 749 750 switch (type) { 751 case PCI_IRQ_INTX: 752 return dw_pcie_ep_raise_intx_irq(ep, func_no); 753 case PCI_IRQ_MSI: 754 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 755 default: 756 dev_err(pci->dev, "Unknown IRQ type\n"); 757 return -EINVAL; 758 } 759 } 760 761 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) 762 { 763 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) 764 dev_get_drvdata(s->private); 765 766 seq_printf(s, "L0s transition count: %u\n", 767 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 768 769 seq_printf(s, "L1 transition count: %u\n", 770 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 771 772 seq_printf(s, "L1.1 transition count: %u\n", 773 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 774 775 seq_printf(s, "L1.2 transition count: %u\n", 776 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 777 778 seq_printf(s, "L2 transition count: %u\n", 779 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 780 781 return 0; 782 } 783 784 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) 785 { 786 struct dw_pcie *pci = &pcie_ep->pci; 787 788 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, 789 qcom_pcie_ep_link_transition_count); 790 } 791 792 static const struct pci_epc_features qcom_pcie_epc_features = { 793 .linkup_notifier = true, 794 .msi_capable = true, 795 .msix_capable = false, 796 .align = SZ_4K, 797 }; 798 799 static const struct pci_epc_features * 800 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 801 { 802 return &qcom_pcie_epc_features; 803 } 804 805 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 806 { 807 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 808 enum pci_barno bar; 809 810 for (bar = BAR_0; bar <= BAR_5; bar++) 811 dw_pcie_ep_reset_bar(pci, bar); 812 } 813 814 static const struct dw_pcie_ep_ops pci_ep_ops = { 815 .init = qcom_pcie_ep_init, 816 .raise_irq = qcom_pcie_ep_raise_irq, 817 .get_features = qcom_pcie_epc_get_features, 818 }; 819 820 static int qcom_pcie_ep_probe(struct platform_device *pdev) 821 { 822 struct device *dev = &pdev->dev; 823 struct qcom_pcie_ep *pcie_ep; 824 char *name; 825 int ret; 826 827 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 828 if (!pcie_ep) 829 return -ENOMEM; 830 831 pcie_ep->pci.dev = dev; 832 pcie_ep->pci.ops = &pci_ops; 833 pcie_ep->pci.ep.ops = &pci_ep_ops; 834 pcie_ep->pci.edma.nr_irqs = 1; 835 836 pcie_ep->cfg = of_device_get_match_data(dev); 837 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) { 838 pcie_ep->pci.edma.ll_wr_cnt = 8; 839 pcie_ep->pci.edma.ll_rd_cnt = 8; 840 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; 841 } 842 843 platform_set_drvdata(pdev, pcie_ep); 844 845 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 846 if (ret) 847 return ret; 848 849 ret = qcom_pcie_enable_resources(pcie_ep); 850 if (ret) { 851 dev_err(dev, "Failed to enable resources: %d\n", ret); 852 return ret; 853 } 854 855 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 856 if (ret) { 857 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 858 goto err_disable_resources; 859 } 860 861 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 862 if (ret) 863 goto err_disable_resources; 864 865 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 866 if (!name) { 867 ret = -ENOMEM; 868 goto err_disable_irqs; 869 } 870 871 pcie_ep->debugfs = debugfs_create_dir(name, NULL); 872 qcom_pcie_ep_init_debugfs(pcie_ep); 873 874 return 0; 875 876 err_disable_irqs: 877 disable_irq(pcie_ep->global_irq); 878 disable_irq(pcie_ep->perst_irq); 879 880 err_disable_resources: 881 qcom_pcie_disable_resources(pcie_ep); 882 883 return ret; 884 } 885 886 static void qcom_pcie_ep_remove(struct platform_device *pdev) 887 { 888 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 889 890 disable_irq(pcie_ep->global_irq); 891 disable_irq(pcie_ep->perst_irq); 892 893 debugfs_remove_recursive(pcie_ep->debugfs); 894 895 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 896 return; 897 898 qcom_pcie_disable_resources(pcie_ep); 899 } 900 901 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { 902 .hdma_support = true, 903 .override_no_snoop = true, 904 }; 905 906 static const struct of_device_id qcom_pcie_ep_match[] = { 907 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, 908 { .compatible = "qcom,sdx55-pcie-ep", }, 909 { .compatible = "qcom,sm8450-pcie-ep", }, 910 { } 911 }; 912 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); 913 914 static struct platform_driver qcom_pcie_ep_driver = { 915 .probe = qcom_pcie_ep_probe, 916 .remove_new = qcom_pcie_ep_remove, 917 .driver = { 918 .name = "qcom-pcie-ep", 919 .of_match_table = qcom_pcie_ep_match, 920 }, 921 }; 922 builtin_platform_driver(qcom_pcie_ep_driver); 923 924 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 925 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 926 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 927 MODULE_LICENSE("GPL v2"); 928