1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/pci.h> 7 8 #include "pcie-designware.h" 9 #include "pcie-qcom-common.h" 10 11 void qcom_pcie_common_set_equalization(struct dw_pcie *pci) 12 { 13 struct device *dev = pci->dev; 14 u32 reg; 15 u16 speed; 16 17 /* 18 * GEN3_RELATED_OFF register is repurposed to apply equalization 19 * settings at various data transmission rates through registers namely 20 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF 21 * determines the data rate for which these equalization settings are 22 * applied. 23 */ 24 25 for (speed = PCIE_SPEED_8_0GT; speed <= pcie_get_link_speed(pci->max_link_speed); speed++) { 26 if (speed > PCIE_SPEED_32_0GT) { 27 dev_warn(dev, "Skipped equalization settings for unsupported data rate\n"); 28 break; 29 } 30 31 reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 32 reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 33 FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, ®, 34 speed - PCIE_SPEED_8_0GT); 35 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); 36 37 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); 38 FIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, ®, 0x1); 39 FIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, ®, 0xd); 40 FIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, ®, 0x5); 41 FIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, ®, 0x5); 42 dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); 43 44 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 45 reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | 46 GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | 47 GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | 48 GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); 49 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); 50 } 51 } 52 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); 53 54 void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) 55 { 56 u32 reg; 57 58 reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); 59 FIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, ®, 0x24); 60 FIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, ®, 0x78); 61 FIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, ®, 0x32); 62 FIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, ®, 0x10); 63 dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); 64 65 reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); 66 reg |= MARGINING_IND_ERROR_SAMPLER | 67 MARGINING_SAMPLE_REPORTING_METHOD | 68 MARGINING_IND_LEFT_RIGHT_TIMING | 69 MARGINING_VOLTAGE_SUPPORTED; 70 reg &= ~MARGINING_IND_UP_DOWN_VOLTAGE; 71 FIELD_MODIFY(MARGINING_MAXLANES, ®, pci->num_lanes); 72 FIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, ®, 0x3f); 73 FIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, ®, 0x3f); 74 dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); 75 } 76 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining); 77