1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Kirin Phone SoCs 4 * 5 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd. 6 * https://www.huawei.com 7 * 8 * Author: Xiaowei Song <songxiaowei@huawei.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/compiler.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/gpio.h> 16 #include <linux/interrupt.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_pci.h> 22 #include <linux/phy/phy.h> 23 #include <linux/pci.h> 24 #include <linux/pci_regs.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/resource.h> 28 #include <linux/types.h> 29 #include "pcie-designware.h" 30 31 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev) 32 33 /* PCIe ELBI registers */ 34 #define SOC_PCIECTRL_CTRL0_ADDR 0x000 35 #define SOC_PCIECTRL_CTRL1_ADDR 0x004 36 #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) 37 38 /* info located in APB */ 39 #define PCIE_APP_LTSSM_ENABLE 0x01c 40 #define PCIE_APB_PHY_STATUS0 0x400 41 #define PCIE_LINKUP_ENABLE (0x8020) 42 #define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) 43 44 /* info located in sysctrl */ 45 #define SCTRL_PCIE_CMOS_OFFSET 0x60 46 #define SCTRL_PCIE_CMOS_BIT 0x10 47 #define SCTRL_PCIE_ISO_OFFSET 0x44 48 #define SCTRL_PCIE_ISO_BIT 0x30 49 #define SCTRL_PCIE_HPCLK_OFFSET 0x190 50 #define SCTRL_PCIE_HPCLK_BIT 0x184000 51 #define SCTRL_PCIE_OE_OFFSET 0x14a 52 #define PCIE_DEBOUNCE_PARAM 0xF0F400 53 #define PCIE_OE_BYPASS (0x3 << 28) 54 55 /* 56 * Max number of connected PCI slots at an external PCI bridge 57 * 58 * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected 59 * lanes (lane 0 upstream, and the other three lanes, one connected to an 60 * in-board Ethernet adapter and the other two connected to M.2 and mini 61 * PCI slots. 62 * 63 * Each slot has a different clock source and uses a separate PERST# pin. 64 */ 65 #define MAX_PCI_SLOTS 3 66 67 enum pcie_kirin_phy_type { 68 PCIE_KIRIN_INTERNAL_PHY, 69 PCIE_KIRIN_EXTERNAL_PHY 70 }; 71 72 struct kirin_pcie { 73 enum pcie_kirin_phy_type type; 74 75 struct dw_pcie *pci; 76 struct regmap *apb; 77 struct phy *phy; 78 void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */ 79 80 /* DWC PERST# */ 81 int gpio_id_dwc_perst; 82 83 /* Per-slot PERST# */ 84 int num_slots; 85 int gpio_id_reset[MAX_PCI_SLOTS]; 86 const char *reset_names[MAX_PCI_SLOTS]; 87 88 /* Per-slot clkreq */ 89 int n_gpio_clkreq; 90 int gpio_id_clkreq[MAX_PCI_SLOTS]; 91 const char *clkreq_names[MAX_PCI_SLOTS]; 92 }; 93 94 /* 95 * Kirin 960 PHY. Can't be split into a PHY driver without changing the 96 * DT schema. 97 */ 98 99 #define REF_CLK_FREQ 100000000 100 101 /* PHY info located in APB */ 102 #define PCIE_APB_PHY_CTRL0 0x0 103 #define PCIE_APB_PHY_CTRL1 0x4 104 #define PCIE_APB_PHY_STATUS0 0x400 105 #define PIPE_CLK_STABLE BIT(19) 106 #define PHY_REF_PAD_BIT BIT(8) 107 #define PHY_PWR_DOWN_BIT BIT(22) 108 #define PHY_RST_ACK_BIT BIT(16) 109 110 /* peri_crg ctrl */ 111 #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 112 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 113 114 /* Time for delay */ 115 #define REF_2_PERST_MIN 21000 116 #define REF_2_PERST_MAX 25000 117 #define PERST_2_ACCESS_MIN 10000 118 #define PERST_2_ACCESS_MAX 12000 119 #define PIPE_CLK_WAIT_MIN 550 120 #define PIPE_CLK_WAIT_MAX 600 121 #define TIME_CMOS_MIN 100 122 #define TIME_CMOS_MAX 105 123 #define TIME_PHY_PD_MIN 10 124 #define TIME_PHY_PD_MAX 11 125 126 struct hi3660_pcie_phy { 127 struct device *dev; 128 void __iomem *base; 129 struct regmap *crgctrl; 130 struct regmap *sysctrl; 131 struct clk *apb_sys_clk; 132 struct clk *apb_phy_clk; 133 struct clk *phy_ref_clk; 134 struct clk *aclk; 135 struct clk *aux_clk; 136 }; 137 138 /* Registers in PCIePHY */ 139 static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy, 140 u32 val, u32 reg) 141 { 142 writel(val, hi3660_pcie_phy->base + reg); 143 } 144 145 static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy, 146 u32 reg) 147 { 148 return readl(hi3660_pcie_phy->base + reg); 149 } 150 151 static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy) 152 { 153 struct device *dev = phy->dev; 154 155 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); 156 if (IS_ERR(phy->phy_ref_clk)) 157 return PTR_ERR(phy->phy_ref_clk); 158 159 phy->aux_clk = devm_clk_get(dev, "pcie_aux"); 160 if (IS_ERR(phy->aux_clk)) 161 return PTR_ERR(phy->aux_clk); 162 163 phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); 164 if (IS_ERR(phy->apb_phy_clk)) 165 return PTR_ERR(phy->apb_phy_clk); 166 167 phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); 168 if (IS_ERR(phy->apb_sys_clk)) 169 return PTR_ERR(phy->apb_sys_clk); 170 171 phy->aclk = devm_clk_get(dev, "pcie_aclk"); 172 if (IS_ERR(phy->aclk)) 173 return PTR_ERR(phy->aclk); 174 175 return 0; 176 } 177 178 static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) 179 { 180 struct device *dev = phy->dev; 181 struct platform_device *pdev; 182 183 /* registers */ 184 pdev = container_of(dev, struct platform_device, dev); 185 186 phy->base = devm_platform_ioremap_resource_byname(pdev, "phy"); 187 if (IS_ERR(phy->base)) 188 return PTR_ERR(phy->base); 189 190 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); 191 if (IS_ERR(phy->crgctrl)) 192 return PTR_ERR(phy->crgctrl); 193 194 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); 195 if (IS_ERR(phy->sysctrl)) 196 return PTR_ERR(phy->sysctrl); 197 198 return 0; 199 } 200 201 static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy) 202 { 203 struct device *dev = phy->dev; 204 u32 reg_val; 205 206 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); 207 reg_val &= ~PHY_REF_PAD_BIT; 208 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); 209 210 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0); 211 reg_val &= ~PHY_PWR_DOWN_BIT; 212 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0); 213 usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX); 214 215 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); 216 reg_val &= ~PHY_RST_ACK_BIT; 217 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); 218 219 usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX); 220 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0); 221 if (reg_val & PIPE_CLK_STABLE) { 222 dev_err(dev, "PIPE clk is not stable\n"); 223 return -EINVAL; 224 } 225 226 return 0; 227 } 228 229 static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy) 230 { 231 u32 val; 232 233 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); 234 val |= PCIE_DEBOUNCE_PARAM; 235 val &= ~PCIE_OE_BYPASS; 236 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); 237 } 238 239 static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable) 240 { 241 int ret = 0; 242 243 if (!enable) 244 goto close_clk; 245 246 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); 247 if (ret) 248 return ret; 249 250 ret = clk_prepare_enable(phy->phy_ref_clk); 251 if (ret) 252 return ret; 253 254 ret = clk_prepare_enable(phy->apb_sys_clk); 255 if (ret) 256 goto apb_sys_fail; 257 258 ret = clk_prepare_enable(phy->apb_phy_clk); 259 if (ret) 260 goto apb_phy_fail; 261 262 ret = clk_prepare_enable(phy->aclk); 263 if (ret) 264 goto aclk_fail; 265 266 ret = clk_prepare_enable(phy->aux_clk); 267 if (ret) 268 goto aux_clk_fail; 269 270 return 0; 271 272 close_clk: 273 clk_disable_unprepare(phy->aux_clk); 274 aux_clk_fail: 275 clk_disable_unprepare(phy->aclk); 276 aclk_fail: 277 clk_disable_unprepare(phy->apb_phy_clk); 278 apb_phy_fail: 279 clk_disable_unprepare(phy->apb_sys_clk); 280 apb_sys_fail: 281 clk_disable_unprepare(phy->phy_ref_clk); 282 283 return ret; 284 } 285 286 static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) 287 { 288 struct hi3660_pcie_phy *phy = pcie->phy_priv; 289 int ret; 290 291 /* Power supply for Host */ 292 regmap_write(phy->sysctrl, 293 SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); 294 usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); 295 296 hi3660_pcie_phy_oe_enable(phy); 297 298 ret = hi3660_pcie_phy_clk_ctrl(phy, true); 299 if (ret) 300 return ret; 301 302 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ 303 regmap_write(phy->sysctrl, 304 SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); 305 regmap_write(phy->crgctrl, 306 CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); 307 regmap_write(phy->sysctrl, 308 SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); 309 310 ret = hi3660_pcie_phy_start(phy); 311 if (ret) 312 goto disable_clks; 313 314 return 0; 315 316 disable_clks: 317 hi3660_pcie_phy_clk_ctrl(phy, false); 318 return ret; 319 } 320 321 static int hi3660_pcie_phy_init(struct platform_device *pdev, 322 struct kirin_pcie *pcie) 323 { 324 struct device *dev = &pdev->dev; 325 struct hi3660_pcie_phy *phy; 326 int ret; 327 328 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 329 if (!phy) 330 return -ENOMEM; 331 332 pcie->phy_priv = phy; 333 phy->dev = dev; 334 335 /* registers */ 336 pdev = container_of(dev, struct platform_device, dev); 337 338 ret = hi3660_pcie_phy_get_clk(phy); 339 if (ret) 340 return ret; 341 342 return hi3660_pcie_phy_get_resource(phy); 343 } 344 345 static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie) 346 { 347 struct hi3660_pcie_phy *phy = pcie->phy_priv; 348 349 /* Drop power supply for Host */ 350 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00); 351 352 hi3660_pcie_phy_clk_ctrl(phy, false); 353 354 return 0; 355 } 356 357 /* 358 * The non-PHY part starts here 359 */ 360 361 static const struct regmap_config pcie_kirin_regmap_conf = { 362 .name = "kirin_pcie_apb", 363 .reg_bits = 32, 364 .val_bits = 32, 365 .reg_stride = 4, 366 }; 367 368 static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie, 369 struct platform_device *pdev) 370 { 371 struct device *dev = &pdev->dev; 372 struct device_node *np = dev->of_node; 373 char name[32]; 374 int ret, i; 375 376 /* This is an optional property */ 377 ret = of_gpio_named_count(np, "hisilicon,clken-gpios"); 378 if (ret < 0) 379 return 0; 380 381 if (ret > MAX_PCI_SLOTS) { 382 dev_err(dev, "Too many GPIO clock requests!\n"); 383 return -EINVAL; 384 } 385 386 pcie->n_gpio_clkreq = ret; 387 388 for (i = 0; i < pcie->n_gpio_clkreq; i++) { 389 pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, 390 "hisilicon,clken-gpios", i); 391 if (pcie->gpio_id_clkreq[i] < 0) 392 return pcie->gpio_id_clkreq[i]; 393 394 sprintf(name, "pcie_clkreq_%d", i); 395 pcie->clkreq_names[i] = devm_kstrdup_const(dev, name, 396 GFP_KERNEL); 397 if (!pcie->clkreq_names[i]) 398 return -ENOMEM; 399 } 400 401 return 0; 402 } 403 404 static int kirin_pcie_parse_port(struct kirin_pcie *pcie, 405 struct platform_device *pdev, 406 struct device_node *node) 407 { 408 struct device *dev = &pdev->dev; 409 struct device_node *parent, *child; 410 int ret, slot, i; 411 char name[32]; 412 413 for_each_available_child_of_node(node, parent) { 414 for_each_available_child_of_node(parent, child) { 415 i = pcie->num_slots; 416 417 pcie->gpio_id_reset[i] = of_get_named_gpio(child, 418 "reset-gpios", 0); 419 if (pcie->gpio_id_reset[i] < 0) 420 continue; 421 422 pcie->num_slots++; 423 if (pcie->num_slots > MAX_PCI_SLOTS) { 424 dev_err(dev, "Too many PCI slots!\n"); 425 ret = -EINVAL; 426 goto put_node; 427 } 428 429 ret = of_pci_get_devfn(child); 430 if (ret < 0) { 431 dev_err(dev, "failed to parse devfn: %d\n", ret); 432 goto put_node; 433 } 434 435 slot = PCI_SLOT(ret); 436 437 sprintf(name, "pcie_perst_%d", slot); 438 pcie->reset_names[i] = devm_kstrdup_const(dev, name, 439 GFP_KERNEL); 440 if (!pcie->reset_names[i]) { 441 ret = -ENOMEM; 442 goto put_node; 443 } 444 } 445 } 446 447 return 0; 448 449 put_node: 450 of_node_put(child); 451 of_node_put(parent); 452 return ret; 453 } 454 455 static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, 456 struct platform_device *pdev) 457 { 458 struct device *dev = &pdev->dev; 459 struct device_node *child, *node = dev->of_node; 460 void __iomem *apb_base; 461 int ret; 462 463 apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); 464 if (IS_ERR(apb_base)) 465 return PTR_ERR(apb_base); 466 467 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, 468 &pcie_kirin_regmap_conf); 469 if (IS_ERR(kirin_pcie->apb)) 470 return PTR_ERR(kirin_pcie->apb); 471 472 /* pcie internal PERST# gpio */ 473 kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node, 474 "reset-gpios", 0); 475 if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) { 476 return -EPROBE_DEFER; 477 } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) { 478 dev_err(dev, "unable to get a valid gpio pin\n"); 479 return -ENODEV; 480 } 481 482 ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev); 483 if (ret) 484 return ret; 485 486 /* Parse OF children */ 487 for_each_available_child_of_node(node, child) { 488 ret = kirin_pcie_parse_port(kirin_pcie, pdev, child); 489 if (ret) 490 goto put_node; 491 } 492 493 return 0; 494 495 put_node: 496 of_node_put(child); 497 return ret; 498 } 499 500 static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, 501 bool on) 502 { 503 u32 val; 504 505 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val); 506 if (on) 507 val = val | PCIE_ELBI_SLV_DBI_ENABLE; 508 else 509 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; 510 511 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val); 512 } 513 514 static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, 515 bool on) 516 { 517 u32 val; 518 519 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val); 520 if (on) 521 val = val | PCIE_ELBI_SLV_DBI_ENABLE; 522 else 523 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; 524 525 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val); 526 } 527 528 static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, 529 int where, int size, u32 *val) 530 { 531 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 532 533 if (PCI_SLOT(devfn)) 534 return PCIBIOS_DEVICE_NOT_FOUND; 535 536 *val = dw_pcie_read_dbi(pci, where, size); 537 return PCIBIOS_SUCCESSFUL; 538 } 539 540 static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, 541 int where, int size, u32 val) 542 { 543 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 544 545 if (PCI_SLOT(devfn)) 546 return PCIBIOS_DEVICE_NOT_FOUND; 547 548 dw_pcie_write_dbi(pci, where, size, val); 549 return PCIBIOS_SUCCESSFUL; 550 } 551 552 static int kirin_pcie_add_bus(struct pci_bus *bus) 553 { 554 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 555 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 556 int i, ret; 557 558 if (!kirin_pcie->num_slots) 559 return 0; 560 561 /* Send PERST# to each slot */ 562 for (i = 0; i < kirin_pcie->num_slots; i++) { 563 ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1); 564 if (ret) { 565 dev_err(pci->dev, "PERST# %s error: %d\n", 566 kirin_pcie->reset_names[i], ret); 567 } 568 } 569 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); 570 571 return 0; 572 } 573 574 static struct pci_ops kirin_pci_ops = { 575 .read = kirin_pcie_rd_own_conf, 576 .write = kirin_pcie_wr_own_conf, 577 .add_bus = kirin_pcie_add_bus, 578 }; 579 580 static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, 581 u32 reg, size_t size) 582 { 583 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 584 u32 ret; 585 586 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); 587 dw_pcie_read(base + reg, size, &ret); 588 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); 589 590 return ret; 591 } 592 593 static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, 594 u32 reg, size_t size, u32 val) 595 { 596 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 597 598 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); 599 dw_pcie_write(base + reg, size, val); 600 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); 601 } 602 603 static int kirin_pcie_link_up(struct dw_pcie *pci) 604 { 605 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 606 u32 val; 607 608 regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); 609 if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) 610 return 1; 611 612 return 0; 613 } 614 615 static int kirin_pcie_start_link(struct dw_pcie *pci) 616 { 617 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 618 619 /* assert LTSSM enable */ 620 regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE, 621 PCIE_LTSSM_ENABLE_BIT); 622 623 return 0; 624 } 625 626 static int kirin_pcie_host_init(struct pcie_port *pp) 627 { 628 pp->bridge->ops = &kirin_pci_ops; 629 630 return 0; 631 } 632 633 static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie, 634 struct device *dev) 635 { 636 int ret, i; 637 638 for (i = 0; i < kirin_pcie->num_slots; i++) { 639 if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) { 640 dev_err(dev, "unable to get a valid %s gpio\n", 641 kirin_pcie->reset_names[i]); 642 return -ENODEV; 643 } 644 645 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i], 646 kirin_pcie->reset_names[i]); 647 if (ret) 648 return ret; 649 } 650 651 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { 652 if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) { 653 dev_err(dev, "unable to get a valid %s gpio\n", 654 kirin_pcie->clkreq_names[i]); 655 return -ENODEV; 656 } 657 658 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], 659 kirin_pcie->clkreq_names[i]); 660 if (ret) 661 return ret; 662 663 ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); 664 if (ret) 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static const struct dw_pcie_ops kirin_dw_pcie_ops = { 672 .read_dbi = kirin_pcie_read_dbi, 673 .write_dbi = kirin_pcie_write_dbi, 674 .link_up = kirin_pcie_link_up, 675 .start_link = kirin_pcie_start_link, 676 }; 677 678 static const struct dw_pcie_host_ops kirin_pcie_host_ops = { 679 .host_init = kirin_pcie_host_init, 680 }; 681 682 static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie) 683 { 684 int i; 685 686 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) 687 return hi3660_pcie_phy_power_off(kirin_pcie); 688 689 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) 690 gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1); 691 692 phy_power_off(kirin_pcie->phy); 693 phy_exit(kirin_pcie->phy); 694 695 return 0; 696 } 697 698 static int kirin_pcie_power_on(struct platform_device *pdev, 699 struct kirin_pcie *kirin_pcie) 700 { 701 struct device *dev = &pdev->dev; 702 int ret; 703 704 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { 705 ret = hi3660_pcie_phy_init(pdev, kirin_pcie); 706 if (ret) 707 return ret; 708 709 ret = hi3660_pcie_phy_power_on(kirin_pcie); 710 if (ret) 711 return ret; 712 } else { 713 kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); 714 if (IS_ERR(kirin_pcie->phy)) 715 return PTR_ERR(kirin_pcie->phy); 716 717 ret = kirin_pcie_gpio_request(kirin_pcie, dev); 718 if (ret) 719 return ret; 720 721 ret = phy_init(kirin_pcie->phy); 722 if (ret) 723 goto err; 724 725 ret = phy_power_on(kirin_pcie->phy); 726 if (ret) 727 goto err; 728 } 729 730 /* perst assert Endpoint */ 731 usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); 732 733 if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) { 734 ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1); 735 if (ret) 736 goto err; 737 } 738 739 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); 740 741 return 0; 742 err: 743 kirin_pcie_power_off(kirin_pcie); 744 745 return ret; 746 } 747 748 static int __exit kirin_pcie_remove(struct platform_device *pdev) 749 { 750 struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); 751 752 dw_pcie_host_deinit(&kirin_pcie->pci->pp); 753 754 kirin_pcie_power_off(kirin_pcie); 755 756 return 0; 757 } 758 759 struct kirin_pcie_data { 760 enum pcie_kirin_phy_type phy_type; 761 }; 762 763 static const struct kirin_pcie_data kirin_960_data = { 764 .phy_type = PCIE_KIRIN_INTERNAL_PHY, 765 }; 766 767 static const struct kirin_pcie_data kirin_970_data = { 768 .phy_type = PCIE_KIRIN_EXTERNAL_PHY, 769 }; 770 771 static const struct of_device_id kirin_pcie_match[] = { 772 { .compatible = "hisilicon,kirin960-pcie", .data = &kirin_960_data }, 773 { .compatible = "hisilicon,kirin970-pcie", .data = &kirin_970_data }, 774 {}, 775 }; 776 777 static int kirin_pcie_probe(struct platform_device *pdev) 778 { 779 struct device *dev = &pdev->dev; 780 const struct kirin_pcie_data *data; 781 struct kirin_pcie *kirin_pcie; 782 struct dw_pcie *pci; 783 int ret; 784 785 if (!dev->of_node) { 786 dev_err(dev, "NULL node\n"); 787 return -EINVAL; 788 } 789 790 data = of_device_get_match_data(dev); 791 if (!data) { 792 dev_err(dev, "OF data missing\n"); 793 return -EINVAL; 794 } 795 796 kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); 797 if (!kirin_pcie) 798 return -ENOMEM; 799 800 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 801 if (!pci) 802 return -ENOMEM; 803 804 pci->dev = dev; 805 pci->ops = &kirin_dw_pcie_ops; 806 pci->pp.ops = &kirin_pcie_host_ops; 807 kirin_pcie->pci = pci; 808 kirin_pcie->type = data->phy_type; 809 810 ret = kirin_pcie_get_resource(kirin_pcie, pdev); 811 if (ret) 812 return ret; 813 814 platform_set_drvdata(pdev, kirin_pcie); 815 816 ret = kirin_pcie_power_on(pdev, kirin_pcie); 817 if (ret) 818 return ret; 819 820 return dw_pcie_host_init(&pci->pp); 821 } 822 823 static struct platform_driver kirin_pcie_driver = { 824 .probe = kirin_pcie_probe, 825 .remove = __exit_p(kirin_pcie_remove), 826 .driver = { 827 .name = "kirin-pcie", 828 .of_match_table = kirin_pcie_match, 829 .suppress_bind_attrs = true, 830 }, 831 }; 832 module_platform_driver(kirin_pcie_driver); 833 834 MODULE_DEVICE_TABLE(of, kirin_pcie_match); 835 MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs"); 836 MODULE_AUTHOR("Xiaowei Song <songxiaowei@huawei.com>"); 837 MODULE_LICENSE("GPL v2"); 838