1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Rockchip SoCs. 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 * http://www.rock-chips.com 7 * 8 * Author: Simon Xue <xxm@rock-chips.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/hw_bitfield.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 /* 30 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write 31 * mask for the lower 16 bits. 32 */ 33 34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) 35 36 /* General Control Register */ 37 #define PCIE_CLIENT_GENERAL_CON 0x0 38 #define PCIE_CLIENT_MODE_MASK GENMASK(7, 4) 39 #define PCIE_CLIENT_MODE_EP 0x0UL 40 #define PCIE_CLIENT_MODE_RC 0x4UL 41 #define PCIE_CLIENT_SET_MODE(x) FIELD_PREP_WM16(PCIE_CLIENT_MODE_MASK, (x)) 42 #define PCIE_CLIENT_LD_RQ_RST_GRT FIELD_PREP_WM16(BIT(3), 1) 43 #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1) 44 #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0) 45 46 /* Interrupt Status Register Related to Legacy Interrupt */ 47 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 48 49 /* Interrupt Status Register Related to Miscellaneous Operation */ 50 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 51 #define PCIE_RDLH_LINK_UP_CHGED BIT(1) 52 #define PCIE_LINK_REQ_RST_NOT_INT BIT(2) 53 54 /* Interrupt Mask Register Related to Legacy Interrupt */ 55 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c 56 #define PCIE_INTR_MASK GENMASK(7, 0) 57 #define PCIE_INTR_CLAMP(_x) ((BIT((_x)) & PCIE_INTR_MASK)) 58 #define PCIE_INTR_LEGACY_MASK(x) (PCIE_INTR_CLAMP((x)) | \ 59 (PCIE_INTR_CLAMP((x)) << 16)) 60 #define PCIE_INTR_LEGACY_UNMASK(x) (PCIE_INTR_CLAMP((x)) << 16) 61 62 /* Interrupt Mask Register Related to Miscellaneous Operation */ 63 #define PCIE_CLIENT_INTR_MASK_MISC 0x24 64 65 /* Hot Reset Control Register */ 66 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 67 #define PCIE_LTSSM_APP_DLY2_EN BIT(1) 68 #define PCIE_LTSSM_APP_DLY2_DONE BIT(3) 69 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 70 71 /* LTSSM Status Register */ 72 #define PCIE_CLIENT_LTSSM_STATUS 0x300 73 #define PCIE_LINKUP 0x3 74 #define PCIE_LINKUP_MASK GENMASK(17, 16) 75 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) 76 77 struct rockchip_pcie { 78 struct dw_pcie pci; 79 void __iomem *apb_base; 80 struct phy *phy; 81 struct clk_bulk_data *clks; 82 unsigned int clk_cnt; 83 struct reset_control *rst; 84 struct gpio_desc *rst_gpio; 85 struct regulator *vpcie3v3; 86 struct irq_domain *irq_domain; 87 const struct rockchip_pcie_of_data *data; 88 }; 89 90 struct rockchip_pcie_of_data { 91 enum dw_pcie_device_mode mode; 92 const struct pci_epc_features *epc_features; 93 }; 94 95 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) 96 { 97 return readl_relaxed(rockchip->apb_base + reg); 98 } 99 100 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val, 101 u32 reg) 102 { 103 writel_relaxed(val, rockchip->apb_base + reg); 104 } 105 106 static void rockchip_pcie_intx_handler(struct irq_desc *desc) 107 { 108 struct irq_chip *chip = irq_desc_get_chip(desc); 109 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); 110 unsigned long reg, hwirq; 111 112 chained_irq_enter(chip, desc); 113 114 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); 115 116 for_each_set_bit(hwirq, ®, 4) 117 generic_handle_domain_irq(rockchip->irq_domain, hwirq); 118 119 chained_irq_exit(chip, desc); 120 } 121 122 static void rockchip_intx_mask(struct irq_data *data) 123 { 124 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), 125 PCIE_INTR_LEGACY_MASK(data->hwirq), 126 PCIE_CLIENT_INTR_MASK_LEGACY); 127 }; 128 129 static void rockchip_intx_unmask(struct irq_data *data) 130 { 131 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), 132 PCIE_INTR_LEGACY_UNMASK(data->hwirq), 133 PCIE_CLIENT_INTR_MASK_LEGACY); 134 }; 135 136 static struct irq_chip rockchip_intx_irq_chip = { 137 .name = "INTx", 138 .irq_mask = rockchip_intx_mask, 139 .irq_unmask = rockchip_intx_unmask, 140 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, 141 }; 142 143 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 144 irq_hw_number_t hwirq) 145 { 146 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); 147 irq_set_chip_data(irq, domain->host_data); 148 149 return 0; 150 } 151 152 static const struct irq_domain_ops intx_domain_ops = { 153 .map = rockchip_pcie_intx_map, 154 }; 155 156 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) 157 { 158 struct device *dev = rockchip->pci.dev; 159 struct device_node *intc; 160 161 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); 162 if (!intc) { 163 dev_err(dev, "missing child interrupt-controller node\n"); 164 return -EINVAL; 165 } 166 167 rockchip->irq_domain = irq_domain_create_linear(of_fwnode_handle(intc), PCI_NUM_INTX, 168 &intx_domain_ops, rockchip); 169 of_node_put(intc); 170 if (!rockchip->irq_domain) { 171 dev_err(dev, "failed to get a INTx IRQ domain\n"); 172 return -EINVAL; 173 } 174 175 return 0; 176 } 177 178 static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) 179 { 180 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); 181 } 182 183 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) 184 { 185 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, 186 PCIE_CLIENT_GENERAL_CON); 187 } 188 189 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) 190 { 191 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, 192 PCIE_CLIENT_GENERAL_CON); 193 } 194 195 static bool rockchip_pcie_link_up(struct dw_pcie *pci) 196 { 197 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); 198 u32 val = rockchip_pcie_get_ltssm(rockchip); 199 200 return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP; 201 } 202 203 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) 204 { 205 u32 cap, lnkcap; 206 207 /* Enable L0S capability for all SoCs */ 208 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 209 if (cap) { 210 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 211 lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S; 212 dw_pcie_dbi_ro_wr_en(pci); 213 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 214 dw_pcie_dbi_ro_wr_dis(pci); 215 } 216 } 217 218 static int rockchip_pcie_start_link(struct dw_pcie *pci) 219 { 220 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); 221 222 /* Reset device */ 223 gpiod_set_value_cansleep(rockchip->rst_gpio, 0); 224 225 rockchip_pcie_enable_ltssm(rockchip); 226 227 /* 228 * PCIe requires the refclk to be stable for 100µs prior to releasing 229 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI 230 * Express Card Electromechanical Specification, 1.1. However, we don't 231 * know if the refclk is coming from RC's PHY or external OSC. If it's 232 * from RC, so enabling LTSSM is the just right place to release #PERST. 233 * We need more extra time as before, rather than setting just 234 * 100us as we don't know how long should the device need to reset. 235 */ 236 msleep(PCIE_T_PVPERL_MS); 237 gpiod_set_value_cansleep(rockchip->rst_gpio, 1); 238 239 return 0; 240 } 241 242 static void rockchip_pcie_stop_link(struct dw_pcie *pci) 243 { 244 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); 245 246 rockchip_pcie_disable_ltssm(rockchip); 247 } 248 249 static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) 250 { 251 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 252 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); 253 struct device *dev = rockchip->pci.dev; 254 int irq, ret; 255 256 irq = of_irq_get_byname(dev->of_node, "legacy"); 257 if (irq < 0) 258 return irq; 259 260 ret = rockchip_pcie_init_irq_domain(rockchip); 261 if (ret < 0) 262 dev_err(dev, "failed to init irq domain\n"); 263 264 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, 265 rockchip); 266 267 rockchip_pcie_enable_l0s(pci); 268 269 return 0; 270 } 271 272 static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { 273 .init = rockchip_pcie_host_init, 274 }; 275 276 /* 277 * ATS does not work on RK3588 when running in EP mode. 278 * 279 * After the host has enabled ATS on the EP side, it will send an IOTLB 280 * invalidation request to the EP side. However, the RK3588 will never send 281 * a completion back and eventually the host will print an IOTLB_INV_TIMEOUT 282 * error, and the EP will not be operational. If we hide the ATS capability, 283 * things work as expected. 284 */ 285 static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep) 286 { 287 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 288 struct device *dev = pci->dev; 289 290 /* Only hide the ATS capability for RK3588 running in EP mode. */ 291 if (!of_device_is_compatible(dev->of_node, "rockchip,rk3588-pcie-ep")) 292 return; 293 294 if (dw_pcie_ep_hide_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI, 295 PCI_EXT_CAP_ID_ATS)) 296 dev_err(dev, "failed to hide ATS capability\n"); 297 } 298 299 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) 300 { 301 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 302 enum pci_barno bar; 303 304 rockchip_pcie_enable_l0s(pci); 305 rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); 306 307 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 308 dw_pcie_ep_reset_bar(pci, bar); 309 }; 310 311 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 312 unsigned int type, u16 interrupt_num) 313 { 314 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 315 316 switch (type) { 317 case PCI_IRQ_INTX: 318 return dw_pcie_ep_raise_intx_irq(ep, func_no); 319 case PCI_IRQ_MSI: 320 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 321 case PCI_IRQ_MSIX: 322 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 323 default: 324 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 325 } 326 327 return 0; 328 } 329 330 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { 331 .linkup_notifier = true, 332 .msi_capable = true, 333 .msix_capable = true, 334 .align = SZ_64K, 335 .bar[BAR_0] = { .type = BAR_RESIZABLE, }, 336 .bar[BAR_1] = { .type = BAR_RESIZABLE, }, 337 .bar[BAR_2] = { .type = BAR_RESIZABLE, }, 338 .bar[BAR_3] = { .type = BAR_RESIZABLE, }, 339 .bar[BAR_4] = { .type = BAR_RESIZABLE, }, 340 .bar[BAR_5] = { .type = BAR_RESIZABLE, }, 341 }; 342 343 /* 344 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of 345 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, 346 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by 347 * default.) If the host could write to BAR4, the iATU settings (for all other 348 * BARs) would be overwritten, resulting in (all other BARs) no longer working. 349 */ 350 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { 351 .linkup_notifier = true, 352 .msi_capable = true, 353 .msix_capable = true, 354 .align = SZ_64K, 355 .bar[BAR_0] = { .type = BAR_RESIZABLE, }, 356 .bar[BAR_1] = { .type = BAR_RESIZABLE, }, 357 .bar[BAR_2] = { .type = BAR_RESIZABLE, }, 358 .bar[BAR_3] = { .type = BAR_RESIZABLE, }, 359 .bar[BAR_4] = { .type = BAR_RESERVED, }, 360 .bar[BAR_5] = { .type = BAR_RESIZABLE, }, 361 }; 362 363 static const struct pci_epc_features * 364 rockchip_pcie_get_features(struct dw_pcie_ep *ep) 365 { 366 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 367 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); 368 369 return rockchip->data->epc_features; 370 } 371 372 static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = { 373 .init = rockchip_pcie_ep_init, 374 .raise_irq = rockchip_pcie_raise_irq, 375 .get_features = rockchip_pcie_get_features, 376 }; 377 378 static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) 379 { 380 struct device *dev = rockchip->pci.dev; 381 int ret; 382 383 ret = devm_clk_bulk_get_all(dev, &rockchip->clks); 384 if (ret < 0) 385 return dev_err_probe(dev, ret, "failed to get clocks\n"); 386 387 rockchip->clk_cnt = ret; 388 389 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); 390 if (ret) 391 return dev_err_probe(dev, ret, "failed to enable clocks\n"); 392 393 return 0; 394 } 395 396 static int rockchip_pcie_resource_get(struct platform_device *pdev, 397 struct rockchip_pcie *rockchip) 398 { 399 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); 400 if (IS_ERR(rockchip->apb_base)) 401 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base), 402 "failed to map apb registers\n"); 403 404 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", 405 GPIOD_OUT_LOW); 406 if (IS_ERR(rockchip->rst_gpio)) 407 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio), 408 "failed to get reset gpio\n"); 409 410 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev); 411 if (IS_ERR(rockchip->rst)) 412 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), 413 "failed to get reset lines\n"); 414 415 return 0; 416 } 417 418 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip) 419 { 420 struct device *dev = rockchip->pci.dev; 421 int ret; 422 423 rockchip->phy = devm_phy_get(dev, "pcie-phy"); 424 if (IS_ERR(rockchip->phy)) 425 return dev_err_probe(dev, PTR_ERR(rockchip->phy), 426 "missing PHY\n"); 427 428 ret = phy_init(rockchip->phy); 429 if (ret < 0) 430 return ret; 431 432 ret = phy_power_on(rockchip->phy); 433 if (ret) 434 phy_exit(rockchip->phy); 435 436 return ret; 437 } 438 439 static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) 440 { 441 phy_power_off(rockchip->phy); 442 phy_exit(rockchip->phy); 443 } 444 445 static const struct dw_pcie_ops dw_pcie_ops = { 446 .link_up = rockchip_pcie_link_up, 447 .start_link = rockchip_pcie_start_link, 448 .stop_link = rockchip_pcie_stop_link, 449 }; 450 451 static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) 452 { 453 struct rockchip_pcie *rockchip = arg; 454 struct dw_pcie *pci = &rockchip->pci; 455 struct dw_pcie_rp *pp = &pci->pp; 456 struct device *dev = pci->dev; 457 u32 reg; 458 459 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); 460 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); 461 462 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg); 463 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); 464 465 if (reg & PCIE_RDLH_LINK_UP_CHGED) { 466 if (rockchip_pcie_link_up(pci)) { 467 msleep(PCIE_RESET_CONFIG_WAIT_MS); 468 dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); 469 /* Rescan the bus to enumerate endpoint devices */ 470 pci_lock_rescan_remove(); 471 pci_rescan_bus(pp->bridge->bus); 472 pci_unlock_rescan_remove(); 473 } 474 } 475 476 return IRQ_HANDLED; 477 } 478 479 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) 480 { 481 struct rockchip_pcie *rockchip = arg; 482 struct dw_pcie *pci = &rockchip->pci; 483 struct device *dev = pci->dev; 484 u32 reg, val; 485 486 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); 487 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); 488 489 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg); 490 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); 491 492 if (reg & PCIE_LINK_REQ_RST_NOT_INT) { 493 dev_dbg(dev, "hot reset or link-down reset\n"); 494 dw_pcie_ep_linkdown(&pci->ep); 495 /* Stop delaying link training. */ 496 val = FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_DONE, 1); 497 rockchip_pcie_writel_apb(rockchip, val, 498 PCIE_CLIENT_HOT_RESET_CTRL); 499 } 500 501 if (reg & PCIE_RDLH_LINK_UP_CHGED) { 502 if (rockchip_pcie_link_up(pci)) { 503 dev_dbg(dev, "link up\n"); 504 dw_pcie_ep_linkup(&pci->ep); 505 } 506 } 507 508 return IRQ_HANDLED; 509 } 510 511 static int rockchip_pcie_configure_rc(struct platform_device *pdev, 512 struct rockchip_pcie *rockchip) 513 { 514 struct device *dev = &pdev->dev; 515 struct dw_pcie_rp *pp; 516 int irq, ret; 517 u32 val; 518 519 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST)) 520 return -ENODEV; 521 522 irq = platform_get_irq_byname(pdev, "sys"); 523 if (irq < 0) 524 return irq; 525 526 ret = devm_request_threaded_irq(dev, irq, NULL, 527 rockchip_pcie_rc_sys_irq_thread, 528 IRQF_ONESHOT, "pcie-sys-rc", rockchip); 529 if (ret) { 530 dev_err(dev, "failed to request PCIe sys IRQ\n"); 531 return ret; 532 } 533 534 /* LTSSM enable control mode */ 535 val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); 536 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); 537 538 rockchip_pcie_writel_apb(rockchip, 539 PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), 540 PCIE_CLIENT_GENERAL_CON); 541 542 pp = &rockchip->pci.pp; 543 pp->ops = &rockchip_pcie_host_ops; 544 pp->use_linkup_irq = true; 545 546 ret = dw_pcie_host_init(pp); 547 if (ret) { 548 dev_err(dev, "failed to initialize host\n"); 549 return ret; 550 } 551 552 /* unmask DLL up/down indicator */ 553 val = FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0); 554 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); 555 556 return ret; 557 } 558 559 static int rockchip_pcie_configure_ep(struct platform_device *pdev, 560 struct rockchip_pcie *rockchip) 561 { 562 struct device *dev = &pdev->dev; 563 int irq, ret; 564 u32 val; 565 566 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) 567 return -ENODEV; 568 569 irq = platform_get_irq_byname(pdev, "sys"); 570 if (irq < 0) 571 return irq; 572 573 ret = devm_request_threaded_irq(dev, irq, NULL, 574 rockchip_pcie_ep_sys_irq_thread, 575 IRQF_ONESHOT, "pcie-sys-ep", rockchip); 576 if (ret) { 577 dev_err(dev, "failed to request PCIe sys IRQ\n"); 578 return ret; 579 } 580 581 /* 582 * LTSSM enable control mode, and automatically delay link training on 583 * hot reset/link-down reset. 584 */ 585 val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) | 586 FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1); 587 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); 588 589 rockchip_pcie_writel_apb(rockchip, 590 PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP), 591 PCIE_CLIENT_GENERAL_CON); 592 593 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; 594 rockchip->pci.ep.page_size = SZ_64K; 595 596 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 597 598 ret = dw_pcie_ep_init(&rockchip->pci.ep); 599 if (ret) { 600 dev_err(dev, "failed to initialize endpoint\n"); 601 return ret; 602 } 603 604 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep); 605 if (ret) { 606 dev_err(dev, "failed to initialize DWC endpoint registers\n"); 607 dw_pcie_ep_deinit(&rockchip->pci.ep); 608 return ret; 609 } 610 611 pci_epc_init_notify(rockchip->pci.ep.epc); 612 613 /* unmask DLL up/down indicator and hot reset/link-down reset */ 614 val = FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0) | 615 FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0); 616 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); 617 618 return ret; 619 } 620 621 static int rockchip_pcie_probe(struct platform_device *pdev) 622 { 623 struct device *dev = &pdev->dev; 624 struct rockchip_pcie *rockchip; 625 const struct rockchip_pcie_of_data *data; 626 int ret; 627 628 data = of_device_get_match_data(dev); 629 if (!data) 630 return -EINVAL; 631 632 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); 633 if (!rockchip) 634 return -ENOMEM; 635 636 platform_set_drvdata(pdev, rockchip); 637 638 rockchip->pci.dev = dev; 639 rockchip->pci.ops = &dw_pcie_ops; 640 rockchip->data = data; 641 642 /* Default N_FTS value (210) is broken, override it to 255 */ 643 rockchip->pci.n_fts[0] = 255; /* Gen1 */ 644 rockchip->pci.n_fts[1] = 255; /* Gen2+ */ 645 646 ret = rockchip_pcie_resource_get(pdev, rockchip); 647 if (ret) 648 return ret; 649 650 ret = reset_control_assert(rockchip->rst); 651 if (ret) 652 return ret; 653 654 /* DON'T MOVE ME: must be enable before PHY init */ 655 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); 656 if (IS_ERR(rockchip->vpcie3v3)) { 657 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV) 658 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3), 659 "failed to get vpcie3v3 regulator\n"); 660 rockchip->vpcie3v3 = NULL; 661 } else { 662 ret = regulator_enable(rockchip->vpcie3v3); 663 if (ret) 664 return dev_err_probe(dev, ret, 665 "failed to enable vpcie3v3 regulator\n"); 666 } 667 668 ret = rockchip_pcie_phy_init(rockchip); 669 if (ret) 670 goto disable_regulator; 671 672 ret = reset_control_deassert(rockchip->rst); 673 if (ret) 674 goto deinit_phy; 675 676 ret = rockchip_pcie_clk_init(rockchip); 677 if (ret) 678 goto deinit_phy; 679 680 switch (data->mode) { 681 case DW_PCIE_RC_TYPE: 682 ret = rockchip_pcie_configure_rc(pdev, rockchip); 683 if (ret) 684 goto deinit_clk; 685 break; 686 case DW_PCIE_EP_TYPE: 687 ret = rockchip_pcie_configure_ep(pdev, rockchip); 688 if (ret) 689 goto deinit_clk; 690 break; 691 default: 692 dev_err(dev, "INVALID device type %d\n", data->mode); 693 ret = -EINVAL; 694 goto deinit_clk; 695 } 696 697 return 0; 698 699 deinit_clk: 700 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); 701 deinit_phy: 702 rockchip_pcie_phy_deinit(rockchip); 703 disable_regulator: 704 if (rockchip->vpcie3v3) 705 regulator_disable(rockchip->vpcie3v3); 706 707 return ret; 708 } 709 710 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { 711 .mode = DW_PCIE_RC_TYPE, 712 }; 713 714 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = { 715 .mode = DW_PCIE_EP_TYPE, 716 .epc_features = &rockchip_pcie_epc_features_rk3568, 717 }; 718 719 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = { 720 .mode = DW_PCIE_EP_TYPE, 721 .epc_features = &rockchip_pcie_epc_features_rk3588, 722 }; 723 724 static const struct of_device_id rockchip_pcie_of_match[] = { 725 { 726 .compatible = "rockchip,rk3568-pcie", 727 .data = &rockchip_pcie_rc_of_data_rk3568, 728 }, 729 { 730 .compatible = "rockchip,rk3568-pcie-ep", 731 .data = &rockchip_pcie_ep_of_data_rk3568, 732 }, 733 { 734 .compatible = "rockchip,rk3588-pcie-ep", 735 .data = &rockchip_pcie_ep_of_data_rk3588, 736 }, 737 {}, 738 }; 739 740 static struct platform_driver rockchip_pcie_driver = { 741 .driver = { 742 .name = "rockchip-dw-pcie", 743 .of_match_table = rockchip_pcie_of_match, 744 .suppress_bind_attrs = true, 745 }, 746 .probe = rockchip_pcie_probe, 747 }; 748 builtin_platform_driver(rockchip_pcie_driver); 749