1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/sizes.h> 21 #include <linux/types.h> 22 23 #include "../../pci.h" 24 #include "pcie-designware.h" 25 26 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 27 [DW_PCIE_DBI_CLK] = "dbi", 28 [DW_PCIE_MSTR_CLK] = "mstr", 29 [DW_PCIE_SLV_CLK] = "slv", 30 }; 31 32 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 33 [DW_PCIE_PIPE_CLK] = "pipe", 34 [DW_PCIE_CORE_CLK] = "core", 35 [DW_PCIE_AUX_CLK] = "aux", 36 [DW_PCIE_REF_CLK] = "ref", 37 }; 38 39 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 40 [DW_PCIE_DBI_RST] = "dbi", 41 [DW_PCIE_MSTR_RST] = "mstr", 42 [DW_PCIE_SLV_RST] = "slv", 43 }; 44 45 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 46 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 47 [DW_PCIE_STICKY_RST] = "sticky", 48 [DW_PCIE_CORE_RST] = "core", 49 [DW_PCIE_PIPE_RST] = "pipe", 50 [DW_PCIE_PHY_RST] = "phy", 51 [DW_PCIE_HOT_RST] = "hot", 52 [DW_PCIE_PWR_RST] = "pwr", 53 }; 54 55 static int dw_pcie_get_clocks(struct dw_pcie *pci) 56 { 57 int i, ret; 58 59 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 60 pci->app_clks[i].id = dw_pcie_app_clks[i]; 61 62 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 63 pci->core_clks[i].id = dw_pcie_core_clks[i]; 64 65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 66 pci->app_clks); 67 if (ret) 68 return ret; 69 70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 71 pci->core_clks); 72 } 73 74 static int dw_pcie_get_resets(struct dw_pcie *pci) 75 { 76 int i, ret; 77 78 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 80 81 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 82 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 83 84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 85 DW_PCIE_NUM_APP_RSTS, 86 pci->app_rsts); 87 if (ret) 88 return ret; 89 90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 91 DW_PCIE_NUM_CORE_RSTS, 92 pci->core_rsts); 93 if (ret) 94 return ret; 95 96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 97 if (IS_ERR(pci->pe_rst)) 98 return PTR_ERR(pci->pe_rst); 99 100 return 0; 101 } 102 103 int dw_pcie_get_resources(struct dw_pcie *pci) 104 { 105 struct platform_device *pdev = to_platform_device(pci->dev); 106 struct device_node *np = dev_of_node(pci->dev); 107 struct resource *res; 108 int ret; 109 110 if (!pci->dbi_base) { 111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 113 if (IS_ERR(pci->dbi_base)) 114 return PTR_ERR(pci->dbi_base); 115 pci->dbi_phys_addr = res->start; 116 } 117 118 /* DBI2 is mainly useful for the endpoint controller */ 119 if (!pci->dbi_base2) { 120 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 121 if (res) { 122 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 123 if (IS_ERR(pci->dbi_base2)) 124 return PTR_ERR(pci->dbi_base2); 125 } else { 126 pci->dbi_base2 = pci->dbi_base + SZ_4K; 127 } 128 } 129 130 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 131 if (!pci->atu_base) { 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 133 if (res) { 134 pci->atu_size = resource_size(res); 135 pci->atu_base = devm_ioremap_resource(pci->dev, res); 136 if (IS_ERR(pci->atu_base)) 137 return PTR_ERR(pci->atu_base); 138 pci->atu_phys_addr = res->start; 139 } else { 140 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 141 } 142 } 143 144 /* Set a default value suitable for at most 8 in and 8 out windows */ 145 if (!pci->atu_size) 146 pci->atu_size = SZ_4K; 147 148 /* eDMA region can be mapped to a custom base address */ 149 if (!pci->edma.reg_base) { 150 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 151 if (res) { 152 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 153 if (IS_ERR(pci->edma.reg_base)) 154 return PTR_ERR(pci->edma.reg_base); 155 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 156 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 157 } 158 } 159 160 /* LLDD is supposed to manually switch the clocks and resets state */ 161 if (dw_pcie_cap_is(pci, REQ_RES)) { 162 ret = dw_pcie_get_clocks(pci); 163 if (ret) 164 return ret; 165 166 ret = dw_pcie_get_resets(pci); 167 if (ret) 168 return ret; 169 } 170 171 if (pci->max_link_speed < 1) 172 pci->max_link_speed = of_pci_get_max_link_speed(np); 173 174 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 175 176 if (of_property_read_bool(np, "snps,enable-cdm-check")) 177 dw_pcie_cap_set(pci, CDM_CHECK); 178 179 return 0; 180 } 181 182 void dw_pcie_version_detect(struct dw_pcie *pci) 183 { 184 u32 ver; 185 186 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 187 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 188 if (!ver) 189 return; 190 191 if (pci->version && pci->version != ver) 192 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 193 pci->version, ver); 194 else 195 pci->version = ver; 196 197 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 198 199 if (pci->type && pci->type != ver) 200 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 201 pci->type, ver); 202 else 203 pci->type = ver; 204 } 205 206 /* 207 * These interfaces resemble the pci_find_*capability() interfaces, but these 208 * are for configuring host controllers, which are bridges *to* PCI devices but 209 * are not PCI devices themselves. 210 */ 211 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, 212 u8 cap) 213 { 214 u8 cap_id, next_cap_ptr; 215 u16 reg; 216 217 if (!cap_ptr) 218 return 0; 219 220 reg = dw_pcie_readw_dbi(pci, cap_ptr); 221 cap_id = (reg & 0x00ff); 222 223 if (cap_id > PCI_CAP_ID_MAX) 224 return 0; 225 226 if (cap_id == cap) 227 return cap_ptr; 228 229 next_cap_ptr = (reg & 0xff00) >> 8; 230 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 231 } 232 233 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 234 { 235 u8 next_cap_ptr; 236 u16 reg; 237 238 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); 239 next_cap_ptr = (reg & 0x00ff); 240 241 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 242 } 243 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 244 245 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, 246 u8 cap) 247 { 248 u32 header; 249 int ttl; 250 int pos = PCI_CFG_SPACE_SIZE; 251 252 /* minimum 8 bytes per capability */ 253 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 254 255 if (start) 256 pos = start; 257 258 header = dw_pcie_readl_dbi(pci, pos); 259 /* 260 * If we have no capabilities, this is indicated by cap ID, 261 * cap version and next pointer all being 0. 262 */ 263 if (header == 0) 264 return 0; 265 266 while (ttl-- > 0) { 267 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 268 return pos; 269 270 pos = PCI_EXT_CAP_NEXT(header); 271 if (pos < PCI_CFG_SPACE_SIZE) 272 break; 273 274 header = dw_pcie_readl_dbi(pci, pos); 275 } 276 277 return 0; 278 } 279 280 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 281 { 282 return dw_pcie_find_next_ext_capability(pci, 0, cap); 283 } 284 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 285 286 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 287 { 288 if (!IS_ALIGNED((uintptr_t)addr, size)) { 289 *val = 0; 290 return PCIBIOS_BAD_REGISTER_NUMBER; 291 } 292 293 if (size == 4) { 294 *val = readl(addr); 295 } else if (size == 2) { 296 *val = readw(addr); 297 } else if (size == 1) { 298 *val = readb(addr); 299 } else { 300 *val = 0; 301 return PCIBIOS_BAD_REGISTER_NUMBER; 302 } 303 304 return PCIBIOS_SUCCESSFUL; 305 } 306 EXPORT_SYMBOL_GPL(dw_pcie_read); 307 308 int dw_pcie_write(void __iomem *addr, int size, u32 val) 309 { 310 if (!IS_ALIGNED((uintptr_t)addr, size)) 311 return PCIBIOS_BAD_REGISTER_NUMBER; 312 313 if (size == 4) 314 writel(val, addr); 315 else if (size == 2) 316 writew(val, addr); 317 else if (size == 1) 318 writeb(val, addr); 319 else 320 return PCIBIOS_BAD_REGISTER_NUMBER; 321 322 return PCIBIOS_SUCCESSFUL; 323 } 324 EXPORT_SYMBOL_GPL(dw_pcie_write); 325 326 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 327 { 328 int ret; 329 u32 val; 330 331 if (pci->ops && pci->ops->read_dbi) 332 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 333 334 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 335 if (ret) 336 dev_err(pci->dev, "Read DBI address failed\n"); 337 338 return val; 339 } 340 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 341 342 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 343 { 344 int ret; 345 346 if (pci->ops && pci->ops->write_dbi) { 347 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 348 return; 349 } 350 351 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 352 if (ret) 353 dev_err(pci->dev, "Write DBI address failed\n"); 354 } 355 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 356 357 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 358 { 359 int ret; 360 361 if (pci->ops && pci->ops->write_dbi2) { 362 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 363 return; 364 } 365 366 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 367 if (ret) 368 dev_err(pci->dev, "write DBI address failed\n"); 369 } 370 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 371 372 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 373 u32 index) 374 { 375 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 376 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 377 378 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 379 return pci->atu_base; 380 } 381 382 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 383 { 384 void __iomem *base; 385 int ret; 386 u32 val; 387 388 base = dw_pcie_select_atu(pci, dir, index); 389 390 if (pci->ops && pci->ops->read_dbi) 391 return pci->ops->read_dbi(pci, base, reg, 4); 392 393 ret = dw_pcie_read(base + reg, 4, &val); 394 if (ret) 395 dev_err(pci->dev, "Read ATU address failed\n"); 396 397 return val; 398 } 399 400 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 401 u32 reg, u32 val) 402 { 403 void __iomem *base; 404 int ret; 405 406 base = dw_pcie_select_atu(pci, dir, index); 407 408 if (pci->ops && pci->ops->write_dbi) { 409 pci->ops->write_dbi(pci, base, reg, 4, val); 410 return; 411 } 412 413 ret = dw_pcie_write(base + reg, 4, val); 414 if (ret) 415 dev_err(pci->dev, "Write ATU address failed\n"); 416 } 417 418 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 419 { 420 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 421 } 422 423 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 424 u32 val) 425 { 426 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 427 } 428 429 static inline u32 dw_pcie_enable_ecrc(u32 val) 430 { 431 /* 432 * DesignWare core version 4.90A has a design issue where the 'TD' 433 * bit in the Control register-1 of the ATU outbound region acts 434 * like an override for the ECRC setting, i.e., the presence of TLP 435 * Digest (ECRC) in the outgoing TLPs is solely determined by this 436 * bit. This is contrary to the PCIe spec which says that the 437 * enablement of the ECRC is solely determined by the AER 438 * registers. 439 * 440 * Because of this, even when the ECRC is enabled through AER 441 * registers, the transactions going through ATU won't have TLP 442 * Digest as there is no way the PCI core AER code could program 443 * the TD bit which is specific to the DesignWare core. 444 * 445 * The best way to handle this scenario is to program the TD bit 446 * always. It affects only the traffic from root port to downstream 447 * devices. 448 * 449 * At this point, 450 * When ECRC is enabled in AER registers, everything works normally 451 * When ECRC is NOT enabled in AER registers, then, 452 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 453 * even through it is not required. Since downstream 454 * TLPs are mostly for configuration accesses and BAR 455 * accesses, they are not in critical path and won't 456 * have much negative effect on the performance. 457 * on End Point:- TLP Digest is received for some/all the packets coming 458 * from the root port. TLP Digest is ignored because, 459 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 460 * "TLP Digest Rules", when an endpoint receives TLP 461 * Digest when its ECRC check functionality is disabled 462 * in AER registers, received TLP Digest is just ignored. 463 * Since there is no issue or error reported either side, best way to 464 * handle the scenario is to program TD bit by default. 465 */ 466 467 return val | PCIE_ATU_TD; 468 } 469 470 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 471 const struct dw_pcie_ob_atu_cfg *atu) 472 { 473 u64 cpu_addr = atu->cpu_addr; 474 u32 retries, val; 475 u64 limit_addr; 476 477 if (pci->ops && pci->ops->cpu_addr_fixup) 478 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); 479 480 limit_addr = cpu_addr + atu->size - 1; 481 482 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || 483 !IS_ALIGNED(cpu_addr, pci->region_align) || 484 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 485 return -EINVAL; 486 } 487 488 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, 489 lower_32_bits(cpu_addr)); 490 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, 491 upper_32_bits(cpu_addr)); 492 493 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, 494 lower_32_bits(limit_addr)); 495 if (dw_pcie_ver_is_ge(pci, 460A)) 496 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, 497 upper_32_bits(limit_addr)); 498 499 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, 500 lower_32_bits(atu->pci_addr)); 501 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, 502 upper_32_bits(atu->pci_addr)); 503 504 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); 505 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && 506 dw_pcie_ver_is_ge(pci, 460A)) 507 val |= PCIE_ATU_INCREASE_REGION_SIZE; 508 if (dw_pcie_ver_is(pci, 490A)) 509 val = dw_pcie_enable_ecrc(val); 510 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 511 512 val = PCIE_ATU_ENABLE; 513 if (atu->type == PCIE_ATU_TYPE_MSG) { 514 /* The data-less messages only for now */ 515 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; 516 } 517 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); 518 519 /* 520 * Make sure ATU enable takes effect before any subsequent config 521 * and I/O accesses. 522 */ 523 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 524 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); 525 if (val & PCIE_ATU_ENABLE) 526 return 0; 527 528 mdelay(LINK_WAIT_IATU); 529 } 530 531 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 532 533 return -ETIMEDOUT; 534 } 535 536 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 537 { 538 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 539 } 540 541 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 542 u32 val) 543 { 544 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 545 } 546 547 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 548 u64 cpu_addr, u64 pci_addr, u64 size) 549 { 550 u64 limit_addr = pci_addr + size - 1; 551 u32 retries, val; 552 553 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 554 !IS_ALIGNED(cpu_addr, pci->region_align) || 555 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 556 return -EINVAL; 557 } 558 559 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 560 lower_32_bits(pci_addr)); 561 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 562 upper_32_bits(pci_addr)); 563 564 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 565 lower_32_bits(limit_addr)); 566 if (dw_pcie_ver_is_ge(pci, 460A)) 567 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 568 upper_32_bits(limit_addr)); 569 570 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 571 lower_32_bits(cpu_addr)); 572 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 573 upper_32_bits(cpu_addr)); 574 575 val = type; 576 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 577 dw_pcie_ver_is_ge(pci, 460A)) 578 val |= PCIE_ATU_INCREASE_REGION_SIZE; 579 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 580 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 581 582 /* 583 * Make sure ATU enable takes effect before any subsequent config 584 * and I/O accesses. 585 */ 586 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 587 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 588 if (val & PCIE_ATU_ENABLE) 589 return 0; 590 591 mdelay(LINK_WAIT_IATU); 592 } 593 594 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 595 596 return -ETIMEDOUT; 597 } 598 599 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 600 int type, u64 cpu_addr, u8 bar, size_t size) 601 { 602 u32 retries, val; 603 604 if (!IS_ALIGNED(cpu_addr, pci->region_align) || 605 !IS_ALIGNED(cpu_addr, size)) 606 return -EINVAL; 607 608 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 609 lower_32_bits(cpu_addr)); 610 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 611 upper_32_bits(cpu_addr)); 612 613 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 614 PCIE_ATU_FUNC_NUM(func_no)); 615 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 616 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 617 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 618 619 /* 620 * Make sure ATU enable takes effect before any subsequent config 621 * and I/O accesses. 622 */ 623 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 624 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 625 if (val & PCIE_ATU_ENABLE) 626 return 0; 627 628 mdelay(LINK_WAIT_IATU); 629 } 630 631 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 632 633 return -ETIMEDOUT; 634 } 635 636 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 637 { 638 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 639 } 640 641 int dw_pcie_wait_for_link(struct dw_pcie *pci) 642 { 643 u32 offset, val; 644 int retries; 645 646 /* Check if the link is up or not */ 647 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 648 if (dw_pcie_link_up(pci)) 649 break; 650 651 msleep(LINK_WAIT_SLEEP_MS); 652 } 653 654 if (retries >= LINK_WAIT_MAX_RETRIES) { 655 dev_info(pci->dev, "Phy link never came up\n"); 656 return -ETIMEDOUT; 657 } 658 659 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 660 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 661 662 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 663 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 664 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 665 666 return 0; 667 } 668 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 669 670 int dw_pcie_link_up(struct dw_pcie *pci) 671 { 672 u32 val; 673 674 if (pci->ops && pci->ops->link_up) 675 return pci->ops->link_up(pci); 676 677 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 678 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 679 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 680 } 681 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 682 683 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 684 { 685 u32 val; 686 687 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 688 val |= PORT_MLTI_UPCFG_SUPPORT; 689 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 690 } 691 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 692 693 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 694 { 695 u32 cap, ctrl2, link_speed; 696 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 697 698 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 699 700 /* 701 * Even if the platform doesn't want to limit the maximum link speed, 702 * just cache the hardware default value so that the vendor drivers can 703 * use it to do any link specific configuration. 704 */ 705 if (pci->max_link_speed < 1) { 706 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 707 return; 708 } 709 710 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 711 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 712 713 switch (pcie_link_speed[pci->max_link_speed]) { 714 case PCIE_SPEED_2_5GT: 715 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 716 break; 717 case PCIE_SPEED_5_0GT: 718 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 719 break; 720 case PCIE_SPEED_8_0GT: 721 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 722 break; 723 case PCIE_SPEED_16_0GT: 724 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 725 break; 726 default: 727 /* Use hardware capability */ 728 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 729 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 730 break; 731 } 732 733 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 734 735 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 736 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 737 738 } 739 740 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 741 { 742 u32 lnkcap, lwsc, plc; 743 u8 cap; 744 745 if (!num_lanes) 746 return; 747 748 /* Set the number of lanes */ 749 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 750 plc &= ~PORT_LINK_FAST_LINK_MODE; 751 plc &= ~PORT_LINK_MODE_MASK; 752 753 /* Set link width speed control register */ 754 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 755 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; 756 switch (num_lanes) { 757 case 1: 758 plc |= PORT_LINK_MODE_1_LANES; 759 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; 760 break; 761 case 2: 762 plc |= PORT_LINK_MODE_2_LANES; 763 lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES; 764 break; 765 case 4: 766 plc |= PORT_LINK_MODE_4_LANES; 767 lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES; 768 break; 769 case 8: 770 plc |= PORT_LINK_MODE_8_LANES; 771 lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES; 772 break; 773 default: 774 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 775 return; 776 } 777 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); 778 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); 779 780 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 781 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 782 lnkcap &= ~PCI_EXP_LNKCAP_MLW; 783 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); 784 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 785 } 786 787 void dw_pcie_iatu_detect(struct dw_pcie *pci) 788 { 789 int max_region, ob, ib; 790 u32 val, min, dir; 791 u64 max; 792 793 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 794 if (val == 0xFFFFFFFF) { 795 dw_pcie_cap_set(pci, IATU_UNROLL); 796 797 max_region = min((int)pci->atu_size / 512, 256); 798 } else { 799 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 800 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 801 802 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 803 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 804 } 805 806 for (ob = 0; ob < max_region; ob++) { 807 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 808 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 809 if (val != 0x11110000) 810 break; 811 } 812 813 for (ib = 0; ib < max_region; ib++) { 814 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 815 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 816 if (val != 0x11110000) 817 break; 818 } 819 820 if (ob) { 821 dir = PCIE_ATU_REGION_DIR_OB; 822 } else if (ib) { 823 dir = PCIE_ATU_REGION_DIR_IB; 824 } else { 825 dev_err(pci->dev, "No iATU regions found\n"); 826 return; 827 } 828 829 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 830 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 831 832 if (dw_pcie_ver_is_ge(pci, 460A)) { 833 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 834 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 835 } else { 836 max = 0; 837 } 838 839 pci->num_ob_windows = ob; 840 pci->num_ib_windows = ib; 841 pci->region_align = 1 << fls(min); 842 pci->region_limit = (max << 32) | (SZ_4G - 1); 843 844 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 845 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 846 pci->num_ob_windows, pci->num_ib_windows, 847 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 848 } 849 850 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 851 { 852 u32 val = 0; 853 int ret; 854 855 if (pci->ops && pci->ops->read_dbi) 856 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 857 858 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 859 if (ret) 860 dev_err(pci->dev, "Read DMA address failed\n"); 861 862 return val; 863 } 864 865 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 866 { 867 struct platform_device *pdev = to_platform_device(dev); 868 char name[6]; 869 int ret; 870 871 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 872 return -EINVAL; 873 874 ret = platform_get_irq_byname_optional(pdev, "dma"); 875 if (ret > 0) 876 return ret; 877 878 snprintf(name, sizeof(name), "dma%u", nr); 879 880 return platform_get_irq_byname_optional(pdev, name); 881 } 882 883 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 884 .irq_vector = dw_pcie_edma_irq_vector, 885 }; 886 887 static void dw_pcie_edma_init_data(struct dw_pcie *pci) 888 { 889 pci->edma.dev = pci->dev; 890 891 if (!pci->edma.ops) 892 pci->edma.ops = &dw_pcie_edma_ops; 893 894 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 895 } 896 897 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 898 { 899 u32 val; 900 901 /* 902 * Bail out finding the mapping format if it is already set by the glue 903 * driver. Also ensure that the edma.reg_base is pointing to a valid 904 * memory region. 905 */ 906 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 907 return pci->edma.reg_base ? 0 : -ENODEV; 908 909 /* 910 * Indirect eDMA CSRs access has been completely removed since v5.40a 911 * thus no space is now reserved for the eDMA channels viewport and 912 * former DMA CTRL register is no longer fixed to FFs. 913 */ 914 if (dw_pcie_ver_is_ge(pci, 540A)) 915 val = 0xFFFFFFFF; 916 else 917 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 918 919 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 920 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 921 } else if (val != 0xFFFFFFFF) { 922 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 923 924 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 925 } else { 926 return -ENODEV; 927 } 928 929 return 0; 930 } 931 932 static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 933 { 934 u32 val; 935 936 /* 937 * Autodetect the read/write channels count only for non-HDMA platforms. 938 * HDMA platforms with native CSR mapping doesn't support autodetect, 939 * so the glue drivers should've passed the valid count already. If not, 940 * the below sanity check will catch it. 941 */ 942 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 943 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 944 945 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 946 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 947 } 948 949 /* Sanity check the channels count if the mapping was incorrect */ 950 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 951 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 952 return -EINVAL; 953 954 return 0; 955 } 956 957 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 958 { 959 int ret; 960 961 dw_pcie_edma_init_data(pci); 962 963 ret = dw_pcie_edma_find_mf(pci); 964 if (ret) 965 return ret; 966 967 return dw_pcie_edma_find_channels(pci); 968 } 969 970 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 971 { 972 struct platform_device *pdev = to_platform_device(pci->dev); 973 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 974 char name[15]; 975 int ret; 976 977 if (pci->edma.nr_irqs == 1) 978 return 0; 979 else if (pci->edma.nr_irqs > 1) 980 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 981 982 ret = platform_get_irq_byname_optional(pdev, "dma"); 983 if (ret > 0) { 984 pci->edma.nr_irqs = 1; 985 return 0; 986 } 987 988 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 989 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 990 991 ret = platform_get_irq_byname_optional(pdev, name); 992 if (ret <= 0) 993 return -EINVAL; 994 } 995 996 return 0; 997 } 998 999 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 1000 { 1001 struct dw_edma_region *ll; 1002 dma_addr_t paddr; 1003 int i; 1004 1005 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1006 ll = &pci->edma.ll_region_wr[i]; 1007 ll->sz = DMA_LLP_MEM_SIZE; 1008 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1009 &paddr, GFP_KERNEL); 1010 if (!ll->vaddr.mem) 1011 return -ENOMEM; 1012 1013 ll->paddr = paddr; 1014 } 1015 1016 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1017 ll = &pci->edma.ll_region_rd[i]; 1018 ll->sz = DMA_LLP_MEM_SIZE; 1019 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1020 &paddr, GFP_KERNEL); 1021 if (!ll->vaddr.mem) 1022 return -ENOMEM; 1023 1024 ll->paddr = paddr; 1025 } 1026 1027 return 0; 1028 } 1029 1030 int dw_pcie_edma_detect(struct dw_pcie *pci) 1031 { 1032 int ret; 1033 1034 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1035 ret = dw_pcie_edma_find_chip(pci); 1036 if (ret) 1037 return 0; 1038 1039 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1040 ret = dw_pcie_edma_irq_verify(pci); 1041 if (ret) { 1042 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1043 return 0; 1044 } 1045 1046 ret = dw_pcie_edma_ll_alloc(pci); 1047 if (ret) { 1048 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1049 return ret; 1050 } 1051 1052 /* Don't fail if the DW eDMA driver can't find the device */ 1053 ret = dw_edma_probe(&pci->edma); 1054 if (ret && ret != -ENODEV) { 1055 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1056 return ret; 1057 } 1058 1059 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1060 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1061 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1062 1063 return 0; 1064 } 1065 1066 void dw_pcie_edma_remove(struct dw_pcie *pci) 1067 { 1068 dw_edma_remove(&pci->edma); 1069 } 1070 1071 void dw_pcie_setup(struct dw_pcie *pci) 1072 { 1073 u32 val; 1074 1075 dw_pcie_link_set_max_speed(pci); 1076 1077 /* Configure Gen1 N_FTS */ 1078 if (pci->n_fts[0]) { 1079 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 1080 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 1081 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 1082 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 1083 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1084 } 1085 1086 /* Configure Gen2+ N_FTS */ 1087 if (pci->n_fts[1]) { 1088 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1089 val &= ~PORT_LOGIC_N_FTS_MASK; 1090 val |= pci->n_fts[1]; 1091 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1092 } 1093 1094 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1095 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1096 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1097 PCIE_PL_CHK_REG_CHK_REG_START; 1098 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1099 } 1100 1101 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1102 val &= ~PORT_LINK_FAST_LINK_MODE; 1103 val |= PORT_LINK_DLL_LINK_EN; 1104 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1105 1106 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1107 } 1108