1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/pcie-dwc.h> 21 #include <linux/platform_device.h> 22 #include <linux/sizes.h> 23 #include <linux/types.h> 24 25 #include "../pci-host-common.h" 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 30 [DW_PCIE_DBI_CLK] = "dbi", 31 [DW_PCIE_MSTR_CLK] = "mstr", 32 [DW_PCIE_SLV_CLK] = "slv", 33 }; 34 35 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 36 [DW_PCIE_PIPE_CLK] = "pipe", 37 [DW_PCIE_CORE_CLK] = "core", 38 [DW_PCIE_AUX_CLK] = "aux", 39 [DW_PCIE_REF_CLK] = "ref", 40 }; 41 42 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 43 [DW_PCIE_DBI_RST] = "dbi", 44 [DW_PCIE_MSTR_RST] = "mstr", 45 [DW_PCIE_SLV_RST] = "slv", 46 }; 47 48 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 49 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 50 [DW_PCIE_STICKY_RST] = "sticky", 51 [DW_PCIE_CORE_RST] = "core", 52 [DW_PCIE_PIPE_RST] = "pipe", 53 [DW_PCIE_PHY_RST] = "phy", 54 [DW_PCIE_HOT_RST] = "hot", 55 [DW_PCIE_PWR_RST] = "pwr", 56 }; 57 58 static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { 59 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ 60 .vsec_id = 0x03, .vsec_rev = 0x1 }, 61 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ 62 .vsec_id = 0x04, .vsec_rev = 0x1 }, 63 { } 64 }; 65 66 static int dw_pcie_get_clocks(struct dw_pcie *pci) 67 { 68 int i, ret; 69 70 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 71 pci->app_clks[i].id = dw_pcie_app_clks[i]; 72 73 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 74 pci->core_clks[i].id = dw_pcie_core_clks[i]; 75 76 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 77 pci->app_clks); 78 if (ret) 79 return ret; 80 81 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 82 pci->core_clks); 83 } 84 85 static int dw_pcie_get_resets(struct dw_pcie *pci) 86 { 87 int i, ret; 88 89 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 90 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 91 92 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 93 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 94 95 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 96 DW_PCIE_NUM_APP_RSTS, 97 pci->app_rsts); 98 if (ret) 99 return ret; 100 101 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 102 DW_PCIE_NUM_CORE_RSTS, 103 pci->core_rsts); 104 if (ret) 105 return ret; 106 107 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 108 if (IS_ERR(pci->pe_rst)) 109 return PTR_ERR(pci->pe_rst); 110 111 return 0; 112 } 113 114 int dw_pcie_get_resources(struct dw_pcie *pci) 115 { 116 struct platform_device *pdev = to_platform_device(pci->dev); 117 struct device_node *np = dev_of_node(pci->dev); 118 struct resource *res; 119 int ret; 120 121 if (!pci->dbi_base) { 122 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 123 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 124 if (IS_ERR(pci->dbi_base)) 125 return PTR_ERR(pci->dbi_base); 126 pci->dbi_phys_addr = res->start; 127 } 128 129 /* DBI2 is mainly useful for the endpoint controller */ 130 if (!pci->dbi_base2) { 131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 132 if (res) { 133 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 134 if (IS_ERR(pci->dbi_base2)) 135 return PTR_ERR(pci->dbi_base2); 136 } else { 137 pci->dbi_base2 = pci->dbi_base + SZ_4K; 138 } 139 } 140 141 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 142 if (!pci->atu_base) { 143 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 144 if (res) { 145 pci->atu_size = resource_size(res); 146 pci->atu_base = devm_ioremap_resource(pci->dev, res); 147 if (IS_ERR(pci->atu_base)) 148 return PTR_ERR(pci->atu_base); 149 pci->atu_phys_addr = res->start; 150 } else { 151 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 152 } 153 } 154 155 /* Set a default value suitable for at most 8 in and 8 out windows */ 156 if (!pci->atu_size) 157 pci->atu_size = SZ_4K; 158 159 /* eDMA region can be mapped to a custom base address */ 160 if (!pci->edma.reg_base) { 161 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 162 if (res) { 163 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 164 if (IS_ERR(pci->edma.reg_base)) 165 return PTR_ERR(pci->edma.reg_base); 166 pci->edma_reg_phys = res->start; 167 pci->edma_reg_size = resource_size(res); 168 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 169 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 170 pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET; 171 pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET; 172 } 173 } 174 175 /* ELBI is an optional resource */ 176 if (!pci->elbi_base) { 177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 178 if (res) { 179 pci->elbi_base = devm_ioremap_resource(pci->dev, res); 180 if (IS_ERR(pci->elbi_base)) 181 return PTR_ERR(pci->elbi_base); 182 } 183 } 184 185 /* LLDD is supposed to manually switch the clocks and resets state */ 186 if (dw_pcie_cap_is(pci, REQ_RES)) { 187 ret = dw_pcie_get_clocks(pci); 188 if (ret) 189 return ret; 190 191 ret = dw_pcie_get_resets(pci); 192 if (ret) 193 return ret; 194 } 195 196 if (pci->max_link_speed < 1) 197 pci->max_link_speed = of_pci_get_max_link_speed(np); 198 199 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 200 201 if (of_property_read_bool(np, "snps,enable-cdm-check")) 202 dw_pcie_cap_set(pci, CDM_CHECK); 203 204 return 0; 205 } 206 207 void dw_pcie_version_detect(struct dw_pcie *pci) 208 { 209 u32 ver; 210 211 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 212 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 213 if (!ver) 214 return; 215 216 if (pci->version && pci->version != ver) 217 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 218 pci->version, ver); 219 else 220 pci->version = ver; 221 222 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 223 224 if (pci->type && pci->type != ver) 225 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 226 pci->type, ver); 227 else 228 pci->type = ver; 229 } 230 231 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 232 { 233 return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 234 NULL, pci); 235 } 236 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 237 238 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 239 { 240 return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, NULL, pci); 241 } 242 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 243 244 void dw_pcie_remove_capability(struct dw_pcie *pci, u8 cap) 245 { 246 u8 cap_pos, pre_pos, next_pos; 247 u16 reg; 248 249 cap_pos = PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 250 &pre_pos, pci); 251 if (!cap_pos) 252 return; 253 254 reg = dw_pcie_readw_dbi(pci, cap_pos); 255 next_pos = (reg & 0xff00) >> 8; 256 257 dw_pcie_dbi_ro_wr_en(pci); 258 if (pre_pos == PCI_CAPABILITY_LIST) 259 dw_pcie_writeb_dbi(pci, PCI_CAPABILITY_LIST, next_pos); 260 else 261 dw_pcie_writeb_dbi(pci, pre_pos + 1, next_pos); 262 dw_pcie_dbi_ro_wr_dis(pci); 263 } 264 EXPORT_SYMBOL_GPL(dw_pcie_remove_capability); 265 266 void dw_pcie_remove_ext_capability(struct dw_pcie *pci, u8 cap) 267 { 268 int cap_pos, next_pos, pre_pos; 269 u32 pre_header, header; 270 271 cap_pos = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, &pre_pos, pci); 272 if (!cap_pos) 273 return; 274 275 header = dw_pcie_readl_dbi(pci, cap_pos); 276 277 /* 278 * If the first cap at offset PCI_CFG_SPACE_SIZE is removed, 279 * only set its capid to zero as it cannot be skipped. 280 */ 281 if (cap_pos == PCI_CFG_SPACE_SIZE) { 282 dw_pcie_dbi_ro_wr_en(pci); 283 dw_pcie_writel_dbi(pci, cap_pos, header & 0xffff0000); 284 dw_pcie_dbi_ro_wr_dis(pci); 285 return; 286 } 287 288 pre_header = dw_pcie_readl_dbi(pci, pre_pos); 289 next_pos = PCI_EXT_CAP_NEXT(header); 290 291 dw_pcie_dbi_ro_wr_en(pci); 292 dw_pcie_writel_dbi(pci, pre_pos, 293 (pre_header & 0xfffff) | (next_pos << 20)); 294 dw_pcie_dbi_ro_wr_dis(pci); 295 } 296 EXPORT_SYMBOL_GPL(dw_pcie_remove_ext_capability); 297 298 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, 299 u16 vsec_id) 300 { 301 u16 vsec = 0; 302 u32 header; 303 304 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) 305 return 0; 306 307 while ((vsec = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, 308 PCI_EXT_CAP_ID_VNDR, NULL, pci))) { 309 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 310 if (PCI_VNDR_HEADER_ID(header) == vsec_id) 311 return vsec; 312 } 313 314 return 0; 315 } 316 317 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, 318 const struct dwc_pcie_vsec_id *vsec_ids) 319 { 320 const struct dwc_pcie_vsec_id *vid; 321 u16 vsec; 322 u32 header; 323 324 for (vid = vsec_ids; vid->vendor_id; vid++) { 325 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, 326 vid->vsec_id); 327 if (vsec) { 328 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 329 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) 330 return vsec; 331 } 332 } 333 334 return 0; 335 } 336 337 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) 338 { 339 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids); 340 } 341 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); 342 343 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) 344 { 345 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); 346 } 347 EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); 348 349 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 350 { 351 if (!IS_ALIGNED((uintptr_t)addr, size)) { 352 *val = 0; 353 return PCIBIOS_BAD_REGISTER_NUMBER; 354 } 355 356 if (size == 4) { 357 *val = readl(addr); 358 } else if (size == 2) { 359 *val = readw(addr); 360 } else if (size == 1) { 361 *val = readb(addr); 362 } else { 363 *val = 0; 364 return PCIBIOS_BAD_REGISTER_NUMBER; 365 } 366 367 return PCIBIOS_SUCCESSFUL; 368 } 369 EXPORT_SYMBOL_GPL(dw_pcie_read); 370 371 int dw_pcie_write(void __iomem *addr, int size, u32 val) 372 { 373 if (!IS_ALIGNED((uintptr_t)addr, size)) 374 return PCIBIOS_BAD_REGISTER_NUMBER; 375 376 if (size == 4) 377 writel(val, addr); 378 else if (size == 2) 379 writew(val, addr); 380 else if (size == 1) 381 writeb(val, addr); 382 else 383 return PCIBIOS_BAD_REGISTER_NUMBER; 384 385 return PCIBIOS_SUCCESSFUL; 386 } 387 EXPORT_SYMBOL_GPL(dw_pcie_write); 388 389 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 390 { 391 int ret; 392 u32 val; 393 394 if (pci->ops && pci->ops->read_dbi) 395 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 396 397 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 398 if (ret) 399 dev_err(pci->dev, "Read DBI address failed\n"); 400 401 return val; 402 } 403 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 404 405 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 406 { 407 int ret; 408 409 if (pci->ops && pci->ops->write_dbi) { 410 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 411 return; 412 } 413 414 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 415 if (ret) 416 dev_err(pci->dev, "Write DBI address failed\n"); 417 } 418 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 419 420 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 421 { 422 int ret; 423 424 if (pci->ops && pci->ops->write_dbi2) { 425 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 426 return; 427 } 428 429 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 430 if (ret) 431 dev_err(pci->dev, "write DBI address failed\n"); 432 } 433 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 434 435 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 436 u32 index) 437 { 438 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 439 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 440 441 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 442 return pci->atu_base; 443 } 444 445 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 446 { 447 void __iomem *base; 448 int ret; 449 u32 val; 450 451 base = dw_pcie_select_atu(pci, dir, index); 452 453 if (pci->ops && pci->ops->read_dbi) 454 return pci->ops->read_dbi(pci, base, reg, 4); 455 456 ret = dw_pcie_read(base + reg, 4, &val); 457 if (ret) 458 dev_err(pci->dev, "Read ATU address failed\n"); 459 460 return val; 461 } 462 463 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 464 u32 reg, u32 val) 465 { 466 void __iomem *base; 467 int ret; 468 469 base = dw_pcie_select_atu(pci, dir, index); 470 471 if (pci->ops && pci->ops->write_dbi) { 472 pci->ops->write_dbi(pci, base, reg, 4, val); 473 return; 474 } 475 476 ret = dw_pcie_write(base + reg, 4, val); 477 if (ret) 478 dev_err(pci->dev, "Write ATU address failed\n"); 479 } 480 481 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 482 { 483 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 484 } 485 486 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 487 u32 val) 488 { 489 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 490 } 491 492 static inline u32 dw_pcie_enable_ecrc(u32 val) 493 { 494 /* 495 * DesignWare core versions prior to 5.10A have a design issue where the 496 * 'TD' bit in the Control register-1 of the ATU outbound region acts 497 * like an override for the ECRC setting, i.e., the presence of TLP 498 * Digest (ECRC) in the outgoing TLPs is solely determined by this 499 * bit. This is contrary to the PCIe spec which says that the 500 * enablement of the ECRC is solely determined by the AER 501 * registers. 502 * 503 * Because of this, even when the ECRC is enabled through AER 504 * registers, the transactions going through ATU won't have TLP 505 * Digest as there is no way the PCI core AER code could program 506 * the TD bit which is specific to the DesignWare core. 507 * 508 * The best way to handle this scenario is to program the TD bit 509 * always. It affects only the traffic from root port to downstream 510 * devices. 511 * 512 * At this point, 513 * When ECRC is enabled in AER registers, everything works normally 514 * When ECRC is NOT enabled in AER registers, then, 515 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 516 * even through it is not required. Since downstream 517 * TLPs are mostly for configuration accesses and BAR 518 * accesses, they are not in critical path and won't 519 * have much negative effect on the performance. 520 * on End Point:- TLP Digest is received for some/all the packets coming 521 * from the root port. TLP Digest is ignored because, 522 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 523 * "TLP Digest Rules", when an endpoint receives TLP 524 * Digest when its ECRC check functionality is disabled 525 * in AER registers, received TLP Digest is just ignored. 526 * Since there is no issue or error reported either side, best way to 527 * handle the scenario is to program TD bit by default. 528 */ 529 530 return val | PCIE_ATU_TD; 531 } 532 533 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 534 const struct dw_pcie_ob_atu_cfg *atu) 535 { 536 u64 parent_bus_addr = atu->parent_bus_addr; 537 u32 retries, val; 538 u64 limit_addr; 539 540 if (atu->index >= pci->num_ob_windows) 541 return -ENOSPC; 542 543 limit_addr = parent_bus_addr + atu->size - 1; 544 545 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || 546 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 547 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 548 return -EINVAL; 549 } 550 551 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, 552 lower_32_bits(parent_bus_addr)); 553 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, 554 upper_32_bits(parent_bus_addr)); 555 556 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, 557 lower_32_bits(limit_addr)); 558 if (dw_pcie_ver_is_ge(pci, 460A)) 559 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, 560 upper_32_bits(limit_addr)); 561 562 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, 563 lower_32_bits(atu->pci_addr)); 564 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, 565 upper_32_bits(atu->pci_addr)); 566 567 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); 568 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && 569 dw_pcie_ver_is_ge(pci, 460A)) 570 val |= PCIE_ATU_INCREASE_REGION_SIZE; 571 if (!dw_pcie_ver_is_ge(pci, 510A)) 572 val = dw_pcie_enable_ecrc(val); 573 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 574 575 val = PCIE_ATU_ENABLE | atu->ctrl2; 576 if (atu->type == PCIE_TLP_TYPE_MSG) { 577 /* The data-less messages only for now */ 578 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; 579 } 580 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); 581 582 /* 583 * Make sure ATU enable takes effect before any subsequent config 584 * and I/O accesses. 585 */ 586 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 587 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); 588 if (val & PCIE_ATU_ENABLE) 589 return 0; 590 591 mdelay(LINK_WAIT_IATU); 592 } 593 594 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 595 596 return -ETIMEDOUT; 597 } 598 599 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 600 { 601 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 602 } 603 604 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 605 u32 val) 606 { 607 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 608 } 609 610 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 611 u64 parent_bus_addr, u64 pci_addr, u64 size) 612 { 613 u64 limit_addr = pci_addr + size - 1; 614 u32 retries, val; 615 616 if (index >= pci->num_ib_windows) 617 return -ENOSPC; 618 619 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 620 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 621 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 622 return -EINVAL; 623 } 624 625 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 626 lower_32_bits(pci_addr)); 627 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 628 upper_32_bits(pci_addr)); 629 630 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 631 lower_32_bits(limit_addr)); 632 if (dw_pcie_ver_is_ge(pci, 460A)) 633 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 634 upper_32_bits(limit_addr)); 635 636 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 637 lower_32_bits(parent_bus_addr)); 638 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 639 upper_32_bits(parent_bus_addr)); 640 641 val = type; 642 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 643 dw_pcie_ver_is_ge(pci, 460A)) 644 val |= PCIE_ATU_INCREASE_REGION_SIZE; 645 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 646 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 647 648 /* 649 * Make sure ATU enable takes effect before any subsequent config 650 * and I/O accesses. 651 */ 652 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 653 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 654 if (val & PCIE_ATU_ENABLE) 655 return 0; 656 657 mdelay(LINK_WAIT_IATU); 658 } 659 660 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 661 662 return -ETIMEDOUT; 663 } 664 665 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 666 int type, u64 parent_bus_addr, u8 bar, size_t size) 667 { 668 u32 retries, val; 669 670 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) || 671 !IS_ALIGNED(parent_bus_addr, size)) 672 return -EINVAL; 673 674 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 675 lower_32_bits(parent_bus_addr)); 676 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 677 upper_32_bits(parent_bus_addr)); 678 679 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 680 PCIE_ATU_FUNC_NUM(func_no)); 681 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 682 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 683 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 684 685 /* 686 * Make sure ATU enable takes effect before any subsequent config 687 * and I/O accesses. 688 */ 689 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 690 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 691 if (val & PCIE_ATU_ENABLE) 692 return 0; 693 694 mdelay(LINK_WAIT_IATU); 695 } 696 697 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 698 699 return -ETIMEDOUT; 700 } 701 702 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 703 { 704 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 705 } 706 707 const char *dw_pcie_ltssm_status_string(enum dw_pcie_ltssm ltssm) 708 { 709 const char *str; 710 711 switch (ltssm) { 712 #define DW_PCIE_LTSSM_NAME(n) case n: str = #n; break 713 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_QUIET); 714 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_ACT); 715 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_ACTIVE); 716 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_COMPLIANCE); 717 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_CONFIG); 718 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_PRE_DETECT_QUIET); 719 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_WAIT); 720 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_START); 721 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_ACEPT); 722 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_WAI); 723 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_ACEPT); 724 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_COMPLETE); 725 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_IDLE); 726 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_LOCK); 727 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_SPEED); 728 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_RCVRCFG); 729 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_IDLE); 730 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0); 731 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0S); 732 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L123_SEND_EIDLE); 733 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_IDLE); 734 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_IDLE); 735 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_WAKE); 736 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_ENTRY); 737 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_IDLE); 738 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED); 739 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ENTRY); 740 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ACTIVE); 741 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT); 742 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT); 743 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET_ENTRY); 744 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET); 745 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ0); 746 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1); 747 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2); 748 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3); 749 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_1); 750 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_2); 751 default: 752 str = "DW_PCIE_LTSSM_UNKNOWN"; 753 break; 754 } 755 756 return str + strlen("DW_PCIE_LTSSM_"); 757 } 758 759 /** 760 * dw_pcie_wait_for_link - Wait for the PCIe link to be up 761 * @pci: DWC instance 762 * 763 * Returns: 0 if link is up, -ENODEV if device is not found, -EIO if the device 764 * is found but not active and -ETIMEDOUT if the link fails to come up for other 765 * reasons. 766 */ 767 int dw_pcie_wait_for_link(struct dw_pcie *pci) 768 { 769 u32 offset, val, ltssm; 770 int retries; 771 772 /* Check if the link is up or not */ 773 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { 774 if (dw_pcie_link_up(pci)) 775 break; 776 777 msleep(PCIE_LINK_WAIT_SLEEP_MS); 778 } 779 780 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { 781 /* 782 * If the link is in Detect.Quiet or Detect.Active state, it 783 * indicates that no device is detected. 784 */ 785 ltssm = dw_pcie_get_ltssm(pci); 786 if (ltssm == DW_PCIE_LTSSM_DETECT_QUIET || 787 ltssm == DW_PCIE_LTSSM_DETECT_ACT) { 788 dev_info(pci->dev, "Device not found\n"); 789 return -ENODEV; 790 791 /* 792 * If the link is in POLL.{Active/Compliance} state, then the 793 * device is found to be connected to the bus, but it is not 794 * active i.e., the device firmware might not yet initialized. 795 */ 796 } else if (ltssm == DW_PCIE_LTSSM_POLL_ACTIVE || 797 ltssm == DW_PCIE_LTSSM_POLL_COMPLIANCE) { 798 dev_info(pci->dev, "Device found, but not active\n"); 799 return -EIO; 800 } 801 802 dev_err(pci->dev, "Link failed to come up. LTSSM: %s\n", 803 dw_pcie_ltssm_status_string(ltssm)); 804 return -ETIMEDOUT; 805 } 806 807 pci_host_common_link_train_delay(pci->max_link_speed); 808 809 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 810 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 811 812 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 813 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 814 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 815 816 return 0; 817 } 818 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 819 820 bool dw_pcie_link_up(struct dw_pcie *pci) 821 { 822 u32 val; 823 824 if (pci->ops && pci->ops->link_up) 825 return pci->ops->link_up(pci); 826 827 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 828 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 829 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 830 } 831 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 832 833 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 834 { 835 u32 val; 836 837 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 838 val |= PORT_MLTI_UPCFG_SUPPORT; 839 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 840 } 841 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 842 843 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 844 { 845 u32 cap, ctrl2, link_speed; 846 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 847 848 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 849 850 /* 851 * Even if the platform doesn't want to limit the maximum link speed, 852 * just cache the hardware default value so that the vendor drivers can 853 * use it to do any link specific configuration. 854 */ 855 if (pci->max_link_speed < 1) { 856 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 857 return; 858 } 859 860 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 861 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 862 863 switch (pcie_get_link_speed(pci->max_link_speed)) { 864 case PCIE_SPEED_2_5GT: 865 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 866 break; 867 case PCIE_SPEED_5_0GT: 868 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 869 break; 870 case PCIE_SPEED_8_0GT: 871 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 872 break; 873 case PCIE_SPEED_16_0GT: 874 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 875 break; 876 default: 877 /* Use hardware capability */ 878 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 879 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 880 break; 881 } 882 883 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 884 885 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 886 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 887 888 } 889 890 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) 891 { 892 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 893 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 894 895 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); 896 } 897 898 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 899 { 900 u32 lnkcap, lwsc, plc; 901 u8 cap; 902 903 if (!num_lanes) 904 return; 905 906 /* Set the number of lanes */ 907 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 908 plc &= ~PORT_LINK_FAST_LINK_MODE; 909 plc &= ~PORT_LINK_MODE_MASK; 910 911 /* Set link width speed control register */ 912 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 913 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; 914 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; 915 switch (num_lanes) { 916 case 1: 917 plc |= PORT_LINK_MODE_1_LANES; 918 break; 919 case 2: 920 plc |= PORT_LINK_MODE_2_LANES; 921 break; 922 case 4: 923 plc |= PORT_LINK_MODE_4_LANES; 924 break; 925 case 8: 926 plc |= PORT_LINK_MODE_8_LANES; 927 break; 928 case 16: 929 plc |= PORT_LINK_MODE_16_LANES; 930 break; 931 default: 932 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 933 return; 934 } 935 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); 936 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); 937 938 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 939 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 940 FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); 941 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 942 } 943 944 void dw_pcie_iatu_detect(struct dw_pcie *pci) 945 { 946 int max_region, ob, ib; 947 u32 val, min, dir; 948 u64 max; 949 950 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 951 if (val == 0xFFFFFFFF) { 952 dw_pcie_cap_set(pci, IATU_UNROLL); 953 954 max_region = min((int)pci->atu_size / 512, 256); 955 } else { 956 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 957 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 958 959 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 960 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 961 } 962 963 for (ob = 0; ob < max_region; ob++) { 964 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 965 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 966 if (val != 0x11110000) 967 break; 968 } 969 970 for (ib = 0; ib < max_region; ib++) { 971 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 972 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 973 if (val != 0x11110000) 974 break; 975 } 976 977 if (ob) { 978 dir = PCIE_ATU_REGION_DIR_OB; 979 } else if (ib) { 980 dir = PCIE_ATU_REGION_DIR_IB; 981 } else { 982 dev_err(pci->dev, "No iATU regions found\n"); 983 return; 984 } 985 986 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 987 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 988 989 if (dw_pcie_ver_is_ge(pci, 460A)) { 990 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 991 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 992 } else { 993 max = 0; 994 } 995 996 pci->num_ob_windows = ob; 997 pci->num_ib_windows = ib; 998 pci->region_align = 1 << fls(min); 999 pci->region_limit = (max << 32) | (SZ_4G - 1); 1000 1001 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 1002 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 1003 pci->num_ob_windows, pci->num_ib_windows, 1004 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 1005 } 1006 1007 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 1008 { 1009 u32 val = 0; 1010 int ret; 1011 1012 if (pci->ops && pci->ops->read_dbi) 1013 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 1014 1015 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 1016 if (ret) 1017 dev_err(pci->dev, "Read DMA address failed\n"); 1018 1019 return val; 1020 } 1021 1022 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 1023 { 1024 struct platform_device *pdev = to_platform_device(dev); 1025 char name[6]; 1026 int ret; 1027 1028 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 1029 return -EINVAL; 1030 1031 ret = platform_get_irq_byname_optional(pdev, "dma"); 1032 if (ret > 0) 1033 return ret; 1034 1035 snprintf(name, sizeof(name), "dma%u", nr); 1036 1037 return platform_get_irq_byname_optional(pdev, name); 1038 } 1039 1040 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 1041 .irq_vector = dw_pcie_edma_irq_vector, 1042 }; 1043 1044 static void dw_pcie_edma_init_data(struct dw_pcie *pci) 1045 { 1046 pci->edma.dev = pci->dev; 1047 1048 if (!pci->edma.ops) 1049 pci->edma.ops = &dw_pcie_edma_ops; 1050 1051 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 1052 } 1053 1054 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 1055 { 1056 u32 val; 1057 1058 /* 1059 * Bail out finding the mapping format if it is already set by the glue 1060 * driver. Also ensure that the edma.reg_base is pointing to a valid 1061 * memory region. 1062 */ 1063 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 1064 return pci->edma.reg_base ? 0 : -ENODEV; 1065 1066 /* 1067 * Indirect eDMA CSRs access has been completely removed since v5.40a 1068 * thus no space is now reserved for the eDMA channels viewport and 1069 * former DMA CTRL register is no longer fixed to FFs. 1070 */ 1071 if (dw_pcie_ver_is_ge(pci, 540A)) 1072 val = 0xFFFFFFFF; 1073 else 1074 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 1075 1076 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 1077 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 1078 } else if (val != 0xFFFFFFFF) { 1079 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 1080 1081 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 1082 } else { 1083 return -ENODEV; 1084 } 1085 1086 return 0; 1087 } 1088 1089 static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 1090 { 1091 u32 val; 1092 1093 /* 1094 * Autodetect the read/write channels count only for non-HDMA platforms. 1095 * HDMA platforms with native CSR mapping doesn't support autodetect, 1096 * so the glue drivers should've passed the valid count already. If not, 1097 * the below sanity check will catch it. 1098 */ 1099 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 1100 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 1101 1102 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 1103 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 1104 } 1105 1106 /* Sanity check the channels count if the mapping was incorrect */ 1107 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 1108 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 1109 return -EINVAL; 1110 1111 return 0; 1112 } 1113 1114 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 1115 { 1116 int ret; 1117 1118 dw_pcie_edma_init_data(pci); 1119 1120 ret = dw_pcie_edma_find_mf(pci); 1121 if (ret) 1122 return ret; 1123 1124 return dw_pcie_edma_find_channels(pci); 1125 } 1126 1127 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 1128 { 1129 struct platform_device *pdev = to_platform_device(pci->dev); 1130 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 1131 char name[15]; 1132 int ret; 1133 1134 if (pci->edma.nr_irqs > 1) 1135 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 1136 1137 ret = platform_get_irq_byname_optional(pdev, "dma"); 1138 if (ret > 0) { 1139 pci->edma.nr_irqs = 1; 1140 return 0; 1141 } 1142 1143 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 1144 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 1145 1146 ret = platform_get_irq_byname_optional(pdev, name); 1147 if (ret <= 0) 1148 return -EINVAL; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 1155 { 1156 struct dw_edma_region *ll; 1157 dma_addr_t paddr; 1158 int i; 1159 1160 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1161 ll = &pci->edma.ll_region_wr[i]; 1162 ll->sz = DMA_LLP_MEM_SIZE; 1163 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1164 &paddr, GFP_KERNEL); 1165 if (!ll->vaddr.mem) 1166 return -ENOMEM; 1167 1168 ll->paddr = paddr; 1169 } 1170 1171 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1172 ll = &pci->edma.ll_region_rd[i]; 1173 ll->sz = DMA_LLP_MEM_SIZE; 1174 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1175 &paddr, GFP_KERNEL); 1176 if (!ll->vaddr.mem) 1177 return -ENOMEM; 1178 1179 ll->paddr = paddr; 1180 } 1181 1182 return 0; 1183 } 1184 1185 int dw_pcie_edma_detect(struct dw_pcie *pci) 1186 { 1187 int ret; 1188 1189 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1190 ret = dw_pcie_edma_find_chip(pci); 1191 if (ret) 1192 return 0; 1193 1194 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1195 ret = dw_pcie_edma_irq_verify(pci); 1196 if (ret) { 1197 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1198 return 0; 1199 } 1200 1201 ret = dw_pcie_edma_ll_alloc(pci); 1202 if (ret) { 1203 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1204 return ret; 1205 } 1206 1207 /* Don't fail if the DW eDMA driver can't find the device */ 1208 ret = dw_edma_probe(&pci->edma); 1209 if (ret && ret != -ENODEV) { 1210 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1211 return ret; 1212 } 1213 1214 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1215 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1216 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1217 1218 return 0; 1219 } 1220 1221 void dw_pcie_edma_remove(struct dw_pcie *pci) 1222 { 1223 dw_edma_remove(&pci->edma); 1224 } 1225 1226 void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) 1227 { 1228 u16 l1ss; 1229 u32 l1ss_cap; 1230 1231 if (pci->l1ss_support) 1232 return; 1233 1234 l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1235 if (!l1ss) 1236 return; 1237 1238 /* 1239 * Unless the driver claims "l1ss_support", don't advertise L1 PM 1240 * Substates because they require CLKREQ# and possibly other 1241 * device-specific configuration. 1242 */ 1243 l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); 1244 l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | 1245 PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | 1246 PCI_L1SS_CAP_L1_PM_SS); 1247 dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); 1248 } 1249 1250 /* TODO: Need to handle multi Root Ports */ 1251 void dw_pcie_program_t_power_on(struct dw_pcie *pci, u32 t_power_on) 1252 { 1253 u8 scale, value; 1254 u16 offset; 1255 u32 val; 1256 1257 if (!t_power_on) 1258 return; 1259 1260 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1261 if (!offset) 1262 return; 1263 1264 pcie_encode_t_power_on(t_power_on, &scale, &value); 1265 1266 dw_pcie_dbi_ro_wr_en(pci); 1267 1268 val = dw_pcie_readl_dbi(pci, offset + PCI_L1SS_CAP); 1269 val &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); 1270 FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale); 1271 FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value); 1272 1273 dw_pcie_writel_dbi(pci, offset + PCI_L1SS_CAP, val); 1274 1275 dw_pcie_dbi_ro_wr_dis(pci); 1276 } 1277 1278 void dw_pcie_setup(struct dw_pcie *pci) 1279 { 1280 u32 val; 1281 1282 dw_pcie_link_set_max_speed(pci); 1283 1284 /* Configure Gen1 N_FTS */ 1285 if (pci->n_fts[0]) { 1286 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 1287 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 1288 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 1289 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 1290 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1291 } 1292 1293 /* Configure Gen2+ N_FTS */ 1294 if (pci->n_fts[1]) { 1295 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1296 val &= ~PORT_LOGIC_N_FTS_MASK; 1297 val |= pci->n_fts[1]; 1298 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1299 } 1300 1301 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1302 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1303 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1304 PCIE_PL_CHK_REG_CHK_REG_START; 1305 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1306 } 1307 1308 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1309 val &= ~PORT_LINK_FAST_LINK_MODE; 1310 val |= PORT_LINK_DLL_LINK_EN; 1311 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1312 1313 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1314 } 1315 1316 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci, 1317 const char *reg_name, 1318 resource_size_t cpu_phys_addr) 1319 { 1320 struct device *dev = pci->dev; 1321 struct device_node *np = dev->of_node; 1322 int index; 1323 u64 reg_addr, fixup_addr; 1324 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr); 1325 1326 /* Look up reg_name address on parent bus */ 1327 index = of_property_match_string(np, "reg-names", reg_name); 1328 1329 if (index < 0) { 1330 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name); 1331 return 0; 1332 } 1333 1334 of_property_read_reg(np, index, ®_addr, NULL); 1335 1336 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL; 1337 if (fixup) { 1338 fixup_addr = fixup(pci, cpu_phys_addr); 1339 if (reg_addr == fixup_addr) { 1340 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n", 1341 reg_name, index, reg_addr, fixup_addr, 1342 (unsigned long long) cpu_phys_addr, fixup); 1343 } else { 1344 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n", 1345 reg_name, index, reg_addr, fixup_addr, 1346 (unsigned long long) cpu_phys_addr); 1347 reg_addr = fixup_addr; 1348 } 1349 1350 return cpu_phys_addr - reg_addr; 1351 } 1352 1353 if (pci->use_parent_dt_ranges) { 1354 1355 /* 1356 * This platform once had a fixup, presumably because it 1357 * translates between CPU and PCI controller addresses. 1358 * Log a note if devicetree didn't describe a translation. 1359 */ 1360 if (reg_addr == cpu_phys_addr) 1361 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n", 1362 reg_name, index, reg_addr, 1363 (unsigned long long) cpu_phys_addr); 1364 } else { 1365 if (reg_addr != cpu_phys_addr) { 1366 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n", 1367 reg_name, index, reg_addr, 1368 (unsigned long long) cpu_phys_addr); 1369 return 0; 1370 } 1371 } 1372 1373 return cpu_phys_addr - reg_addr; 1374 } 1375