1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/sizes.h> 21 #include <linux/types.h> 22 23 #include "../../pci.h" 24 #include "pcie-designware.h" 25 26 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 27 [DW_PCIE_DBI_CLK] = "dbi", 28 [DW_PCIE_MSTR_CLK] = "mstr", 29 [DW_PCIE_SLV_CLK] = "slv", 30 }; 31 32 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 33 [DW_PCIE_PIPE_CLK] = "pipe", 34 [DW_PCIE_CORE_CLK] = "core", 35 [DW_PCIE_AUX_CLK] = "aux", 36 [DW_PCIE_REF_CLK] = "ref", 37 }; 38 39 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 40 [DW_PCIE_DBI_RST] = "dbi", 41 [DW_PCIE_MSTR_RST] = "mstr", 42 [DW_PCIE_SLV_RST] = "slv", 43 }; 44 45 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 46 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 47 [DW_PCIE_STICKY_RST] = "sticky", 48 [DW_PCIE_CORE_RST] = "core", 49 [DW_PCIE_PIPE_RST] = "pipe", 50 [DW_PCIE_PHY_RST] = "phy", 51 [DW_PCIE_HOT_RST] = "hot", 52 [DW_PCIE_PWR_RST] = "pwr", 53 }; 54 55 static int dw_pcie_get_clocks(struct dw_pcie *pci) 56 { 57 int i, ret; 58 59 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 60 pci->app_clks[i].id = dw_pcie_app_clks[i]; 61 62 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 63 pci->core_clks[i].id = dw_pcie_core_clks[i]; 64 65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 66 pci->app_clks); 67 if (ret) 68 return ret; 69 70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 71 pci->core_clks); 72 } 73 74 static int dw_pcie_get_resets(struct dw_pcie *pci) 75 { 76 int i, ret; 77 78 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 80 81 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 82 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 83 84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 85 DW_PCIE_NUM_APP_RSTS, 86 pci->app_rsts); 87 if (ret) 88 return ret; 89 90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 91 DW_PCIE_NUM_CORE_RSTS, 92 pci->core_rsts); 93 if (ret) 94 return ret; 95 96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 97 if (IS_ERR(pci->pe_rst)) 98 return PTR_ERR(pci->pe_rst); 99 100 return 0; 101 } 102 103 int dw_pcie_get_resources(struct dw_pcie *pci) 104 { 105 struct platform_device *pdev = to_platform_device(pci->dev); 106 struct device_node *np = dev_of_node(pci->dev); 107 struct resource *res; 108 int ret; 109 110 if (!pci->dbi_base) { 111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 113 if (IS_ERR(pci->dbi_base)) 114 return PTR_ERR(pci->dbi_base); 115 pci->dbi_phys_addr = res->start; 116 } 117 118 /* DBI2 is mainly useful for the endpoint controller */ 119 if (!pci->dbi_base2) { 120 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 121 if (res) { 122 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 123 if (IS_ERR(pci->dbi_base2)) 124 return PTR_ERR(pci->dbi_base2); 125 } else { 126 pci->dbi_base2 = pci->dbi_base + SZ_4K; 127 } 128 } 129 130 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 131 if (!pci->atu_base) { 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 133 if (res) { 134 pci->atu_size = resource_size(res); 135 pci->atu_base = devm_ioremap_resource(pci->dev, res); 136 if (IS_ERR(pci->atu_base)) 137 return PTR_ERR(pci->atu_base); 138 pci->atu_phys_addr = res->start; 139 } else { 140 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 141 } 142 } 143 144 /* Set a default value suitable for at most 8 in and 8 out windows */ 145 if (!pci->atu_size) 146 pci->atu_size = SZ_4K; 147 148 /* eDMA region can be mapped to a custom base address */ 149 if (!pci->edma.reg_base) { 150 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 151 if (res) { 152 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 153 if (IS_ERR(pci->edma.reg_base)) 154 return PTR_ERR(pci->edma.reg_base); 155 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 156 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 157 } 158 } 159 160 /* LLDD is supposed to manually switch the clocks and resets state */ 161 if (dw_pcie_cap_is(pci, REQ_RES)) { 162 ret = dw_pcie_get_clocks(pci); 163 if (ret) 164 return ret; 165 166 ret = dw_pcie_get_resets(pci); 167 if (ret) 168 return ret; 169 } 170 171 if (pci->max_link_speed < 1) 172 pci->max_link_speed = of_pci_get_max_link_speed(np); 173 174 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 175 176 if (of_property_read_bool(np, "snps,enable-cdm-check")) 177 dw_pcie_cap_set(pci, CDM_CHECK); 178 179 return 0; 180 } 181 182 void dw_pcie_version_detect(struct dw_pcie *pci) 183 { 184 u32 ver; 185 186 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 187 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 188 if (!ver) 189 return; 190 191 if (pci->version && pci->version != ver) 192 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 193 pci->version, ver); 194 else 195 pci->version = ver; 196 197 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 198 199 if (pci->type && pci->type != ver) 200 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 201 pci->type, ver); 202 else 203 pci->type = ver; 204 } 205 206 /* 207 * These interfaces resemble the pci_find_*capability() interfaces, but these 208 * are for configuring host controllers, which are bridges *to* PCI devices but 209 * are not PCI devices themselves. 210 */ 211 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, 212 u8 cap) 213 { 214 u8 cap_id, next_cap_ptr; 215 u16 reg; 216 217 if (!cap_ptr) 218 return 0; 219 220 reg = dw_pcie_readw_dbi(pci, cap_ptr); 221 cap_id = (reg & 0x00ff); 222 223 if (cap_id > PCI_CAP_ID_MAX) 224 return 0; 225 226 if (cap_id == cap) 227 return cap_ptr; 228 229 next_cap_ptr = (reg & 0xff00) >> 8; 230 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 231 } 232 233 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 234 { 235 u8 next_cap_ptr; 236 u16 reg; 237 238 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); 239 next_cap_ptr = (reg & 0x00ff); 240 241 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 242 } 243 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 244 245 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, 246 u8 cap) 247 { 248 u32 header; 249 int ttl; 250 int pos = PCI_CFG_SPACE_SIZE; 251 252 /* minimum 8 bytes per capability */ 253 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 254 255 if (start) 256 pos = start; 257 258 header = dw_pcie_readl_dbi(pci, pos); 259 /* 260 * If we have no capabilities, this is indicated by cap ID, 261 * cap version and next pointer all being 0. 262 */ 263 if (header == 0) 264 return 0; 265 266 while (ttl-- > 0) { 267 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 268 return pos; 269 270 pos = PCI_EXT_CAP_NEXT(header); 271 if (pos < PCI_CFG_SPACE_SIZE) 272 break; 273 274 header = dw_pcie_readl_dbi(pci, pos); 275 } 276 277 return 0; 278 } 279 280 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 281 { 282 return dw_pcie_find_next_ext_capability(pci, 0, cap); 283 } 284 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 285 286 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 287 { 288 if (!IS_ALIGNED((uintptr_t)addr, size)) { 289 *val = 0; 290 return PCIBIOS_BAD_REGISTER_NUMBER; 291 } 292 293 if (size == 4) { 294 *val = readl(addr); 295 } else if (size == 2) { 296 *val = readw(addr); 297 } else if (size == 1) { 298 *val = readb(addr); 299 } else { 300 *val = 0; 301 return PCIBIOS_BAD_REGISTER_NUMBER; 302 } 303 304 return PCIBIOS_SUCCESSFUL; 305 } 306 EXPORT_SYMBOL_GPL(dw_pcie_read); 307 308 int dw_pcie_write(void __iomem *addr, int size, u32 val) 309 { 310 if (!IS_ALIGNED((uintptr_t)addr, size)) 311 return PCIBIOS_BAD_REGISTER_NUMBER; 312 313 if (size == 4) 314 writel(val, addr); 315 else if (size == 2) 316 writew(val, addr); 317 else if (size == 1) 318 writeb(val, addr); 319 else 320 return PCIBIOS_BAD_REGISTER_NUMBER; 321 322 return PCIBIOS_SUCCESSFUL; 323 } 324 EXPORT_SYMBOL_GPL(dw_pcie_write); 325 326 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 327 { 328 int ret; 329 u32 val; 330 331 if (pci->ops && pci->ops->read_dbi) 332 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 333 334 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 335 if (ret) 336 dev_err(pci->dev, "Read DBI address failed\n"); 337 338 return val; 339 } 340 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 341 342 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 343 { 344 int ret; 345 346 if (pci->ops && pci->ops->write_dbi) { 347 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 348 return; 349 } 350 351 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 352 if (ret) 353 dev_err(pci->dev, "Write DBI address failed\n"); 354 } 355 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 356 357 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 358 { 359 int ret; 360 361 if (pci->ops && pci->ops->write_dbi2) { 362 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 363 return; 364 } 365 366 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 367 if (ret) 368 dev_err(pci->dev, "write DBI address failed\n"); 369 } 370 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 371 372 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 373 u32 index) 374 { 375 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 376 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 377 378 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 379 return pci->atu_base; 380 } 381 382 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 383 { 384 void __iomem *base; 385 int ret; 386 u32 val; 387 388 base = dw_pcie_select_atu(pci, dir, index); 389 390 if (pci->ops && pci->ops->read_dbi) 391 return pci->ops->read_dbi(pci, base, reg, 4); 392 393 ret = dw_pcie_read(base + reg, 4, &val); 394 if (ret) 395 dev_err(pci->dev, "Read ATU address failed\n"); 396 397 return val; 398 } 399 400 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 401 u32 reg, u32 val) 402 { 403 void __iomem *base; 404 int ret; 405 406 base = dw_pcie_select_atu(pci, dir, index); 407 408 if (pci->ops && pci->ops->write_dbi) { 409 pci->ops->write_dbi(pci, base, reg, 4, val); 410 return; 411 } 412 413 ret = dw_pcie_write(base + reg, 4, val); 414 if (ret) 415 dev_err(pci->dev, "Write ATU address failed\n"); 416 } 417 418 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 419 { 420 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 421 } 422 423 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 424 u32 val) 425 { 426 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 427 } 428 429 static inline u32 dw_pcie_enable_ecrc(u32 val) 430 { 431 /* 432 * DesignWare core version 4.90A has a design issue where the 'TD' 433 * bit in the Control register-1 of the ATU outbound region acts 434 * like an override for the ECRC setting, i.e., the presence of TLP 435 * Digest (ECRC) in the outgoing TLPs is solely determined by this 436 * bit. This is contrary to the PCIe spec which says that the 437 * enablement of the ECRC is solely determined by the AER 438 * registers. 439 * 440 * Because of this, even when the ECRC is enabled through AER 441 * registers, the transactions going through ATU won't have TLP 442 * Digest as there is no way the PCI core AER code could program 443 * the TD bit which is specific to the DesignWare core. 444 * 445 * The best way to handle this scenario is to program the TD bit 446 * always. It affects only the traffic from root port to downstream 447 * devices. 448 * 449 * At this point, 450 * When ECRC is enabled in AER registers, everything works normally 451 * When ECRC is NOT enabled in AER registers, then, 452 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 453 * even through it is not required. Since downstream 454 * TLPs are mostly for configuration accesses and BAR 455 * accesses, they are not in critical path and won't 456 * have much negative effect on the performance. 457 * on End Point:- TLP Digest is received for some/all the packets coming 458 * from the root port. TLP Digest is ignored because, 459 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 460 * "TLP Digest Rules", when an endpoint receives TLP 461 * Digest when its ECRC check functionality is disabled 462 * in AER registers, received TLP Digest is just ignored. 463 * Since there is no issue or error reported either side, best way to 464 * handle the scenario is to program TD bit by default. 465 */ 466 467 return val | PCIE_ATU_TD; 468 } 469 470 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 471 const struct dw_pcie_ob_atu_cfg *atu) 472 { 473 u64 cpu_addr = atu->cpu_addr; 474 u32 retries, val; 475 u64 limit_addr; 476 477 if (pci->ops && pci->ops->cpu_addr_fixup) 478 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); 479 480 limit_addr = cpu_addr + atu->size - 1; 481 482 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || 483 !IS_ALIGNED(cpu_addr, pci->region_align) || 484 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 485 return -EINVAL; 486 } 487 488 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, 489 lower_32_bits(cpu_addr)); 490 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, 491 upper_32_bits(cpu_addr)); 492 493 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, 494 lower_32_bits(limit_addr)); 495 if (dw_pcie_ver_is_ge(pci, 460A)) 496 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, 497 upper_32_bits(limit_addr)); 498 499 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, 500 lower_32_bits(atu->pci_addr)); 501 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, 502 upper_32_bits(atu->pci_addr)); 503 504 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); 505 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && 506 dw_pcie_ver_is_ge(pci, 460A)) 507 val |= PCIE_ATU_INCREASE_REGION_SIZE; 508 if (dw_pcie_ver_is(pci, 490A)) 509 val = dw_pcie_enable_ecrc(val); 510 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 511 512 val = PCIE_ATU_ENABLE; 513 if (atu->type == PCIE_ATU_TYPE_MSG) { 514 /* The data-less messages only for now */ 515 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; 516 } 517 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); 518 519 /* 520 * Make sure ATU enable takes effect before any subsequent config 521 * and I/O accesses. 522 */ 523 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 524 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); 525 if (val & PCIE_ATU_ENABLE) 526 return 0; 527 528 mdelay(LINK_WAIT_IATU); 529 } 530 531 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 532 533 return -ETIMEDOUT; 534 } 535 536 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 537 { 538 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 539 } 540 541 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 542 u32 val) 543 { 544 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 545 } 546 547 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 548 u64 cpu_addr, u64 pci_addr, u64 size) 549 { 550 u64 limit_addr = pci_addr + size - 1; 551 u32 retries, val; 552 553 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 554 !IS_ALIGNED(cpu_addr, pci->region_align) || 555 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 556 return -EINVAL; 557 } 558 559 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 560 lower_32_bits(pci_addr)); 561 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 562 upper_32_bits(pci_addr)); 563 564 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 565 lower_32_bits(limit_addr)); 566 if (dw_pcie_ver_is_ge(pci, 460A)) 567 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 568 upper_32_bits(limit_addr)); 569 570 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 571 lower_32_bits(cpu_addr)); 572 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 573 upper_32_bits(cpu_addr)); 574 575 val = type; 576 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 577 dw_pcie_ver_is_ge(pci, 460A)) 578 val |= PCIE_ATU_INCREASE_REGION_SIZE; 579 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 580 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 581 582 /* 583 * Make sure ATU enable takes effect before any subsequent config 584 * and I/O accesses. 585 */ 586 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 587 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 588 if (val & PCIE_ATU_ENABLE) 589 return 0; 590 591 mdelay(LINK_WAIT_IATU); 592 } 593 594 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 595 596 return -ETIMEDOUT; 597 } 598 599 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 600 int type, u64 cpu_addr, u8 bar) 601 { 602 u32 retries, val; 603 604 if (!IS_ALIGNED(cpu_addr, pci->region_align)) 605 return -EINVAL; 606 607 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 608 lower_32_bits(cpu_addr)); 609 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 610 upper_32_bits(cpu_addr)); 611 612 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 613 PCIE_ATU_FUNC_NUM(func_no)); 614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 615 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 616 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 617 618 /* 619 * Make sure ATU enable takes effect before any subsequent config 620 * and I/O accesses. 621 */ 622 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 623 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 624 if (val & PCIE_ATU_ENABLE) 625 return 0; 626 627 mdelay(LINK_WAIT_IATU); 628 } 629 630 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 631 632 return -ETIMEDOUT; 633 } 634 635 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 636 { 637 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 638 } 639 640 int dw_pcie_wait_for_link(struct dw_pcie *pci) 641 { 642 u32 offset, val; 643 int retries; 644 645 /* Check if the link is up or not */ 646 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 647 if (dw_pcie_link_up(pci)) 648 break; 649 650 msleep(LINK_WAIT_SLEEP_MS); 651 } 652 653 if (retries >= LINK_WAIT_MAX_RETRIES) { 654 dev_info(pci->dev, "Phy link never came up\n"); 655 return -ETIMEDOUT; 656 } 657 658 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 659 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 660 661 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 662 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 663 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 664 665 return 0; 666 } 667 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 668 669 int dw_pcie_link_up(struct dw_pcie *pci) 670 { 671 u32 val; 672 673 if (pci->ops && pci->ops->link_up) 674 return pci->ops->link_up(pci); 675 676 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 677 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 678 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 679 } 680 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 681 682 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 683 { 684 u32 val; 685 686 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 687 val |= PORT_MLTI_UPCFG_SUPPORT; 688 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 689 } 690 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 691 692 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 693 { 694 u32 cap, ctrl2, link_speed; 695 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 696 697 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 698 699 /* 700 * Even if the platform doesn't want to limit the maximum link speed, 701 * just cache the hardware default value so that the vendor drivers can 702 * use it to do any link specific configuration. 703 */ 704 if (pci->max_link_speed < 1) { 705 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 706 return; 707 } 708 709 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 710 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 711 712 switch (pcie_link_speed[pci->max_link_speed]) { 713 case PCIE_SPEED_2_5GT: 714 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 715 break; 716 case PCIE_SPEED_5_0GT: 717 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 718 break; 719 case PCIE_SPEED_8_0GT: 720 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 721 break; 722 case PCIE_SPEED_16_0GT: 723 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 724 break; 725 default: 726 /* Use hardware capability */ 727 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 728 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 729 break; 730 } 731 732 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 733 734 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 735 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 736 737 } 738 739 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 740 { 741 u32 lnkcap, lwsc, plc; 742 u8 cap; 743 744 if (!num_lanes) 745 return; 746 747 /* Set the number of lanes */ 748 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 749 plc &= ~PORT_LINK_FAST_LINK_MODE; 750 plc &= ~PORT_LINK_MODE_MASK; 751 752 /* Set link width speed control register */ 753 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 754 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; 755 switch (num_lanes) { 756 case 1: 757 plc |= PORT_LINK_MODE_1_LANES; 758 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; 759 break; 760 case 2: 761 plc |= PORT_LINK_MODE_2_LANES; 762 lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES; 763 break; 764 case 4: 765 plc |= PORT_LINK_MODE_4_LANES; 766 lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES; 767 break; 768 case 8: 769 plc |= PORT_LINK_MODE_8_LANES; 770 lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES; 771 break; 772 default: 773 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 774 return; 775 } 776 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); 777 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); 778 779 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 780 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 781 lnkcap &= ~PCI_EXP_LNKCAP_MLW; 782 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); 783 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 784 } 785 786 void dw_pcie_iatu_detect(struct dw_pcie *pci) 787 { 788 int max_region, ob, ib; 789 u32 val, min, dir; 790 u64 max; 791 792 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 793 if (val == 0xFFFFFFFF) { 794 dw_pcie_cap_set(pci, IATU_UNROLL); 795 796 max_region = min((int)pci->atu_size / 512, 256); 797 } else { 798 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 799 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 800 801 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 802 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 803 } 804 805 for (ob = 0; ob < max_region; ob++) { 806 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 807 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 808 if (val != 0x11110000) 809 break; 810 } 811 812 for (ib = 0; ib < max_region; ib++) { 813 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 814 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 815 if (val != 0x11110000) 816 break; 817 } 818 819 if (ob) { 820 dir = PCIE_ATU_REGION_DIR_OB; 821 } else if (ib) { 822 dir = PCIE_ATU_REGION_DIR_IB; 823 } else { 824 dev_err(pci->dev, "No iATU regions found\n"); 825 return; 826 } 827 828 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 829 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 830 831 if (dw_pcie_ver_is_ge(pci, 460A)) { 832 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 833 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 834 } else { 835 max = 0; 836 } 837 838 pci->num_ob_windows = ob; 839 pci->num_ib_windows = ib; 840 pci->region_align = 1 << fls(min); 841 pci->region_limit = (max << 32) | (SZ_4G - 1); 842 843 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 844 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 845 pci->num_ob_windows, pci->num_ib_windows, 846 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 847 } 848 849 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 850 { 851 u32 val = 0; 852 int ret; 853 854 if (pci->ops && pci->ops->read_dbi) 855 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 856 857 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 858 if (ret) 859 dev_err(pci->dev, "Read DMA address failed\n"); 860 861 return val; 862 } 863 864 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 865 { 866 struct platform_device *pdev = to_platform_device(dev); 867 char name[6]; 868 int ret; 869 870 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 871 return -EINVAL; 872 873 ret = platform_get_irq_byname_optional(pdev, "dma"); 874 if (ret > 0) 875 return ret; 876 877 snprintf(name, sizeof(name), "dma%u", nr); 878 879 return platform_get_irq_byname_optional(pdev, name); 880 } 881 882 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 883 .irq_vector = dw_pcie_edma_irq_vector, 884 }; 885 886 static void dw_pcie_edma_init_data(struct dw_pcie *pci) 887 { 888 pci->edma.dev = pci->dev; 889 890 if (!pci->edma.ops) 891 pci->edma.ops = &dw_pcie_edma_ops; 892 893 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 894 } 895 896 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 897 { 898 u32 val; 899 900 /* 901 * Bail out finding the mapping format if it is already set by the glue 902 * driver. Also ensure that the edma.reg_base is pointing to a valid 903 * memory region. 904 */ 905 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 906 return pci->edma.reg_base ? 0 : -ENODEV; 907 908 /* 909 * Indirect eDMA CSRs access has been completely removed since v5.40a 910 * thus no space is now reserved for the eDMA channels viewport and 911 * former DMA CTRL register is no longer fixed to FFs. 912 */ 913 if (dw_pcie_ver_is_ge(pci, 540A)) 914 val = 0xFFFFFFFF; 915 else 916 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 917 918 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 919 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 920 } else if (val != 0xFFFFFFFF) { 921 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 922 923 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 924 } else { 925 return -ENODEV; 926 } 927 928 return 0; 929 } 930 931 static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 932 { 933 u32 val; 934 935 /* 936 * Autodetect the read/write channels count only for non-HDMA platforms. 937 * HDMA platforms with native CSR mapping doesn't support autodetect, 938 * so the glue drivers should've passed the valid count already. If not, 939 * the below sanity check will catch it. 940 */ 941 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 942 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 943 944 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 945 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 946 } 947 948 /* Sanity check the channels count if the mapping was incorrect */ 949 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 950 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 951 return -EINVAL; 952 953 return 0; 954 } 955 956 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 957 { 958 int ret; 959 960 dw_pcie_edma_init_data(pci); 961 962 ret = dw_pcie_edma_find_mf(pci); 963 if (ret) 964 return ret; 965 966 return dw_pcie_edma_find_channels(pci); 967 } 968 969 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 970 { 971 struct platform_device *pdev = to_platform_device(pci->dev); 972 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 973 char name[6]; 974 int ret; 975 976 if (pci->edma.nr_irqs == 1) 977 return 0; 978 else if (pci->edma.nr_irqs > 1) 979 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 980 981 ret = platform_get_irq_byname_optional(pdev, "dma"); 982 if (ret > 0) { 983 pci->edma.nr_irqs = 1; 984 return 0; 985 } 986 987 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 988 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 989 990 ret = platform_get_irq_byname_optional(pdev, name); 991 if (ret <= 0) 992 return -EINVAL; 993 } 994 995 return 0; 996 } 997 998 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 999 { 1000 struct dw_edma_region *ll; 1001 dma_addr_t paddr; 1002 int i; 1003 1004 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1005 ll = &pci->edma.ll_region_wr[i]; 1006 ll->sz = DMA_LLP_MEM_SIZE; 1007 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1008 &paddr, GFP_KERNEL); 1009 if (!ll->vaddr.mem) 1010 return -ENOMEM; 1011 1012 ll->paddr = paddr; 1013 } 1014 1015 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1016 ll = &pci->edma.ll_region_rd[i]; 1017 ll->sz = DMA_LLP_MEM_SIZE; 1018 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1019 &paddr, GFP_KERNEL); 1020 if (!ll->vaddr.mem) 1021 return -ENOMEM; 1022 1023 ll->paddr = paddr; 1024 } 1025 1026 return 0; 1027 } 1028 1029 int dw_pcie_edma_detect(struct dw_pcie *pci) 1030 { 1031 int ret; 1032 1033 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1034 ret = dw_pcie_edma_find_chip(pci); 1035 if (ret) 1036 return 0; 1037 1038 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1039 ret = dw_pcie_edma_irq_verify(pci); 1040 if (ret) { 1041 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1042 return 0; 1043 } 1044 1045 ret = dw_pcie_edma_ll_alloc(pci); 1046 if (ret) { 1047 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1048 return ret; 1049 } 1050 1051 /* Don't fail if the DW eDMA driver can't find the device */ 1052 ret = dw_edma_probe(&pci->edma); 1053 if (ret && ret != -ENODEV) { 1054 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1055 return ret; 1056 } 1057 1058 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1059 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1060 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1061 1062 return 0; 1063 } 1064 1065 void dw_pcie_edma_remove(struct dw_pcie *pci) 1066 { 1067 dw_edma_remove(&pci->edma); 1068 } 1069 1070 void dw_pcie_setup(struct dw_pcie *pci) 1071 { 1072 u32 val; 1073 1074 dw_pcie_link_set_max_speed(pci); 1075 1076 /* Configure Gen1 N_FTS */ 1077 if (pci->n_fts[0]) { 1078 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 1079 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 1080 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 1081 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 1082 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1083 } 1084 1085 /* Configure Gen2+ N_FTS */ 1086 if (pci->n_fts[1]) { 1087 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1088 val &= ~PORT_LOGIC_N_FTS_MASK; 1089 val |= pci->n_fts[1]; 1090 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1091 } 1092 1093 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1094 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1095 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1096 PCIE_PL_CHK_REG_CHK_REG_START; 1097 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1098 } 1099 1100 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1101 val &= ~PORT_LINK_FAST_LINK_MODE; 1102 val |= PORT_LINK_DLL_LINK_EN; 1103 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1104 1105 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1106 } 1107