1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/pcie-dwc.h> 21 #include <linux/platform_device.h> 22 #include <linux/sizes.h> 23 #include <linux/types.h> 24 25 #include "../pci-host-common.h" 26 #include "../../pci.h" 27 #include "pcie-designware.h" 28 29 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 30 [DW_PCIE_DBI_CLK] = "dbi", 31 [DW_PCIE_MSTR_CLK] = "mstr", 32 [DW_PCIE_SLV_CLK] = "slv", 33 }; 34 35 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 36 [DW_PCIE_PIPE_CLK] = "pipe", 37 [DW_PCIE_CORE_CLK] = "core", 38 [DW_PCIE_AUX_CLK] = "aux", 39 [DW_PCIE_REF_CLK] = "ref", 40 }; 41 42 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 43 [DW_PCIE_DBI_RST] = "dbi", 44 [DW_PCIE_MSTR_RST] = "mstr", 45 [DW_PCIE_SLV_RST] = "slv", 46 }; 47 48 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 49 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 50 [DW_PCIE_STICKY_RST] = "sticky", 51 [DW_PCIE_CORE_RST] = "core", 52 [DW_PCIE_PIPE_RST] = "pipe", 53 [DW_PCIE_PHY_RST] = "phy", 54 [DW_PCIE_HOT_RST] = "hot", 55 [DW_PCIE_PWR_RST] = "pwr", 56 }; 57 58 static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { 59 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ 60 .vsec_id = 0x03, .vsec_rev = 0x1 }, 61 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ 62 .vsec_id = 0x04, .vsec_rev = 0x1 }, 63 { } 64 }; 65 66 static int dw_pcie_get_clocks(struct dw_pcie *pci) 67 { 68 int i, ret; 69 70 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 71 pci->app_clks[i].id = dw_pcie_app_clks[i]; 72 73 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 74 pci->core_clks[i].id = dw_pcie_core_clks[i]; 75 76 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 77 pci->app_clks); 78 if (ret) 79 return ret; 80 81 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 82 pci->core_clks); 83 } 84 85 static int dw_pcie_get_resets(struct dw_pcie *pci) 86 { 87 int i, ret; 88 89 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 90 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 91 92 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 93 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 94 95 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 96 DW_PCIE_NUM_APP_RSTS, 97 pci->app_rsts); 98 if (ret) 99 return ret; 100 101 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 102 DW_PCIE_NUM_CORE_RSTS, 103 pci->core_rsts); 104 if (ret) 105 return ret; 106 107 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 108 if (IS_ERR(pci->pe_rst)) 109 return PTR_ERR(pci->pe_rst); 110 111 return 0; 112 } 113 114 int dw_pcie_get_resources(struct dw_pcie *pci) 115 { 116 struct platform_device *pdev = to_platform_device(pci->dev); 117 struct device_node *np = dev_of_node(pci->dev); 118 struct resource *res; 119 int ret; 120 121 if (!pci->dbi_base) { 122 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 123 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 124 if (IS_ERR(pci->dbi_base)) 125 return PTR_ERR(pci->dbi_base); 126 pci->dbi_phys_addr = res->start; 127 } 128 129 /* DBI2 is mainly useful for the endpoint controller */ 130 if (!pci->dbi_base2) { 131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 132 if (res) { 133 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 134 if (IS_ERR(pci->dbi_base2)) 135 return PTR_ERR(pci->dbi_base2); 136 } else { 137 pci->dbi_base2 = pci->dbi_base + SZ_4K; 138 } 139 } 140 141 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 142 if (!pci->atu_base) { 143 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 144 if (res) { 145 pci->atu_size = resource_size(res); 146 pci->atu_base = devm_ioremap_resource(pci->dev, res); 147 if (IS_ERR(pci->atu_base)) 148 return PTR_ERR(pci->atu_base); 149 pci->atu_phys_addr = res->start; 150 } else { 151 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 152 } 153 } 154 155 /* Set a default value suitable for at most 8 in and 8 out windows */ 156 if (!pci->atu_size) 157 pci->atu_size = SZ_4K; 158 159 /* eDMA region can be mapped to a custom base address */ 160 if (!pci->edma.reg_base) { 161 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 162 if (res) { 163 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 164 if (IS_ERR(pci->edma.reg_base)) 165 return PTR_ERR(pci->edma.reg_base); 166 pci->edma_reg_phys = res->start; 167 pci->edma_reg_size = resource_size(res); 168 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 169 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 170 pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET; 171 pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET; 172 } 173 } 174 175 /* ELBI is an optional resource */ 176 if (!pci->elbi_base) { 177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 178 if (res) { 179 pci->elbi_base = devm_ioremap_resource(pci->dev, res); 180 if (IS_ERR(pci->elbi_base)) 181 return PTR_ERR(pci->elbi_base); 182 } 183 } 184 185 /* LLDD is supposed to manually switch the clocks and resets state */ 186 if (dw_pcie_cap_is(pci, REQ_RES)) { 187 ret = dw_pcie_get_clocks(pci); 188 if (ret) 189 return ret; 190 191 ret = dw_pcie_get_resets(pci); 192 if (ret) 193 return ret; 194 } 195 196 if (pci->max_link_speed < 1) 197 pci->max_link_speed = of_pci_get_max_link_speed(np); 198 199 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 200 201 if (of_property_read_bool(np, "snps,enable-cdm-check")) 202 dw_pcie_cap_set(pci, CDM_CHECK); 203 204 return 0; 205 } 206 207 void dw_pcie_version_detect(struct dw_pcie *pci) 208 { 209 u32 ver; 210 211 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 212 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 213 if (!ver) 214 return; 215 216 if (pci->version && pci->version != ver) 217 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 218 pci->version, ver); 219 else 220 pci->version = ver; 221 222 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 223 224 if (pci->type && pci->type != ver) 225 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 226 pci->type, ver); 227 else 228 pci->type = ver; 229 } 230 231 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 232 { 233 return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 234 NULL, pci); 235 } 236 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 237 238 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 239 { 240 return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, NULL, pci); 241 } 242 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 243 244 void dw_pcie_remove_capability(struct dw_pcie *pci, u8 cap) 245 { 246 u8 cap_pos, pre_pos, next_pos; 247 u16 reg; 248 249 cap_pos = PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 250 &pre_pos, pci); 251 if (!cap_pos) 252 return; 253 254 reg = dw_pcie_readw_dbi(pci, cap_pos); 255 next_pos = (reg & 0xff00) >> 8; 256 257 dw_pcie_dbi_ro_wr_en(pci); 258 if (pre_pos == PCI_CAPABILITY_LIST) 259 dw_pcie_writeb_dbi(pci, PCI_CAPABILITY_LIST, next_pos); 260 else 261 dw_pcie_writeb_dbi(pci, pre_pos + 1, next_pos); 262 dw_pcie_dbi_ro_wr_dis(pci); 263 } 264 EXPORT_SYMBOL_GPL(dw_pcie_remove_capability); 265 266 void dw_pcie_remove_ext_capability(struct dw_pcie *pci, u8 cap) 267 { 268 int cap_pos, next_pos, pre_pos; 269 u32 pre_header, header; 270 271 cap_pos = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, &pre_pos, pci); 272 if (!cap_pos) 273 return; 274 275 header = dw_pcie_readl_dbi(pci, cap_pos); 276 277 /* 278 * If the first cap at offset PCI_CFG_SPACE_SIZE is removed, 279 * only set its capid to zero as it cannot be skipped. 280 */ 281 if (cap_pos == PCI_CFG_SPACE_SIZE) { 282 dw_pcie_dbi_ro_wr_en(pci); 283 dw_pcie_writel_dbi(pci, cap_pos, header & 0xffff0000); 284 dw_pcie_dbi_ro_wr_dis(pci); 285 return; 286 } 287 288 pre_header = dw_pcie_readl_dbi(pci, pre_pos); 289 next_pos = PCI_EXT_CAP_NEXT(header); 290 291 dw_pcie_dbi_ro_wr_en(pci); 292 dw_pcie_writel_dbi(pci, pre_pos, 293 (pre_header & 0xfffff) | (next_pos << 20)); 294 dw_pcie_dbi_ro_wr_dis(pci); 295 } 296 EXPORT_SYMBOL_GPL(dw_pcie_remove_ext_capability); 297 298 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, 299 u16 vsec_id) 300 { 301 u16 vsec = 0; 302 u32 header; 303 304 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) 305 return 0; 306 307 while ((vsec = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, 308 PCI_EXT_CAP_ID_VNDR, NULL, pci))) { 309 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 310 if (PCI_VNDR_HEADER_ID(header) == vsec_id) 311 return vsec; 312 } 313 314 return 0; 315 } 316 317 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, 318 const struct dwc_pcie_vsec_id *vsec_ids) 319 { 320 const struct dwc_pcie_vsec_id *vid; 321 u16 vsec; 322 u32 header; 323 324 for (vid = vsec_ids; vid->vendor_id; vid++) { 325 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, 326 vid->vsec_id); 327 if (vsec) { 328 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 329 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) 330 return vsec; 331 } 332 } 333 334 return 0; 335 } 336 337 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) 338 { 339 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids); 340 } 341 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); 342 343 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) 344 { 345 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); 346 } 347 EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); 348 349 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 350 { 351 if (!IS_ALIGNED((uintptr_t)addr, size)) { 352 *val = 0; 353 return PCIBIOS_BAD_REGISTER_NUMBER; 354 } 355 356 if (size == 4) { 357 *val = readl(addr); 358 } else if (size == 2) { 359 *val = readw(addr); 360 } else if (size == 1) { 361 *val = readb(addr); 362 } else { 363 *val = 0; 364 return PCIBIOS_BAD_REGISTER_NUMBER; 365 } 366 367 return PCIBIOS_SUCCESSFUL; 368 } 369 EXPORT_SYMBOL_GPL(dw_pcie_read); 370 371 int dw_pcie_write(void __iomem *addr, int size, u32 val) 372 { 373 if (!IS_ALIGNED((uintptr_t)addr, size)) 374 return PCIBIOS_BAD_REGISTER_NUMBER; 375 376 if (size == 4) 377 writel(val, addr); 378 else if (size == 2) 379 writew(val, addr); 380 else if (size == 1) 381 writeb(val, addr); 382 else 383 return PCIBIOS_BAD_REGISTER_NUMBER; 384 385 return PCIBIOS_SUCCESSFUL; 386 } 387 EXPORT_SYMBOL_GPL(dw_pcie_write); 388 389 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 390 { 391 int ret; 392 u32 val; 393 394 if (pci->ops && pci->ops->read_dbi) 395 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 396 397 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 398 if (ret) 399 dev_err(pci->dev, "Read DBI address failed\n"); 400 401 return val; 402 } 403 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 404 405 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 406 { 407 int ret; 408 409 if (pci->ops && pci->ops->write_dbi) { 410 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 411 return; 412 } 413 414 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 415 if (ret) 416 dev_err(pci->dev, "Write DBI address failed\n"); 417 } 418 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 419 420 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 421 { 422 int ret; 423 424 if (pci->ops && pci->ops->write_dbi2) { 425 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 426 return; 427 } 428 429 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 430 if (ret) 431 dev_err(pci->dev, "write DBI address failed\n"); 432 } 433 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 434 435 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 436 u32 index) 437 { 438 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 439 return pci->atu_base + ATU_UNROLL_BASE(dir, index); 440 441 dw_pcie_writel_dbi(pci, IATU_VIEWPORT, dir | index); 442 return pci->atu_base; 443 } 444 445 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 446 { 447 void __iomem *base; 448 int ret; 449 u32 val; 450 451 base = dw_pcie_select_atu(pci, dir, index); 452 453 if (pci->ops && pci->ops->read_dbi) 454 return pci->ops->read_dbi(pci, base, reg, 4); 455 456 ret = dw_pcie_read(base + reg, 4, &val); 457 if (ret) 458 dev_err(pci->dev, "Read ATU address failed\n"); 459 460 return val; 461 } 462 463 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 464 u32 reg, u32 val) 465 { 466 void __iomem *base; 467 int ret; 468 469 base = dw_pcie_select_atu(pci, dir, index); 470 471 if (pci->ops && pci->ops->write_dbi) { 472 pci->ops->write_dbi(pci, base, reg, 4, val); 473 return; 474 } 475 476 ret = dw_pcie_write(base + reg, 4, val); 477 if (ret) 478 dev_err(pci->dev, "Write ATU address failed\n"); 479 } 480 481 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 482 { 483 return dw_pcie_readl_atu(pci, ATU_REGION_DIR_OB, index, reg); 484 } 485 486 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 487 u32 val) 488 { 489 dw_pcie_writel_atu(pci, ATU_REGION_DIR_OB, index, reg, val); 490 } 491 492 static inline u32 dw_pcie_enable_ecrc(u32 val) 493 { 494 /* 495 * DesignWare core versions prior to 5.10A have a design issue where the 496 * 'TD' bit in the Control register-1 of the ATU outbound region acts 497 * like an override for the ECRC setting, i.e., the presence of TLP 498 * Digest (ECRC) in the outgoing TLPs is solely determined by this 499 * bit. This is contrary to the PCIe spec which says that the 500 * enablement of the ECRC is solely determined by the AER 501 * registers. 502 * 503 * Because of this, even when the ECRC is enabled through AER 504 * registers, the transactions going through ATU won't have TLP 505 * Digest as there is no way the PCI core AER code could program 506 * the TD bit which is specific to the DesignWare core. 507 * 508 * The best way to handle this scenario is to program the TD bit 509 * always. It affects only the traffic from root port to downstream 510 * devices. 511 * 512 * At this point, 513 * When ECRC is enabled in AER registers, everything works normally 514 * When ECRC is NOT enabled in AER registers, then, 515 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 516 * even through it is not required. Since downstream 517 * TLPs are mostly for configuration accesses and BAR 518 * accesses, they are not in critical path and won't 519 * have much negative effect on the performance. 520 * on End Point:- TLP Digest is received for some/all the packets coming 521 * from the root port. TLP Digest is ignored because, 522 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 523 * "TLP Digest Rules", when an endpoint receives TLP 524 * Digest when its ECRC check functionality is disabled 525 * in AER registers, received TLP Digest is just ignored. 526 * Since there is no issue or error reported either side, best way to 527 * handle the scenario is to program TD bit by default. 528 */ 529 530 return val | ATU_TD; 531 } 532 533 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 534 const struct dw_pcie_ob_atu_cfg *atu) 535 { 536 u64 parent_bus_addr = atu->parent_bus_addr; 537 u32 retries, val; 538 u64 limit_addr; 539 540 if (atu->index >= pci->num_ob_windows) 541 return -ENOSPC; 542 543 limit_addr = parent_bus_addr + atu->size - 1; 544 545 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || 546 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 547 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 548 return -EINVAL; 549 } 550 551 dw_pcie_writel_atu_ob(pci, atu->index, ATU_LOWER_BASE, 552 lower_32_bits(parent_bus_addr)); 553 dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_BASE, 554 upper_32_bits(parent_bus_addr)); 555 556 dw_pcie_writel_atu_ob(pci, atu->index, ATU_LIMIT, 557 lower_32_bits(limit_addr)); 558 if (dw_pcie_ver_is_ge(pci, 460A)) 559 dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_LIMIT, 560 upper_32_bits(limit_addr)); 561 562 dw_pcie_writel_atu_ob(pci, atu->index, ATU_LOWER_TARGET, 563 lower_32_bits(atu->pci_addr)); 564 dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_TARGET, 565 upper_32_bits(atu->pci_addr)); 566 567 val = atu->type | atu->routing | ATU_FUNC_NUM(atu->func_no); 568 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && 569 dw_pcie_ver_is_ge(pci, 460A)) 570 val |= ATU_INCREASE_REGION_SIZE; 571 if (!dw_pcie_ver_is_ge(pci, 510A)) 572 val = dw_pcie_enable_ecrc(val); 573 dw_pcie_writel_atu_ob(pci, atu->index, ATU_REGION_CTRL1, val); 574 575 val = ATU_ENABLE | atu->ctrl2; 576 if (atu->type == PCIE_TLP_TYPE_MSG) { 577 /* The data-less messages only for now */ 578 val |= ATU_INHIBIT_PAYLOAD | atu->code; 579 } 580 if (dw_pcie_ver_is_ge(pci, 460A)) 581 val |= ATU_DMA_BYPASS; 582 dw_pcie_writel_atu_ob(pci, atu->index, ATU_REGION_CTRL2, val); 583 584 /* 585 * Make sure ATU enable takes effect before any subsequent config 586 * and I/O accesses. 587 */ 588 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 589 val = dw_pcie_readl_atu_ob(pci, atu->index, ATU_REGION_CTRL2); 590 if (val & ATU_ENABLE) 591 return 0; 592 593 mdelay(LINK_WAIT_IATU); 594 } 595 596 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 597 598 return -ETIMEDOUT; 599 } 600 601 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 602 { 603 return dw_pcie_readl_atu(pci, ATU_REGION_DIR_IB, index, reg); 604 } 605 606 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 607 u32 val) 608 { 609 dw_pcie_writel_atu(pci, ATU_REGION_DIR_IB, index, reg, val); 610 } 611 612 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 613 u64 parent_bus_addr, u64 pci_addr, u64 size) 614 { 615 u64 limit_addr = pci_addr + size - 1; 616 u32 retries, val; 617 618 if (index >= pci->num_ib_windows) 619 return -ENOSPC; 620 621 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 622 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 623 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 624 return -EINVAL; 625 } 626 627 dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_BASE, 628 lower_32_bits(pci_addr)); 629 dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_BASE, 630 upper_32_bits(pci_addr)); 631 632 dw_pcie_writel_atu_ib(pci, index, ATU_LIMIT, 633 lower_32_bits(limit_addr)); 634 if (dw_pcie_ver_is_ge(pci, 460A)) 635 dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_LIMIT, 636 upper_32_bits(limit_addr)); 637 638 dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_TARGET, 639 lower_32_bits(parent_bus_addr)); 640 dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_TARGET, 641 upper_32_bits(parent_bus_addr)); 642 643 val = type; 644 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 645 dw_pcie_ver_is_ge(pci, 460A)) 646 val |= ATU_INCREASE_REGION_SIZE; 647 dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL1, val); 648 dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL2, ATU_ENABLE); 649 650 /* 651 * Make sure ATU enable takes effect before any subsequent config 652 * and I/O accesses. 653 */ 654 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 655 val = dw_pcie_readl_atu_ib(pci, index, ATU_REGION_CTRL2); 656 if (val & ATU_ENABLE) 657 return 0; 658 659 mdelay(LINK_WAIT_IATU); 660 } 661 662 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 663 664 return -ETIMEDOUT; 665 } 666 667 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 668 int type, u64 parent_bus_addr, u8 bar, size_t size) 669 { 670 u32 retries, val; 671 672 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) || 673 !IS_ALIGNED(parent_bus_addr, size)) 674 return -EINVAL; 675 676 dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_TARGET, 677 lower_32_bits(parent_bus_addr)); 678 dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_TARGET, 679 upper_32_bits(parent_bus_addr)); 680 681 dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL1, type | 682 ATU_FUNC_NUM(func_no)); 683 dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL2, 684 ATU_ENABLE | ATU_FUNC_NUM_MATCH_EN | 685 ATU_BAR_MODE_ENABLE | (bar << 8)); 686 687 /* 688 * Make sure ATU enable takes effect before any subsequent config 689 * and I/O accesses. 690 */ 691 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 692 val = dw_pcie_readl_atu_ib(pci, index, ATU_REGION_CTRL2); 693 if (val & ATU_ENABLE) 694 return 0; 695 696 mdelay(LINK_WAIT_IATU); 697 } 698 699 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 700 701 return -ETIMEDOUT; 702 } 703 704 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 705 { 706 dw_pcie_writel_atu(pci, dir, index, ATU_REGION_CTRL2, 0); 707 } 708 709 const char *dw_pcie_ltssm_status_string(enum dw_pcie_ltssm ltssm) 710 { 711 const char *str; 712 713 switch (ltssm) { 714 #define DW_PCIE_LTSSM_NAME(n) case n: str = #n; break 715 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_QUIET); 716 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_ACT); 717 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_ACTIVE); 718 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_COMPLIANCE); 719 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_CONFIG); 720 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_PRE_DETECT_QUIET); 721 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_WAIT); 722 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_START); 723 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_ACEPT); 724 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_WAI); 725 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_ACEPT); 726 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_COMPLETE); 727 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_IDLE); 728 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_LOCK); 729 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_SPEED); 730 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_RCVRCFG); 731 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_IDLE); 732 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0); 733 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0S); 734 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L123_SEND_EIDLE); 735 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_IDLE); 736 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_IDLE); 737 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_WAKE); 738 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_ENTRY); 739 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_IDLE); 740 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED); 741 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ENTRY); 742 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ACTIVE); 743 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT); 744 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT); 745 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET_ENTRY); 746 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET); 747 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ0); 748 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1); 749 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2); 750 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3); 751 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_1); 752 DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_2); 753 default: 754 str = "DW_PCIE_LTSSM_UNKNOWN"; 755 break; 756 } 757 758 return str + strlen("DW_PCIE_LTSSM_"); 759 } 760 761 /** 762 * dw_pcie_wait_for_link - Wait for the PCIe link to be up 763 * @pci: DWC instance 764 * 765 * Returns: 0 if link is up, -ENODEV if device is not found, -EIO if the device 766 * is found but not active and -ETIMEDOUT if the link fails to come up for other 767 * reasons. 768 */ 769 int dw_pcie_wait_for_link(struct dw_pcie *pci) 770 { 771 u32 offset, val, ltssm; 772 int retries; 773 774 /* Check if the link is up or not */ 775 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { 776 if (dw_pcie_link_up(pci)) 777 break; 778 779 msleep(PCIE_LINK_WAIT_SLEEP_MS); 780 } 781 782 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { 783 /* 784 * If the link is in Detect.Quiet or Detect.Active state, it 785 * indicates that no device is detected. 786 */ 787 ltssm = dw_pcie_get_ltssm(pci); 788 if (ltssm == DW_PCIE_LTSSM_DETECT_QUIET || 789 ltssm == DW_PCIE_LTSSM_DETECT_ACT) { 790 dev_info(pci->dev, "Device not found\n"); 791 return -ENODEV; 792 793 /* 794 * If the link is in POLL.{Active/Compliance} state, then the 795 * device is found to be connected to the bus, but it is not 796 * active i.e., the device firmware might not yet initialized. 797 */ 798 } else if (ltssm == DW_PCIE_LTSSM_POLL_ACTIVE || 799 ltssm == DW_PCIE_LTSSM_POLL_COMPLIANCE) { 800 dev_info(pci->dev, "Device found, but not active\n"); 801 return -EIO; 802 } 803 804 dev_err(pci->dev, "Link failed to come up. LTSSM: %s\n", 805 dw_pcie_ltssm_status_string(ltssm)); 806 return -ETIMEDOUT; 807 } 808 809 pci_host_common_link_train_delay(pci->max_link_speed); 810 811 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 812 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 813 814 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 815 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 816 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 817 818 return 0; 819 } 820 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 821 822 bool dw_pcie_link_up(struct dw_pcie *pci) 823 { 824 u32 val; 825 826 if (pci->ops && pci->ops->link_up) 827 return pci->ops->link_up(pci); 828 829 val = dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG1); 830 return ((val & PORT_LINK_DEBUG1_LINK_UP) && 831 (!(val & PORT_LINK_DEBUG1_LINK_IN_TRAINING))); 832 } 833 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 834 835 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 836 { 837 u32 val; 838 839 val = dw_pcie_readl_dbi(pci, MULTI_LANE_CTRL); 840 val |= MULTI_LANE_CTRL_UPCFG_SUPPORT; 841 dw_pcie_writel_dbi(pci, MULTI_LANE_CTRL, val); 842 } 843 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 844 845 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 846 { 847 u32 cap, ctrl2; 848 enum pci_bus_speed link_speed; 849 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 850 u16 ctrl2_speed; 851 852 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 853 854 /* 855 * Even if the platform doesn't want to limit the maximum link speed, 856 * just cache the hardware default value so that the vendor drivers can 857 * use it to do any link specific configuration. 858 */ 859 if (pci->max_link_speed < 1) { 860 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 861 return; 862 } 863 864 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 865 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 866 867 link_speed = pcie_get_link_speed(pci->max_link_speed); 868 ctrl2_speed = pci_bus_speed2lnkctl2(link_speed); 869 if (ctrl2_speed == 0) { 870 /* Use hardware capability */ 871 ctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 872 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 873 } 874 875 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed); 876 877 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 878 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed); 879 880 } 881 882 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) 883 { 884 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 885 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 886 887 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); 888 } 889 890 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 891 { 892 u32 lnkcap, lwsc, plc; 893 u8 cap; 894 895 if (!num_lanes) 896 return; 897 898 /* Set the number of lanes */ 899 plc = dw_pcie_readl_dbi(pci, PORT_LINK_CTRL); 900 plc &= ~PORT_LINK_CTRL_FLM; 901 plc &= ~PORT_LINK_CTRL_LC_MASK; 902 903 /* Set link width speed control register */ 904 lwsc = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL); 905 lwsc &= ~LINK_WIDTH_MASK; 906 lwsc |= LINK_WIDTH_1_LANES; 907 switch (num_lanes) { 908 case 1: 909 plc |= PORT_LINK_CTRL_LC_1_LANES; 910 break; 911 case 2: 912 plc |= PORT_LINK_CTRL_LC_2_LANES; 913 break; 914 case 4: 915 plc |= PORT_LINK_CTRL_LC_4_LANES; 916 break; 917 case 8: 918 plc |= PORT_LINK_CTRL_LC_8_LANES; 919 break; 920 case 16: 921 plc |= PORT_LINK_CTRL_LC_16_LANES; 922 break; 923 default: 924 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 925 return; 926 } 927 dw_pcie_writel_dbi(pci, PORT_LINK_CTRL, plc); 928 dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, lwsc); 929 930 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 931 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 932 FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); 933 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 934 } 935 936 void dw_pcie_iatu_detect(struct dw_pcie *pci) 937 { 938 int max_region, ob, ib; 939 u32 val, min, dir; 940 u64 max; 941 942 val = dw_pcie_readl_dbi(pci, IATU_VIEWPORT); 943 if (val == 0xFFFFFFFF) { 944 dw_pcie_cap_set(pci, IATU_UNROLL); 945 946 max_region = min((int)pci->atu_size / 512, 256); 947 } else { 948 pci->atu_base = pci->dbi_base + ATU_VIEWPORT_BASE; 949 pci->atu_size = ATU_VIEWPORT_SIZE; 950 951 dw_pcie_writel_dbi(pci, IATU_VIEWPORT, 0xFF); 952 max_region = dw_pcie_readl_dbi(pci, IATU_VIEWPORT) + 1; 953 } 954 955 for (ob = 0; ob < max_region; ob++) { 956 dw_pcie_writel_atu_ob(pci, ob, ATU_LOWER_TARGET, 0x11110000); 957 val = dw_pcie_readl_atu_ob(pci, ob, ATU_LOWER_TARGET); 958 if (val != 0x11110000) 959 break; 960 } 961 962 for (ib = 0; ib < max_region; ib++) { 963 dw_pcie_writel_atu_ib(pci, ib, ATU_LOWER_TARGET, 0x11110000); 964 val = dw_pcie_readl_atu_ib(pci, ib, ATU_LOWER_TARGET); 965 if (val != 0x11110000) 966 break; 967 } 968 969 if (ob) { 970 dir = ATU_REGION_DIR_OB; 971 } else if (ib) { 972 dir = ATU_REGION_DIR_IB; 973 } else { 974 dev_err(pci->dev, "No iATU regions found\n"); 975 return; 976 } 977 978 dw_pcie_writel_atu(pci, dir, 0, ATU_LIMIT, 0x0); 979 min = dw_pcie_readl_atu(pci, dir, 0, ATU_LIMIT); 980 981 if (dw_pcie_ver_is_ge(pci, 460A)) { 982 dw_pcie_writel_atu(pci, dir, 0, ATU_UPPER_LIMIT, 0xFFFFFFFF); 983 max = dw_pcie_readl_atu(pci, dir, 0, ATU_UPPER_LIMIT); 984 } else { 985 max = 0; 986 } 987 988 pci->num_ob_windows = ob; 989 pci->num_ib_windows = ib; 990 pci->region_align = 1 << fls(min); 991 pci->region_limit = (max << 32) | (SZ_4G - 1); 992 993 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 994 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 995 pci->num_ob_windows, pci->num_ib_windows, 996 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 997 } 998 999 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 1000 { 1001 u32 val = 0; 1002 int ret; 1003 1004 if (pci->ops && pci->ops->read_dbi) 1005 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 1006 1007 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 1008 if (ret) 1009 dev_err(pci->dev, "Read DMA address failed\n"); 1010 1011 return val; 1012 } 1013 1014 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 1015 { 1016 struct platform_device *pdev = to_platform_device(dev); 1017 char name[6]; 1018 int ret; 1019 1020 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 1021 return -EINVAL; 1022 1023 ret = platform_get_irq_byname_optional(pdev, "dma"); 1024 if (ret > 0) 1025 return ret; 1026 1027 snprintf(name, sizeof(name), "dma%u", nr); 1028 1029 return platform_get_irq_byname_optional(pdev, name); 1030 } 1031 1032 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 1033 .irq_vector = dw_pcie_edma_irq_vector, 1034 }; 1035 1036 static void dw_pcie_edma_init_data(struct dw_pcie *pci) 1037 { 1038 pci->edma.dev = pci->dev; 1039 1040 if (!pci->edma.ops) 1041 pci->edma.ops = &dw_pcie_edma_ops; 1042 1043 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 1044 } 1045 1046 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 1047 { 1048 u32 val; 1049 1050 /* 1051 * Bail out finding the mapping format if it is already set by the glue 1052 * driver. Also ensure that the edma.reg_base is pointing to a valid 1053 * memory region. 1054 */ 1055 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 1056 return pci->edma.reg_base ? 0 : -ENODEV; 1057 1058 /* 1059 * Indirect eDMA CSRs access has been completely removed since v5.40a 1060 * thus no space is now reserved for the eDMA channels viewport and 1061 * former DMA CTRL register is no longer fixed to FFs. 1062 */ 1063 if (dw_pcie_ver_is_ge(pci, 540A)) 1064 val = 0xFFFFFFFF; 1065 else 1066 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 1067 1068 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 1069 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 1070 } else if (val != 0xFFFFFFFF) { 1071 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 1072 1073 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 1074 } else { 1075 return -ENODEV; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 1082 { 1083 u32 val; 1084 1085 /* 1086 * Autodetect the read/write channels count only for non-HDMA platforms. 1087 * HDMA platforms with native CSR mapping doesn't support autodetect, 1088 * so the glue drivers should've passed the valid count already. If not, 1089 * the below sanity check will catch it. 1090 */ 1091 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 1092 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 1093 1094 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 1095 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 1096 } 1097 1098 /* Sanity check the channels count if the mapping was incorrect */ 1099 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 1100 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 1101 return -EINVAL; 1102 1103 return 0; 1104 } 1105 1106 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 1107 { 1108 int ret; 1109 1110 dw_pcie_edma_init_data(pci); 1111 1112 ret = dw_pcie_edma_find_mf(pci); 1113 if (ret) 1114 return ret; 1115 1116 return dw_pcie_edma_find_channels(pci); 1117 } 1118 1119 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 1120 { 1121 struct platform_device *pdev = to_platform_device(pci->dev); 1122 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 1123 char name[15]; 1124 int ret; 1125 1126 if (pci->edma.nr_irqs > 1) 1127 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 1128 1129 ret = platform_get_irq_byname_optional(pdev, "dma"); 1130 if (ret > 0) { 1131 pci->edma.nr_irqs = 1; 1132 return 0; 1133 } 1134 1135 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 1136 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 1137 1138 ret = platform_get_irq_byname_optional(pdev, name); 1139 if (ret <= 0) 1140 return -EINVAL; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 1147 { 1148 struct dw_edma_region *ll; 1149 dma_addr_t paddr; 1150 int i; 1151 1152 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1153 ll = &pci->edma.ll_region_wr[i]; 1154 ll->sz = DMA_LLP_MEM_SIZE; 1155 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1156 &paddr, GFP_KERNEL); 1157 if (!ll->vaddr.mem) 1158 return -ENOMEM; 1159 1160 ll->paddr = paddr; 1161 } 1162 1163 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1164 ll = &pci->edma.ll_region_rd[i]; 1165 ll->sz = DMA_LLP_MEM_SIZE; 1166 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1167 &paddr, GFP_KERNEL); 1168 if (!ll->vaddr.mem) 1169 return -ENOMEM; 1170 1171 ll->paddr = paddr; 1172 } 1173 1174 return 0; 1175 } 1176 1177 int dw_pcie_edma_detect(struct dw_pcie *pci) 1178 { 1179 int ret; 1180 1181 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1182 ret = dw_pcie_edma_find_chip(pci); 1183 if (ret) 1184 return 0; 1185 1186 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1187 ret = dw_pcie_edma_irq_verify(pci); 1188 if (ret) { 1189 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1190 return 0; 1191 } 1192 1193 ret = dw_pcie_edma_ll_alloc(pci); 1194 if (ret) { 1195 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1196 return ret; 1197 } 1198 1199 /* Don't fail if the DW eDMA driver can't find the device */ 1200 ret = dw_edma_probe(&pci->edma); 1201 if (ret && ret != -ENODEV) { 1202 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1203 return ret; 1204 } 1205 1206 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1207 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1208 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1209 1210 return 0; 1211 } 1212 1213 void dw_pcie_edma_remove(struct dw_pcie *pci) 1214 { 1215 dw_edma_remove(&pci->edma); 1216 } 1217 1218 void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) 1219 { 1220 u16 l1ss; 1221 u32 l1ss_cap; 1222 1223 if (pci->l1ss_support) 1224 return; 1225 1226 l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1227 if (!l1ss) 1228 return; 1229 1230 /* 1231 * Unless the driver claims "l1ss_support", don't advertise L1 PM 1232 * Substates because they require CLKREQ# and possibly other 1233 * device-specific configuration. 1234 */ 1235 l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); 1236 l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | 1237 PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | 1238 PCI_L1SS_CAP_L1_PM_SS); 1239 dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); 1240 } 1241 1242 /* TODO: Need to handle multi Root Ports */ 1243 void dw_pcie_program_t_power_on(struct dw_pcie *pci, u32 t_power_on) 1244 { 1245 u8 scale, value; 1246 u16 offset; 1247 u32 val; 1248 1249 if (!t_power_on) 1250 return; 1251 1252 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1253 if (!offset) 1254 return; 1255 1256 pcie_encode_t_power_on(t_power_on, &scale, &value); 1257 1258 dw_pcie_dbi_ro_wr_en(pci); 1259 1260 val = dw_pcie_readl_dbi(pci, offset + PCI_L1SS_CAP); 1261 val &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); 1262 FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale); 1263 FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value); 1264 1265 dw_pcie_writel_dbi(pci, offset + PCI_L1SS_CAP, val); 1266 1267 dw_pcie_dbi_ro_wr_dis(pci); 1268 } 1269 1270 void dw_pcie_setup(struct dw_pcie *pci) 1271 { 1272 u32 val; 1273 1274 dw_pcie_link_set_max_speed(pci); 1275 1276 /* Configure Gen1 N_FTS */ 1277 if (pci->n_fts[0]) { 1278 val = dw_pcie_readl_dbi(pci, PORT_AFAC); 1279 val &= ~(PORT_AFAC_N_FTS_MASK | PORT_AFAC_CC_N_FTS_MASK); 1280 val |= PORT_AFAC_N_FTS(pci->n_fts[0]); 1281 val |= PORT_AFAC_CC_N_FTS(pci->n_fts[0]); 1282 dw_pcie_writel_dbi(pci, PORT_AFAC, val); 1283 } 1284 1285 /* Configure Gen2+ N_FTS */ 1286 if (pci->n_fts[1]) { 1287 val = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL); 1288 val &= ~N_FTS_MASK; 1289 val |= pci->n_fts[1]; 1290 dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, val); 1291 } 1292 1293 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1294 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1295 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1296 PCIE_PL_CHK_REG_CHK_REG_START; 1297 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1298 } 1299 1300 val = dw_pcie_readl_dbi(pci, PORT_LINK_CTRL); 1301 val &= ~PORT_LINK_CTRL_FLM; 1302 val |= PORT_LINK_CTRL_DLE; 1303 dw_pcie_writel_dbi(pci, PORT_LINK_CTRL, val); 1304 1305 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1306 } 1307 1308 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci, 1309 const char *reg_name, 1310 resource_size_t cpu_phys_addr) 1311 { 1312 struct device *dev = pci->dev; 1313 struct device_node *np = dev->of_node; 1314 int index; 1315 u64 reg_addr, fixup_addr; 1316 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr); 1317 1318 /* Look up reg_name address on parent bus */ 1319 index = of_property_match_string(np, "reg-names", reg_name); 1320 1321 if (index < 0) { 1322 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name); 1323 return 0; 1324 } 1325 1326 of_property_read_reg(np, index, ®_addr, NULL); 1327 1328 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL; 1329 if (fixup) { 1330 fixup_addr = fixup(pci, cpu_phys_addr); 1331 if (reg_addr == fixup_addr) { 1332 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n", 1333 reg_name, index, reg_addr, fixup_addr, 1334 (unsigned long long) cpu_phys_addr, fixup); 1335 } else { 1336 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n", 1337 reg_name, index, reg_addr, fixup_addr, 1338 (unsigned long long) cpu_phys_addr); 1339 reg_addr = fixup_addr; 1340 } 1341 1342 return cpu_phys_addr - reg_addr; 1343 } 1344 1345 if (pci->use_parent_dt_ranges) { 1346 1347 /* 1348 * This platform once had a fixup, presumably because it 1349 * translates between CPU and PCI controller addresses. 1350 * Log a note if devicetree didn't describe a translation. 1351 */ 1352 if (reg_addr == cpu_phys_addr) 1353 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n", 1354 reg_name, index, reg_addr, 1355 (unsigned long long) cpu_phys_addr); 1356 } else { 1357 if (reg_addr != cpu_phys_addr) { 1358 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n", 1359 reg_name, index, reg_addr, 1360 (unsigned long long) cpu_phys_addr); 1361 return 0; 1362 } 1363 } 1364 1365 return cpu_phys_addr - reg_addr; 1366 } 1367