1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/iopoll.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/msi.h> 15 #include <linux/of_address.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci_regs.h> 18 #include <linux/platform_device.h> 19 20 #include "../../pci.h" 21 #include "pcie-designware.h" 22 23 static struct pci_ops dw_pcie_ops; 24 static struct pci_ops dw_child_pcie_ops; 25 26 static void dw_msi_ack_irq(struct irq_data *d) 27 { 28 irq_chip_ack_parent(d); 29 } 30 31 static void dw_msi_mask_irq(struct irq_data *d) 32 { 33 pci_msi_mask_irq(d); 34 irq_chip_mask_parent(d); 35 } 36 37 static void dw_msi_unmask_irq(struct irq_data *d) 38 { 39 pci_msi_unmask_irq(d); 40 irq_chip_unmask_parent(d); 41 } 42 43 static struct irq_chip dw_pcie_msi_irq_chip = { 44 .name = "PCI-MSI", 45 .irq_ack = dw_msi_ack_irq, 46 .irq_mask = dw_msi_mask_irq, 47 .irq_unmask = dw_msi_unmask_irq, 48 }; 49 50 static struct msi_domain_info dw_pcie_msi_domain_info = { 51 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 52 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 53 .chip = &dw_pcie_msi_irq_chip, 54 }; 55 56 /* MSI int handler */ 57 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) 58 { 59 int i, pos; 60 unsigned long val; 61 u32 status, num_ctrls; 62 irqreturn_t ret = IRQ_NONE; 63 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 64 65 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 66 67 for (i = 0; i < num_ctrls; i++) { 68 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 69 (i * MSI_REG_CTRL_BLOCK_SIZE)); 70 if (!status) 71 continue; 72 73 ret = IRQ_HANDLED; 74 val = status; 75 pos = 0; 76 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 77 pos)) != MAX_MSI_IRQS_PER_CTRL) { 78 generic_handle_domain_irq(pp->irq_domain, 79 (i * MAX_MSI_IRQS_PER_CTRL) + 80 pos); 81 pos++; 82 } 83 } 84 85 return ret; 86 } 87 88 /* Chained MSI interrupt service routine */ 89 static void dw_chained_msi_isr(struct irq_desc *desc) 90 { 91 struct irq_chip *chip = irq_desc_get_chip(desc); 92 struct dw_pcie_rp *pp; 93 94 chained_irq_enter(chip, desc); 95 96 pp = irq_desc_get_handler_data(desc); 97 dw_handle_msi_irq(pp); 98 99 chained_irq_exit(chip, desc); 100 } 101 102 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 103 { 104 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 106 u64 msi_target; 107 108 msi_target = (u64)pp->msi_data; 109 110 msg->address_lo = lower_32_bits(msi_target); 111 msg->address_hi = upper_32_bits(msi_target); 112 113 msg->data = d->hwirq; 114 115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 116 (int)d->hwirq, msg->address_hi, msg->address_lo); 117 } 118 119 static int dw_pci_msi_set_affinity(struct irq_data *d, 120 const struct cpumask *mask, bool force) 121 { 122 return -EINVAL; 123 } 124 125 static void dw_pci_bottom_mask(struct irq_data *d) 126 { 127 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 129 unsigned int res, bit, ctrl; 130 unsigned long flags; 131 132 raw_spin_lock_irqsave(&pp->lock, flags); 133 134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 137 138 pp->irq_mask[ctrl] |= BIT(bit); 139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 140 141 raw_spin_unlock_irqrestore(&pp->lock, flags); 142 } 143 144 static void dw_pci_bottom_unmask(struct irq_data *d) 145 { 146 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 148 unsigned int res, bit, ctrl; 149 unsigned long flags; 150 151 raw_spin_lock_irqsave(&pp->lock, flags); 152 153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 156 157 pp->irq_mask[ctrl] &= ~BIT(bit); 158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 159 160 raw_spin_unlock_irqrestore(&pp->lock, flags); 161 } 162 163 static void dw_pci_bottom_ack(struct irq_data *d) 164 { 165 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 167 unsigned int res, bit, ctrl; 168 169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 172 173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 174 } 175 176 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 177 .name = "DWPCI-MSI", 178 .irq_ack = dw_pci_bottom_ack, 179 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 180 .irq_set_affinity = dw_pci_msi_set_affinity, 181 .irq_mask = dw_pci_bottom_mask, 182 .irq_unmask = dw_pci_bottom_unmask, 183 }; 184 185 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 186 unsigned int virq, unsigned int nr_irqs, 187 void *args) 188 { 189 struct dw_pcie_rp *pp = domain->host_data; 190 unsigned long flags; 191 u32 i; 192 int bit; 193 194 raw_spin_lock_irqsave(&pp->lock, flags); 195 196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 197 order_base_2(nr_irqs)); 198 199 raw_spin_unlock_irqrestore(&pp->lock, flags); 200 201 if (bit < 0) 202 return -ENOSPC; 203 204 for (i = 0; i < nr_irqs; i++) 205 irq_domain_set_info(domain, virq + i, bit + i, 206 pp->msi_irq_chip, 207 pp, handle_edge_irq, 208 NULL, NULL); 209 210 return 0; 211 } 212 213 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 214 unsigned int virq, unsigned int nr_irqs) 215 { 216 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 217 struct dw_pcie_rp *pp = domain->host_data; 218 unsigned long flags; 219 220 raw_spin_lock_irqsave(&pp->lock, flags); 221 222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 223 order_base_2(nr_irqs)); 224 225 raw_spin_unlock_irqrestore(&pp->lock, flags); 226 } 227 228 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 229 .alloc = dw_pcie_irq_domain_alloc, 230 .free = dw_pcie_irq_domain_free, 231 }; 232 233 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) 234 { 235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 237 238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 239 &dw_pcie_msi_domain_ops, pp); 240 if (!pp->irq_domain) { 241 dev_err(pci->dev, "Failed to create IRQ domain\n"); 242 return -ENOMEM; 243 } 244 245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 246 247 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 248 &dw_pcie_msi_domain_info, 249 pp->irq_domain); 250 if (!pp->msi_domain) { 251 dev_err(pci->dev, "Failed to create MSI domain\n"); 252 irq_domain_remove(pp->irq_domain); 253 return -ENOMEM; 254 } 255 256 return 0; 257 } 258 259 static void dw_pcie_free_msi(struct dw_pcie_rp *pp) 260 { 261 u32 ctrl; 262 263 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 264 if (pp->msi_irq[ctrl] > 0) 265 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 266 NULL, NULL); 267 } 268 269 irq_domain_remove(pp->msi_domain); 270 irq_domain_remove(pp->irq_domain); 271 } 272 273 static void dw_pcie_msi_init(struct dw_pcie_rp *pp) 274 { 275 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 276 u64 msi_target = (u64)pp->msi_data; 277 278 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 279 return; 280 281 /* Program the msi_data */ 282 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 283 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 284 } 285 286 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) 287 { 288 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 289 struct device *dev = pci->dev; 290 struct platform_device *pdev = to_platform_device(dev); 291 u32 ctrl, max_vectors; 292 int irq; 293 294 /* Parse any "msiX" IRQs described in the devicetree */ 295 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 296 char msi_name[] = "msiX"; 297 298 msi_name[3] = '0' + ctrl; 299 irq = platform_get_irq_byname_optional(pdev, msi_name); 300 if (irq == -ENXIO) 301 break; 302 if (irq < 0) 303 return dev_err_probe(dev, irq, 304 "Failed to parse MSI IRQ '%s'\n", 305 msi_name); 306 307 pp->msi_irq[ctrl] = irq; 308 } 309 310 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */ 311 if (ctrl == 0) 312 return -ENXIO; 313 314 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; 315 if (pp->num_vectors > max_vectors) { 316 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", 317 max_vectors); 318 pp->num_vectors = max_vectors; 319 } 320 if (!pp->num_vectors) 321 pp->num_vectors = max_vectors; 322 323 return 0; 324 } 325 326 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) 327 { 328 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 329 struct device *dev = pci->dev; 330 struct platform_device *pdev = to_platform_device(dev); 331 u64 *msi_vaddr = NULL; 332 int ret; 333 u32 ctrl, num_ctrls; 334 335 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) 336 pp->irq_mask[ctrl] = ~0; 337 338 if (!pp->msi_irq[0]) { 339 ret = dw_pcie_parse_split_msi_irq(pp); 340 if (ret < 0 && ret != -ENXIO) 341 return ret; 342 } 343 344 if (!pp->num_vectors) 345 pp->num_vectors = MSI_DEF_NUM_VECTORS; 346 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 347 348 if (!pp->msi_irq[0]) { 349 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); 350 if (pp->msi_irq[0] < 0) { 351 pp->msi_irq[0] = platform_get_irq(pdev, 0); 352 if (pp->msi_irq[0] < 0) 353 return pp->msi_irq[0]; 354 } 355 } 356 357 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); 358 359 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 360 361 ret = dw_pcie_allocate_domains(pp); 362 if (ret) 363 return ret; 364 365 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 366 if (pp->msi_irq[ctrl] > 0) 367 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 368 dw_chained_msi_isr, pp); 369 } 370 371 /* 372 * Even though the iMSI-RX Module supports 64-bit addresses some 373 * peripheral PCIe devices may lack 64-bit message support. In 374 * order not to miss MSI TLPs from those devices the MSI target 375 * address has to be within the lowest 4GB. 376 * 377 * Note until there is a better alternative found the reservation is 378 * done by allocating from the artificially limited DMA-coherent 379 * memory. 380 */ 381 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 382 if (!ret) 383 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, 384 GFP_KERNEL); 385 386 if (!msi_vaddr) { 387 dev_warn(dev, "Failed to allocate 32-bit MSI address\n"); 388 dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); 389 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, 390 GFP_KERNEL); 391 if (!msi_vaddr) { 392 dev_err(dev, "Failed to allocate MSI address\n"); 393 dw_pcie_free_msi(pp); 394 return -ENOMEM; 395 } 396 } 397 398 return 0; 399 } 400 401 int dw_pcie_host_init(struct dw_pcie_rp *pp) 402 { 403 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 404 struct device *dev = pci->dev; 405 struct device_node *np = dev->of_node; 406 struct platform_device *pdev = to_platform_device(dev); 407 struct resource_entry *win; 408 struct pci_host_bridge *bridge; 409 struct resource *res; 410 int ret; 411 412 raw_spin_lock_init(&pp->lock); 413 414 ret = dw_pcie_get_resources(pci); 415 if (ret) 416 return ret; 417 418 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 419 if (res) { 420 pp->cfg0_size = resource_size(res); 421 pp->cfg0_base = res->start; 422 423 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 424 if (IS_ERR(pp->va_cfg0_base)) 425 return PTR_ERR(pp->va_cfg0_base); 426 } else { 427 dev_err(dev, "Missing *config* reg space\n"); 428 return -ENODEV; 429 } 430 431 bridge = devm_pci_alloc_host_bridge(dev, 0); 432 if (!bridge) 433 return -ENOMEM; 434 435 pp->bridge = bridge; 436 437 /* Get the I/O range from DT */ 438 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 439 if (win) { 440 pp->io_size = resource_size(win->res); 441 pp->io_bus_addr = win->res->start - win->offset; 442 pp->io_base = pci_pio_to_address(win->res->start); 443 } 444 445 /* Set default bus ops */ 446 bridge->ops = &dw_pcie_ops; 447 bridge->child_ops = &dw_child_pcie_ops; 448 449 if (pp->ops->init) { 450 ret = pp->ops->init(pp); 451 if (ret) 452 return ret; 453 } 454 455 if (pci_msi_enabled()) { 456 pp->has_msi_ctrl = !(pp->ops->msi_init || 457 of_property_read_bool(np, "msi-parent") || 458 of_property_read_bool(np, "msi-map")); 459 460 /* 461 * For the has_msi_ctrl case the default assignment is handled 462 * in the dw_pcie_msi_host_init(). 463 */ 464 if (!pp->has_msi_ctrl && !pp->num_vectors) { 465 pp->num_vectors = MSI_DEF_NUM_VECTORS; 466 } else if (pp->num_vectors > MAX_MSI_IRQS) { 467 dev_err(dev, "Invalid number of vectors\n"); 468 ret = -EINVAL; 469 goto err_deinit_host; 470 } 471 472 if (pp->ops->msi_init) { 473 ret = pp->ops->msi_init(pp); 474 if (ret < 0) 475 goto err_deinit_host; 476 } else if (pp->has_msi_ctrl) { 477 ret = dw_pcie_msi_host_init(pp); 478 if (ret < 0) 479 goto err_deinit_host; 480 } 481 } 482 483 dw_pcie_version_detect(pci); 484 485 dw_pcie_iatu_detect(pci); 486 487 ret = dw_pcie_edma_detect(pci); 488 if (ret) 489 goto err_free_msi; 490 491 ret = dw_pcie_setup_rc(pp); 492 if (ret) 493 goto err_remove_edma; 494 495 if (!dw_pcie_link_up(pci)) { 496 ret = dw_pcie_start_link(pci); 497 if (ret) 498 goto err_remove_edma; 499 } 500 501 /* Ignore errors, the link may come up later */ 502 dw_pcie_wait_for_link(pci); 503 504 bridge->sysdata = pp; 505 506 ret = pci_host_probe(bridge); 507 if (ret) 508 goto err_stop_link; 509 510 if (pp->ops->post_init) 511 pp->ops->post_init(pp); 512 513 return 0; 514 515 err_stop_link: 516 dw_pcie_stop_link(pci); 517 518 err_remove_edma: 519 dw_pcie_edma_remove(pci); 520 521 err_free_msi: 522 if (pp->has_msi_ctrl) 523 dw_pcie_free_msi(pp); 524 525 err_deinit_host: 526 if (pp->ops->deinit) 527 pp->ops->deinit(pp); 528 529 return ret; 530 } 531 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 532 533 void dw_pcie_host_deinit(struct dw_pcie_rp *pp) 534 { 535 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 536 537 pci_stop_root_bus(pp->bridge->bus); 538 pci_remove_root_bus(pp->bridge->bus); 539 540 dw_pcie_stop_link(pci); 541 542 dw_pcie_edma_remove(pci); 543 544 if (pp->has_msi_ctrl) 545 dw_pcie_free_msi(pp); 546 547 if (pp->ops->deinit) 548 pp->ops->deinit(pp); 549 } 550 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 551 552 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 553 unsigned int devfn, int where) 554 { 555 struct dw_pcie_rp *pp = bus->sysdata; 556 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 557 int type, ret; 558 u32 busdev; 559 560 /* 561 * Checking whether the link is up here is a last line of defense 562 * against platforms that forward errors on the system bus as 563 * SError upon PCI configuration transactions issued when the link 564 * is down. This check is racy by definition and does not stop 565 * the system from triggering an SError if the link goes down 566 * after this check is performed. 567 */ 568 if (!dw_pcie_link_up(pci)) 569 return NULL; 570 571 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 572 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 573 574 if (pci_is_root_bus(bus->parent)) 575 type = PCIE_ATU_TYPE_CFG0; 576 else 577 type = PCIE_ATU_TYPE_CFG1; 578 579 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, 580 pp->cfg0_size); 581 if (ret) 582 return NULL; 583 584 return pp->va_cfg0_base + where; 585 } 586 587 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 588 int where, int size, u32 *val) 589 { 590 struct dw_pcie_rp *pp = bus->sysdata; 591 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 592 int ret; 593 594 ret = pci_generic_config_read(bus, devfn, where, size, val); 595 if (ret != PCIBIOS_SUCCESSFUL) 596 return ret; 597 598 if (pp->cfg0_io_shared) { 599 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 600 pp->io_base, pp->io_bus_addr, 601 pp->io_size); 602 if (ret) 603 return PCIBIOS_SET_FAILED; 604 } 605 606 return PCIBIOS_SUCCESSFUL; 607 } 608 609 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 610 int where, int size, u32 val) 611 { 612 struct dw_pcie_rp *pp = bus->sysdata; 613 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 614 int ret; 615 616 ret = pci_generic_config_write(bus, devfn, where, size, val); 617 if (ret != PCIBIOS_SUCCESSFUL) 618 return ret; 619 620 if (pp->cfg0_io_shared) { 621 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 622 pp->io_base, pp->io_bus_addr, 623 pp->io_size); 624 if (ret) 625 return PCIBIOS_SET_FAILED; 626 } 627 628 return PCIBIOS_SUCCESSFUL; 629 } 630 631 static struct pci_ops dw_child_pcie_ops = { 632 .map_bus = dw_pcie_other_conf_map_bus, 633 .read = dw_pcie_rd_other_conf, 634 .write = dw_pcie_wr_other_conf, 635 }; 636 637 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 638 { 639 struct dw_pcie_rp *pp = bus->sysdata; 640 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 641 642 if (PCI_SLOT(devfn) > 0) 643 return NULL; 644 645 return pci->dbi_base + where; 646 } 647 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 648 649 static struct pci_ops dw_pcie_ops = { 650 .map_bus = dw_pcie_own_conf_map_bus, 651 .read = pci_generic_config_read, 652 .write = pci_generic_config_write, 653 }; 654 655 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) 656 { 657 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 658 struct resource_entry *entry; 659 int i, ret; 660 661 /* Note the very first outbound ATU is used for CFG IOs */ 662 if (!pci->num_ob_windows) { 663 dev_err(pci->dev, "No outbound iATU found\n"); 664 return -EINVAL; 665 } 666 667 /* 668 * Ensure all out/inbound windows are disabled before proceeding with 669 * the MEM/IO (dma-)ranges setups. 670 */ 671 for (i = 0; i < pci->num_ob_windows; i++) 672 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i); 673 674 for (i = 0; i < pci->num_ib_windows; i++) 675 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i); 676 677 i = 0; 678 resource_list_for_each_entry(entry, &pp->bridge->windows) { 679 if (resource_type(entry->res) != IORESOURCE_MEM) 680 continue; 681 682 if (pci->num_ob_windows <= ++i) 683 break; 684 685 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, 686 entry->res->start, 687 entry->res->start - entry->offset, 688 resource_size(entry->res)); 689 if (ret) { 690 dev_err(pci->dev, "Failed to set MEM range %pr\n", 691 entry->res); 692 return ret; 693 } 694 } 695 696 if (pp->io_size) { 697 if (pci->num_ob_windows > ++i) { 698 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, 699 pp->io_base, 700 pp->io_bus_addr, 701 pp->io_size); 702 if (ret) { 703 dev_err(pci->dev, "Failed to set IO range %pr\n", 704 entry->res); 705 return ret; 706 } 707 } else { 708 pp->cfg0_io_shared = true; 709 } 710 } 711 712 if (pci->num_ob_windows <= i) 713 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", 714 pci->num_ob_windows); 715 716 i = 0; 717 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { 718 if (resource_type(entry->res) != IORESOURCE_MEM) 719 continue; 720 721 if (pci->num_ib_windows <= i) 722 break; 723 724 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, 725 entry->res->start, 726 entry->res->start - entry->offset, 727 resource_size(entry->res)); 728 if (ret) { 729 dev_err(pci->dev, "Failed to set DMA range %pr\n", 730 entry->res); 731 return ret; 732 } 733 } 734 735 if (pci->num_ib_windows <= i) 736 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n", 737 pci->num_ib_windows); 738 739 return 0; 740 } 741 742 int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 743 { 744 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 745 u32 val, ctrl, num_ctrls; 746 int ret; 747 748 /* 749 * Enable DBI read-only registers for writing/updating configuration. 750 * Write permission gets disabled towards the end of this function. 751 */ 752 dw_pcie_dbi_ro_wr_en(pci); 753 754 dw_pcie_setup(pci); 755 756 if (pp->has_msi_ctrl) { 757 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 758 759 /* Initialize IRQ Status array */ 760 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 761 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 762 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 763 pp->irq_mask[ctrl]); 764 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 765 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 766 ~0); 767 } 768 } 769 770 dw_pcie_msi_init(pp); 771 772 /* Setup RC BARs */ 773 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 774 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 775 776 /* Setup interrupt pins */ 777 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 778 val &= 0xffff00ff; 779 val |= 0x00000100; 780 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 781 782 /* Setup bus numbers */ 783 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 784 val &= 0xff000000; 785 val |= 0x00ff0100; 786 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 787 788 /* Setup command register */ 789 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 790 val &= 0xffff0000; 791 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 792 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 793 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 794 795 /* 796 * If the platform provides its own child bus config accesses, it means 797 * the platform uses its own address translation component rather than 798 * ATU, so we should not program the ATU here. 799 */ 800 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 801 ret = dw_pcie_iatu_setup(pp); 802 if (ret) 803 return ret; 804 } 805 806 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 807 808 /* Program correct class for RC */ 809 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 810 811 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 812 val |= PORT_LOGIC_SPEED_CHANGE; 813 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 814 815 dw_pcie_dbi_ro_wr_dis(pci); 816 817 return 0; 818 } 819 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 820 821 int dw_pcie_suspend_noirq(struct dw_pcie *pci) 822 { 823 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 824 u32 val; 825 int ret; 826 827 /* 828 * If L1SS is supported, then do not put the link into L2 as some 829 * devices such as NVMe expect low resume latency. 830 */ 831 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) 832 return 0; 833 834 if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) 835 return 0; 836 837 if (!pci->pp.ops->pme_turn_off) 838 return 0; 839 840 pci->pp.ops->pme_turn_off(&pci->pp); 841 842 ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, 843 PCIE_PME_TO_L2_TIMEOUT_US/10, 844 PCIE_PME_TO_L2_TIMEOUT_US, false, pci); 845 if (ret) { 846 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); 847 return ret; 848 } 849 850 if (pci->pp.ops->deinit) 851 pci->pp.ops->deinit(&pci->pp); 852 853 pci->suspended = true; 854 855 return ret; 856 } 857 EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); 858 859 int dw_pcie_resume_noirq(struct dw_pcie *pci) 860 { 861 int ret; 862 863 if (!pci->suspended) 864 return 0; 865 866 pci->suspended = false; 867 868 if (pci->pp.ops->init) { 869 ret = pci->pp.ops->init(&pci->pp); 870 if (ret) { 871 dev_err(pci->dev, "Host init failed: %d\n", ret); 872 return ret; 873 } 874 } 875 876 dw_pcie_setup_rc(&pci->pp); 877 878 ret = dw_pcie_start_link(pci); 879 if (ret) 880 return ret; 881 882 ret = dw_pcie_wait_for_link(pci); 883 if (ret) 884 return ret; 885 886 return ret; 887 } 888 EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); 889