1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/iopoll.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/msi.h> 15 #include <linux/of_address.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci_regs.h> 18 #include <linux/platform_device.h> 19 20 #include "../../pci.h" 21 #include "pcie-designware.h" 22 23 static struct pci_ops dw_pcie_ops; 24 static struct pci_ops dw_child_pcie_ops; 25 26 static void dw_msi_ack_irq(struct irq_data *d) 27 { 28 irq_chip_ack_parent(d); 29 } 30 31 static void dw_msi_mask_irq(struct irq_data *d) 32 { 33 pci_msi_mask_irq(d); 34 irq_chip_mask_parent(d); 35 } 36 37 static void dw_msi_unmask_irq(struct irq_data *d) 38 { 39 pci_msi_unmask_irq(d); 40 irq_chip_unmask_parent(d); 41 } 42 43 static struct irq_chip dw_pcie_msi_irq_chip = { 44 .name = "PCI-MSI", 45 .irq_ack = dw_msi_ack_irq, 46 .irq_mask = dw_msi_mask_irq, 47 .irq_unmask = dw_msi_unmask_irq, 48 }; 49 50 static struct msi_domain_info dw_pcie_msi_domain_info = { 51 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 52 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX | 53 MSI_FLAG_MULTI_PCI_MSI, 54 .chip = &dw_pcie_msi_irq_chip, 55 }; 56 57 /* MSI int handler */ 58 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) 59 { 60 int i, pos; 61 unsigned long val; 62 u32 status, num_ctrls; 63 irqreturn_t ret = IRQ_NONE; 64 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 65 66 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 67 68 for (i = 0; i < num_ctrls; i++) { 69 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 70 (i * MSI_REG_CTRL_BLOCK_SIZE)); 71 if (!status) 72 continue; 73 74 ret = IRQ_HANDLED; 75 val = status; 76 pos = 0; 77 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 78 pos)) != MAX_MSI_IRQS_PER_CTRL) { 79 generic_handle_domain_irq(pp->irq_domain, 80 (i * MAX_MSI_IRQS_PER_CTRL) + 81 pos); 82 pos++; 83 } 84 } 85 86 return ret; 87 } 88 89 /* Chained MSI interrupt service routine */ 90 static void dw_chained_msi_isr(struct irq_desc *desc) 91 { 92 struct irq_chip *chip = irq_desc_get_chip(desc); 93 struct dw_pcie_rp *pp; 94 95 chained_irq_enter(chip, desc); 96 97 pp = irq_desc_get_handler_data(desc); 98 dw_handle_msi_irq(pp); 99 100 chained_irq_exit(chip, desc); 101 } 102 103 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 104 { 105 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 106 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 107 u64 msi_target; 108 109 msi_target = (u64)pp->msi_data; 110 111 msg->address_lo = lower_32_bits(msi_target); 112 msg->address_hi = upper_32_bits(msi_target); 113 114 msg->data = d->hwirq; 115 116 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 117 (int)d->hwirq, msg->address_hi, msg->address_lo); 118 } 119 120 static void dw_pci_bottom_mask(struct irq_data *d) 121 { 122 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 123 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 124 unsigned int res, bit, ctrl; 125 unsigned long flags; 126 127 raw_spin_lock_irqsave(&pp->lock, flags); 128 129 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 130 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 131 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 132 133 pp->irq_mask[ctrl] |= BIT(bit); 134 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 135 136 raw_spin_unlock_irqrestore(&pp->lock, flags); 137 } 138 139 static void dw_pci_bottom_unmask(struct irq_data *d) 140 { 141 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 142 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 143 unsigned int res, bit, ctrl; 144 unsigned long flags; 145 146 raw_spin_lock_irqsave(&pp->lock, flags); 147 148 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 149 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 150 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 151 152 pp->irq_mask[ctrl] &= ~BIT(bit); 153 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 154 155 raw_spin_unlock_irqrestore(&pp->lock, flags); 156 } 157 158 static void dw_pci_bottom_ack(struct irq_data *d) 159 { 160 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 161 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 162 unsigned int res, bit, ctrl; 163 164 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 165 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 166 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 167 168 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 169 } 170 171 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 172 .name = "DWPCI-MSI", 173 .irq_ack = dw_pci_bottom_ack, 174 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 175 .irq_mask = dw_pci_bottom_mask, 176 .irq_unmask = dw_pci_bottom_unmask, 177 }; 178 179 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 180 unsigned int virq, unsigned int nr_irqs, 181 void *args) 182 { 183 struct dw_pcie_rp *pp = domain->host_data; 184 unsigned long flags; 185 u32 i; 186 int bit; 187 188 raw_spin_lock_irqsave(&pp->lock, flags); 189 190 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 191 order_base_2(nr_irqs)); 192 193 raw_spin_unlock_irqrestore(&pp->lock, flags); 194 195 if (bit < 0) 196 return -ENOSPC; 197 198 for (i = 0; i < nr_irqs; i++) 199 irq_domain_set_info(domain, virq + i, bit + i, 200 pp->msi_irq_chip, 201 pp, handle_edge_irq, 202 NULL, NULL); 203 204 return 0; 205 } 206 207 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 208 unsigned int virq, unsigned int nr_irqs) 209 { 210 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 211 struct dw_pcie_rp *pp = domain->host_data; 212 unsigned long flags; 213 214 raw_spin_lock_irqsave(&pp->lock, flags); 215 216 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 217 order_base_2(nr_irqs)); 218 219 raw_spin_unlock_irqrestore(&pp->lock, flags); 220 } 221 222 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 223 .alloc = dw_pcie_irq_domain_alloc, 224 .free = dw_pcie_irq_domain_free, 225 }; 226 227 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) 228 { 229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 230 struct fwnode_handle *fwnode = of_fwnode_handle(pci->dev->of_node); 231 232 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 233 &dw_pcie_msi_domain_ops, pp); 234 if (!pp->irq_domain) { 235 dev_err(pci->dev, "Failed to create IRQ domain\n"); 236 return -ENOMEM; 237 } 238 239 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 240 241 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 242 &dw_pcie_msi_domain_info, 243 pp->irq_domain); 244 if (!pp->msi_domain) { 245 dev_err(pci->dev, "Failed to create MSI domain\n"); 246 irq_domain_remove(pp->irq_domain); 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static void dw_pcie_free_msi(struct dw_pcie_rp *pp) 254 { 255 u32 ctrl; 256 257 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 258 if (pp->msi_irq[ctrl] > 0) 259 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 260 NULL, NULL); 261 } 262 263 irq_domain_remove(pp->msi_domain); 264 irq_domain_remove(pp->irq_domain); 265 } 266 267 static void dw_pcie_msi_init(struct dw_pcie_rp *pp) 268 { 269 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 270 u64 msi_target = (u64)pp->msi_data; 271 272 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 273 return; 274 275 /* Program the msi_data */ 276 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 277 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 278 } 279 280 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) 281 { 282 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 283 struct device *dev = pci->dev; 284 struct platform_device *pdev = to_platform_device(dev); 285 u32 ctrl, max_vectors; 286 int irq; 287 288 /* Parse any "msiX" IRQs described in the devicetree */ 289 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 290 char msi_name[] = "msiX"; 291 292 msi_name[3] = '0' + ctrl; 293 irq = platform_get_irq_byname_optional(pdev, msi_name); 294 if (irq == -ENXIO) 295 break; 296 if (irq < 0) 297 return dev_err_probe(dev, irq, 298 "Failed to parse MSI IRQ '%s'\n", 299 msi_name); 300 301 pp->msi_irq[ctrl] = irq; 302 } 303 304 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */ 305 if (ctrl == 0) 306 return -ENXIO; 307 308 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; 309 if (pp->num_vectors > max_vectors) { 310 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", 311 max_vectors); 312 pp->num_vectors = max_vectors; 313 } 314 if (!pp->num_vectors) 315 pp->num_vectors = max_vectors; 316 317 return 0; 318 } 319 320 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) 321 { 322 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 323 struct device *dev = pci->dev; 324 struct platform_device *pdev = to_platform_device(dev); 325 u64 *msi_vaddr = NULL; 326 int ret; 327 u32 ctrl, num_ctrls; 328 329 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) 330 pp->irq_mask[ctrl] = ~0; 331 332 if (!pp->msi_irq[0]) { 333 ret = dw_pcie_parse_split_msi_irq(pp); 334 if (ret < 0 && ret != -ENXIO) 335 return ret; 336 } 337 338 if (!pp->num_vectors) 339 pp->num_vectors = MSI_DEF_NUM_VECTORS; 340 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 341 342 if (!pp->msi_irq[0]) { 343 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); 344 if (pp->msi_irq[0] < 0) { 345 pp->msi_irq[0] = platform_get_irq(pdev, 0); 346 if (pp->msi_irq[0] < 0) 347 return pp->msi_irq[0]; 348 } 349 } 350 351 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); 352 353 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 354 355 ret = dw_pcie_allocate_domains(pp); 356 if (ret) 357 return ret; 358 359 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 360 if (pp->msi_irq[ctrl] > 0) 361 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 362 dw_chained_msi_isr, pp); 363 } 364 365 /* 366 * Even though the iMSI-RX Module supports 64-bit addresses some 367 * peripheral PCIe devices may lack 64-bit message support. In 368 * order not to miss MSI TLPs from those devices the MSI target 369 * address has to be within the lowest 4GB. 370 * 371 * Note until there is a better alternative found the reservation is 372 * done by allocating from the artificially limited DMA-coherent 373 * memory. 374 */ 375 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 376 if (!ret) 377 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, 378 GFP_KERNEL); 379 380 if (!msi_vaddr) { 381 dev_warn(dev, "Failed to allocate 32-bit MSI address\n"); 382 dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); 383 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, 384 GFP_KERNEL); 385 if (!msi_vaddr) { 386 dev_err(dev, "Failed to allocate MSI address\n"); 387 dw_pcie_free_msi(pp); 388 return -ENOMEM; 389 } 390 } 391 392 return 0; 393 } 394 395 static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) 396 { 397 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 398 struct resource_entry *win; 399 struct resource *res; 400 401 win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 402 if (win) { 403 res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL); 404 if (!res) 405 return; 406 407 /* 408 * Allocate MSG TLP region of size 'region_align' at the end of 409 * the host bridge window. 410 */ 411 res->start = win->res->end - pci->region_align + 1; 412 res->end = win->res->end; 413 res->name = "msg"; 414 res->flags = win->res->flags | IORESOURCE_BUSY; 415 416 if (!devm_request_resource(pci->dev, win->res, res)) 417 pp->msg_res = res; 418 } 419 } 420 421 static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) 422 { 423 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 424 struct device *dev = pci->dev; 425 struct platform_device *pdev = to_platform_device(dev); 426 struct resource_entry *win; 427 struct resource *res; 428 int ret; 429 430 ret = dw_pcie_get_resources(pci); 431 if (ret) 432 return ret; 433 434 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 435 if (!res) { 436 dev_err(dev, "Missing \"config\" reg space\n"); 437 return -ENODEV; 438 } 439 440 pp->cfg0_size = resource_size(res); 441 pp->cfg0_base = res->start; 442 443 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 444 if (IS_ERR(pp->va_cfg0_base)) 445 return PTR_ERR(pp->va_cfg0_base); 446 447 /* Get the I/O range from DT */ 448 win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_IO); 449 if (win) { 450 pp->io_size = resource_size(win->res); 451 pp->io_bus_addr = win->res->start - win->offset; 452 pp->io_base = pci_pio_to_address(win->res->start); 453 } 454 455 /* 456 * visconti_pcie_cpu_addr_fixup() uses pp->io_base, so we have to 457 * call dw_pcie_parent_bus_offset() after setting pp->io_base. 458 */ 459 pci->parent_bus_offset = dw_pcie_parent_bus_offset(pci, "config", 460 pp->cfg0_base); 461 return 0; 462 } 463 464 int dw_pcie_host_init(struct dw_pcie_rp *pp) 465 { 466 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 467 struct device *dev = pci->dev; 468 struct device_node *np = dev->of_node; 469 struct pci_host_bridge *bridge; 470 int ret; 471 472 raw_spin_lock_init(&pp->lock); 473 474 bridge = devm_pci_alloc_host_bridge(dev, 0); 475 if (!bridge) 476 return -ENOMEM; 477 478 pp->bridge = bridge; 479 480 ret = dw_pcie_host_get_resources(pp); 481 if (ret) 482 return ret; 483 484 /* Set default bus ops */ 485 bridge->ops = &dw_pcie_ops; 486 bridge->child_ops = &dw_child_pcie_ops; 487 488 if (pp->ops->init) { 489 ret = pp->ops->init(pp); 490 if (ret) 491 return ret; 492 } 493 494 if (pci_msi_enabled()) { 495 pp->has_msi_ctrl = !(pp->ops->msi_init || 496 of_property_present(np, "msi-parent") || 497 of_property_present(np, "msi-map")); 498 499 /* 500 * For the has_msi_ctrl case the default assignment is handled 501 * in the dw_pcie_msi_host_init(). 502 */ 503 if (!pp->has_msi_ctrl && !pp->num_vectors) { 504 pp->num_vectors = MSI_DEF_NUM_VECTORS; 505 } else if (pp->num_vectors > MAX_MSI_IRQS) { 506 dev_err(dev, "Invalid number of vectors\n"); 507 ret = -EINVAL; 508 goto err_deinit_host; 509 } 510 511 if (pp->ops->msi_init) { 512 ret = pp->ops->msi_init(pp); 513 if (ret < 0) 514 goto err_deinit_host; 515 } else if (pp->has_msi_ctrl) { 516 ret = dw_pcie_msi_host_init(pp); 517 if (ret < 0) 518 goto err_deinit_host; 519 } 520 } 521 522 dw_pcie_version_detect(pci); 523 524 dw_pcie_iatu_detect(pci); 525 526 if (pci->num_lanes < 1) 527 pci->num_lanes = dw_pcie_link_get_max_link_width(pci); 528 529 ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); 530 if (ret) 531 goto err_free_msi; 532 533 /* 534 * Allocate the resource for MSG TLP before programming the iATU 535 * outbound window in dw_pcie_setup_rc(). Since the allocation depends 536 * on the value of 'region_align', this has to be done after 537 * dw_pcie_iatu_detect(). 538 * 539 * Glue drivers need to set 'use_atu_msg' before dw_pcie_host_init() to 540 * make use of the generic MSG TLP implementation. 541 */ 542 if (pp->use_atu_msg) 543 dw_pcie_host_request_msg_tlp_res(pp); 544 545 ret = dw_pcie_edma_detect(pci); 546 if (ret) 547 goto err_free_msi; 548 549 ret = dw_pcie_setup_rc(pp); 550 if (ret) 551 goto err_remove_edma; 552 553 if (!dw_pcie_link_up(pci)) { 554 ret = dw_pcie_start_link(pci); 555 if (ret) 556 goto err_remove_edma; 557 } 558 559 /* 560 * Note: Skip the link up delay only when a Link Up IRQ is present. 561 * If there is no Link Up IRQ, we should not bypass the delay 562 * because that would require users to manually rescan for devices. 563 */ 564 if (!pp->use_linkup_irq) 565 /* Ignore errors, the link may come up later */ 566 dw_pcie_wait_for_link(pci); 567 568 bridge->sysdata = pp; 569 570 ret = pci_host_probe(bridge); 571 if (ret) 572 goto err_stop_link; 573 574 if (pp->ops->post_init) 575 pp->ops->post_init(pp); 576 577 dwc_pcie_debugfs_init(pci, DW_PCIE_RC_TYPE); 578 579 return 0; 580 581 err_stop_link: 582 dw_pcie_stop_link(pci); 583 584 err_remove_edma: 585 dw_pcie_edma_remove(pci); 586 587 err_free_msi: 588 if (pp->has_msi_ctrl) 589 dw_pcie_free_msi(pp); 590 591 err_deinit_host: 592 if (pp->ops->deinit) 593 pp->ops->deinit(pp); 594 595 return ret; 596 } 597 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 598 599 void dw_pcie_host_deinit(struct dw_pcie_rp *pp) 600 { 601 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 602 603 dwc_pcie_debugfs_deinit(pci); 604 605 pci_stop_root_bus(pp->bridge->bus); 606 pci_remove_root_bus(pp->bridge->bus); 607 608 dw_pcie_stop_link(pci); 609 610 dw_pcie_edma_remove(pci); 611 612 if (pp->has_msi_ctrl) 613 dw_pcie_free_msi(pp); 614 615 if (pp->ops->deinit) 616 pp->ops->deinit(pp); 617 } 618 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 619 620 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 621 unsigned int devfn, int where) 622 { 623 struct dw_pcie_rp *pp = bus->sysdata; 624 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 625 struct dw_pcie_ob_atu_cfg atu = { 0 }; 626 int type, ret; 627 u32 busdev; 628 629 /* 630 * Checking whether the link is up here is a last line of defense 631 * against platforms that forward errors on the system bus as 632 * SError upon PCI configuration transactions issued when the link 633 * is down. This check is racy by definition and does not stop 634 * the system from triggering an SError if the link goes down 635 * after this check is performed. 636 */ 637 if (!dw_pcie_link_up(pci)) 638 return NULL; 639 640 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 641 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 642 643 if (pci_is_root_bus(bus->parent)) 644 type = PCIE_ATU_TYPE_CFG0; 645 else 646 type = PCIE_ATU_TYPE_CFG1; 647 648 atu.type = type; 649 atu.parent_bus_addr = pp->cfg0_base - pci->parent_bus_offset; 650 atu.pci_addr = busdev; 651 atu.size = pp->cfg0_size; 652 653 ret = dw_pcie_prog_outbound_atu(pci, &atu); 654 if (ret) 655 return NULL; 656 657 return pp->va_cfg0_base + where; 658 } 659 660 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 661 int where, int size, u32 *val) 662 { 663 struct dw_pcie_rp *pp = bus->sysdata; 664 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 665 struct dw_pcie_ob_atu_cfg atu = { 0 }; 666 int ret; 667 668 ret = pci_generic_config_read(bus, devfn, where, size, val); 669 if (ret != PCIBIOS_SUCCESSFUL) 670 return ret; 671 672 if (pp->cfg0_io_shared) { 673 atu.type = PCIE_ATU_TYPE_IO; 674 atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset; 675 atu.pci_addr = pp->io_bus_addr; 676 atu.size = pp->io_size; 677 678 ret = dw_pcie_prog_outbound_atu(pci, &atu); 679 if (ret) 680 return PCIBIOS_SET_FAILED; 681 } 682 683 return PCIBIOS_SUCCESSFUL; 684 } 685 686 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 687 int where, int size, u32 val) 688 { 689 struct dw_pcie_rp *pp = bus->sysdata; 690 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 691 struct dw_pcie_ob_atu_cfg atu = { 0 }; 692 int ret; 693 694 ret = pci_generic_config_write(bus, devfn, where, size, val); 695 if (ret != PCIBIOS_SUCCESSFUL) 696 return ret; 697 698 if (pp->cfg0_io_shared) { 699 atu.type = PCIE_ATU_TYPE_IO; 700 atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset; 701 atu.pci_addr = pp->io_bus_addr; 702 atu.size = pp->io_size; 703 704 ret = dw_pcie_prog_outbound_atu(pci, &atu); 705 if (ret) 706 return PCIBIOS_SET_FAILED; 707 } 708 709 return PCIBIOS_SUCCESSFUL; 710 } 711 712 static struct pci_ops dw_child_pcie_ops = { 713 .map_bus = dw_pcie_other_conf_map_bus, 714 .read = dw_pcie_rd_other_conf, 715 .write = dw_pcie_wr_other_conf, 716 }; 717 718 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 719 { 720 struct dw_pcie_rp *pp = bus->sysdata; 721 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 722 723 if (PCI_SLOT(devfn) > 0) 724 return NULL; 725 726 return pci->dbi_base + where; 727 } 728 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 729 730 static struct pci_ops dw_pcie_ops = { 731 .map_bus = dw_pcie_own_conf_map_bus, 732 .read = pci_generic_config_read, 733 .write = pci_generic_config_write, 734 }; 735 736 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) 737 { 738 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 739 struct dw_pcie_ob_atu_cfg atu = { 0 }; 740 struct resource_entry *entry; 741 int i, ret; 742 743 /* Note the very first outbound ATU is used for CFG IOs */ 744 if (!pci->num_ob_windows) { 745 dev_err(pci->dev, "No outbound iATU found\n"); 746 return -EINVAL; 747 } 748 749 /* 750 * Ensure all out/inbound windows are disabled before proceeding with 751 * the MEM/IO (dma-)ranges setups. 752 */ 753 for (i = 0; i < pci->num_ob_windows; i++) 754 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i); 755 756 for (i = 0; i < pci->num_ib_windows; i++) 757 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i); 758 759 i = 0; 760 resource_list_for_each_entry(entry, &pp->bridge->windows) { 761 if (resource_type(entry->res) != IORESOURCE_MEM) 762 continue; 763 764 if (pci->num_ob_windows <= ++i) 765 break; 766 767 atu.index = i; 768 atu.type = PCIE_ATU_TYPE_MEM; 769 atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; 770 atu.pci_addr = entry->res->start - entry->offset; 771 772 /* Adjust iATU size if MSG TLP region was allocated before */ 773 if (pp->msg_res && pp->msg_res->parent == entry->res) 774 atu.size = resource_size(entry->res) - 775 resource_size(pp->msg_res); 776 else 777 atu.size = resource_size(entry->res); 778 779 ret = dw_pcie_prog_outbound_atu(pci, &atu); 780 if (ret) { 781 dev_err(pci->dev, "Failed to set MEM range %pr\n", 782 entry->res); 783 return ret; 784 } 785 } 786 787 if (pp->io_size) { 788 if (pci->num_ob_windows > ++i) { 789 atu.index = i; 790 atu.type = PCIE_ATU_TYPE_IO; 791 atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset; 792 atu.pci_addr = pp->io_bus_addr; 793 atu.size = pp->io_size; 794 795 ret = dw_pcie_prog_outbound_atu(pci, &atu); 796 if (ret) { 797 dev_err(pci->dev, "Failed to set IO range %pr\n", 798 entry->res); 799 return ret; 800 } 801 } else { 802 pp->cfg0_io_shared = true; 803 } 804 } 805 806 if (pci->num_ob_windows <= i) 807 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", 808 pci->num_ob_windows); 809 810 pp->msg_atu_index = i; 811 812 i = 0; 813 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { 814 if (resource_type(entry->res) != IORESOURCE_MEM) 815 continue; 816 817 if (pci->num_ib_windows <= i) 818 break; 819 820 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, 821 entry->res->start, 822 entry->res->start - entry->offset, 823 resource_size(entry->res)); 824 if (ret) { 825 dev_err(pci->dev, "Failed to set DMA range %pr\n", 826 entry->res); 827 return ret; 828 } 829 } 830 831 if (pci->num_ib_windows <= i) 832 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n", 833 pci->num_ib_windows); 834 835 return 0; 836 } 837 838 static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) 839 { 840 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 841 u8 lane_eq_offset, lane_reg_size, cap_id; 842 u8 *presets; 843 u32 cap; 844 int i; 845 846 if (speed == PCIE_SPEED_8_0GT) { 847 presets = (u8 *)pp->presets.eq_presets_8gts; 848 lane_eq_offset = PCI_SECPCI_LE_CTRL; 849 cap_id = PCI_EXT_CAP_ID_SECPCI; 850 /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ 851 lane_reg_size = 0x2; 852 } else if (speed == PCIE_SPEED_16_0GT) { 853 presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; 854 lane_eq_offset = PCI_PL_16GT_LE_CTRL; 855 cap_id = PCI_EXT_CAP_ID_PL_16GT; 856 lane_reg_size = 0x1; 857 } else if (speed == PCIE_SPEED_32_0GT) { 858 presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_32GTS - 1]; 859 lane_eq_offset = PCI_PL_32GT_LE_CTRL; 860 cap_id = PCI_EXT_CAP_ID_PL_32GT; 861 lane_reg_size = 0x1; 862 } else if (speed == PCIE_SPEED_64_0GT) { 863 presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_64GTS - 1]; 864 lane_eq_offset = PCI_PL_64GT_LE_CTRL; 865 cap_id = PCI_EXT_CAP_ID_PL_64GT; 866 lane_reg_size = 0x1; 867 } else { 868 return; 869 } 870 871 if (presets[0] == PCI_EQ_RESV) 872 return; 873 874 cap = dw_pcie_find_ext_capability(pci, cap_id); 875 if (!cap) 876 return; 877 878 /* 879 * Write preset values to the registers byte-by-byte for the given 880 * number of lanes and register size. 881 */ 882 for (i = 0; i < pci->num_lanes * lane_reg_size; i++) 883 dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); 884 } 885 886 static void dw_pcie_config_presets(struct dw_pcie_rp *pp) 887 { 888 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 889 enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; 890 891 /* 892 * Lane equalization settings need to be applied for all data rates the 893 * controller supports and for all supported lanes. 894 */ 895 896 if (speed >= PCIE_SPEED_8_0GT) 897 dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); 898 899 if (speed >= PCIE_SPEED_16_0GT) 900 dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); 901 902 if (speed >= PCIE_SPEED_32_0GT) 903 dw_pcie_program_presets(pp, PCIE_SPEED_32_0GT); 904 905 if (speed >= PCIE_SPEED_64_0GT) 906 dw_pcie_program_presets(pp, PCIE_SPEED_64_0GT); 907 } 908 909 int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 910 { 911 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 912 u32 val, ctrl, num_ctrls; 913 int ret; 914 915 /* 916 * Enable DBI read-only registers for writing/updating configuration. 917 * Write permission gets disabled towards the end of this function. 918 */ 919 dw_pcie_dbi_ro_wr_en(pci); 920 921 dw_pcie_setup(pci); 922 923 if (pp->has_msi_ctrl) { 924 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 925 926 /* Initialize IRQ Status array */ 927 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 928 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 929 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 930 pp->irq_mask[ctrl]); 931 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 932 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 933 ~0); 934 } 935 } 936 937 dw_pcie_msi_init(pp); 938 939 /* Setup RC BARs */ 940 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 941 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 942 943 /* Setup interrupt pins */ 944 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 945 val &= 0xffff00ff; 946 val |= 0x00000100; 947 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 948 949 /* Setup bus numbers */ 950 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 951 val &= 0xff000000; 952 val |= 0x00ff0100; 953 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 954 955 /* Setup command register */ 956 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 957 val &= 0xffff0000; 958 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 959 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 960 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 961 962 dw_pcie_config_presets(pp); 963 /* 964 * If the platform provides its own child bus config accesses, it means 965 * the platform uses its own address translation component rather than 966 * ATU, so we should not program the ATU here. 967 */ 968 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 969 ret = dw_pcie_iatu_setup(pp); 970 if (ret) 971 return ret; 972 } 973 974 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 975 976 /* Program correct class for RC */ 977 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 978 979 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 980 val |= PORT_LOGIC_SPEED_CHANGE; 981 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 982 983 dw_pcie_dbi_ro_wr_dis(pci); 984 985 return 0; 986 } 987 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 988 989 static int dw_pcie_pme_turn_off(struct dw_pcie *pci) 990 { 991 struct dw_pcie_ob_atu_cfg atu = { 0 }; 992 void __iomem *mem; 993 int ret; 994 995 if (pci->num_ob_windows <= pci->pp.msg_atu_index) 996 return -ENOSPC; 997 998 if (!pci->pp.msg_res) 999 return -ENOSPC; 1000 1001 atu.code = PCIE_MSG_CODE_PME_TURN_OFF; 1002 atu.routing = PCIE_MSG_TYPE_R_BC; 1003 atu.type = PCIE_ATU_TYPE_MSG; 1004 atu.size = resource_size(pci->pp.msg_res); 1005 atu.index = pci->pp.msg_atu_index; 1006 1007 atu.parent_bus_addr = pci->pp.msg_res->start - pci->parent_bus_offset; 1008 1009 ret = dw_pcie_prog_outbound_atu(pci, &atu); 1010 if (ret) 1011 return ret; 1012 1013 mem = ioremap(pci->pp.msg_res->start, pci->region_align); 1014 if (!mem) 1015 return -ENOMEM; 1016 1017 /* A dummy write is converted to a Msg TLP */ 1018 writel(0, mem); 1019 1020 iounmap(mem); 1021 1022 return 0; 1023 } 1024 1025 int dw_pcie_suspend_noirq(struct dw_pcie *pci) 1026 { 1027 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1028 u32 val; 1029 int ret; 1030 1031 /* 1032 * If L1SS is supported, then do not put the link into L2 as some 1033 * devices such as NVMe expect low resume latency. 1034 */ 1035 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) 1036 return 0; 1037 1038 if (pci->pp.ops->pme_turn_off) { 1039 pci->pp.ops->pme_turn_off(&pci->pp); 1040 } else { 1041 ret = dw_pcie_pme_turn_off(pci); 1042 if (ret) 1043 return ret; 1044 } 1045 1046 ret = read_poll_timeout(dw_pcie_get_ltssm, val, 1047 val == DW_PCIE_LTSSM_L2_IDLE || 1048 val <= DW_PCIE_LTSSM_DETECT_WAIT, 1049 PCIE_PME_TO_L2_TIMEOUT_US/10, 1050 PCIE_PME_TO_L2_TIMEOUT_US, false, pci); 1051 if (ret) { 1052 /* Only log message when LTSSM isn't in DETECT or POLL */ 1053 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); 1054 return ret; 1055 } 1056 1057 /* 1058 * Per PCIe r6.0, sec 5.3.3.2.1, software should wait at least 1059 * 100ns after L2/L3 Ready before turning off refclock and 1060 * main power. This is harmless when no endpoint is connected. 1061 */ 1062 udelay(1); 1063 1064 dw_pcie_stop_link(pci); 1065 if (pci->pp.ops->deinit) 1066 pci->pp.ops->deinit(&pci->pp); 1067 1068 pci->suspended = true; 1069 1070 return ret; 1071 } 1072 EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); 1073 1074 int dw_pcie_resume_noirq(struct dw_pcie *pci) 1075 { 1076 int ret; 1077 1078 if (!pci->suspended) 1079 return 0; 1080 1081 pci->suspended = false; 1082 1083 if (pci->pp.ops->init) { 1084 ret = pci->pp.ops->init(&pci->pp); 1085 if (ret) { 1086 dev_err(pci->dev, "Host init failed: %d\n", ret); 1087 return ret; 1088 } 1089 } 1090 1091 dw_pcie_setup_rc(&pci->pp); 1092 1093 ret = dw_pcie_start_link(pci); 1094 if (ret) 1095 return ret; 1096 1097 ret = dw_pcie_wait_for_link(pci); 1098 if (ret) 1099 return ret; 1100 1101 return ret; 1102 } 1103 EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); 1104