1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Marvell Armada-8K SoCs 4 * 5 * Armada-8K PCIe Glue Layer Source Code 6 * 7 * Copyright (C) 2016 Marvell Technology Group Ltd. 8 * 9 * Author: Yehuda Yitshak <yehuday@marvell.com> 10 * Author: Shadi Ammouri <shadi@marvell.com> 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/of.h> 19 #include <linux/pci.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/resource.h> 23 #include <linux/of_pci.h> 24 #include <linux/of_irq.h> 25 26 #include "pcie-designware.h" 27 28 #define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4 29 30 struct armada8k_pcie { 31 struct dw_pcie *pci; 32 struct clk *clk; 33 struct clk *clk_reg; 34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; 35 unsigned int phy_count; 36 }; 37 38 #define PCIE_VENDOR_REGS_OFFSET 0x8000 39 40 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) 41 #define PCIE_APP_LTSSM_EN BIT(2) 42 #define PCIE_DEVICE_TYPE_SHIFT 4 43 #define PCIE_DEVICE_TYPE_MASK 0xF 44 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ 45 46 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8) 47 #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) 48 #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) 49 50 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) 51 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) 52 #define PCIE_INT_A_ASSERT_MASK BIT(9) 53 #define PCIE_INT_B_ASSERT_MASK BIT(10) 54 #define PCIE_INT_C_ASSERT_MASK BIT(11) 55 #define PCIE_INT_D_ASSERT_MASK BIT(12) 56 57 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) 58 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) 59 #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) 60 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60) 61 /* 62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write 63 * allocate 64 */ 65 #define ARCACHE_DEFAULT_VALUE 0x3511 66 #define AWCACHE_DEFAULT_VALUE 0x5311 67 68 #define DOMAIN_OUTER_SHAREABLE 0x2 69 #define AX_USER_DOMAIN_MASK 0x3 70 #define AX_USER_DOMAIN_SHIFT 4 71 72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) 73 74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) 75 { 76 int i; 77 78 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 79 phy_power_off(pcie->phy[i]); 80 phy_exit(pcie->phy[i]); 81 } 82 } 83 84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) 85 { 86 int ret; 87 int i; 88 89 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 90 ret = phy_init(pcie->phy[i]); 91 if (ret) 92 return ret; 93 94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, 95 pcie->phy_count); 96 if (ret) { 97 phy_exit(pcie->phy[i]); 98 return ret; 99 } 100 101 ret = phy_power_on(pcie->phy[i]); 102 if (ret) { 103 phy_exit(pcie->phy[i]); 104 return ret; 105 } 106 } 107 108 return 0; 109 } 110 111 static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie) 112 { 113 struct dw_pcie *pci = pcie->pci; 114 struct device *dev = pci->dev; 115 struct device_node *node = dev->of_node; 116 int ret = 0; 117 int i; 118 119 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 120 pcie->phy[i] = devm_of_phy_get_by_index(dev, node, i); 121 if (IS_ERR(pcie->phy[i])) { 122 if (PTR_ERR(pcie->phy[i]) != -ENODEV) 123 return PTR_ERR(pcie->phy[i]); 124 125 pcie->phy[i] = NULL; 126 continue; 127 } 128 129 pcie->phy_count++; 130 } 131 132 /* Old bindings miss the PHY handle, so just warn if there is no PHY */ 133 if (!pcie->phy_count) 134 dev_warn(dev, "No available PHY\n"); 135 136 ret = armada8k_pcie_enable_phys(pcie); 137 if (ret) 138 dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret); 139 140 return ret; 141 } 142 143 static int armada8k_pcie_link_up(struct dw_pcie *pci) 144 { 145 u32 reg; 146 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 147 148 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); 149 150 if ((reg & mask) == mask) 151 return 1; 152 153 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); 154 return 0; 155 } 156 157 static int armada8k_pcie_start_link(struct dw_pcie *pci) 158 { 159 u32 reg; 160 161 /* Start LTSSM */ 162 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 163 reg |= PCIE_APP_LTSSM_EN; 164 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 165 166 return 0; 167 } 168 169 static int armada8k_pcie_host_init(struct pcie_port *pp) 170 { 171 u32 reg; 172 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 173 174 if (!dw_pcie_link_up(pci)) { 175 /* Disable LTSSM state machine to enable configuration */ 176 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 177 reg &= ~(PCIE_APP_LTSSM_EN); 178 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 179 } 180 181 /* Set the device to root complex mode */ 182 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 183 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); 184 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; 185 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 186 187 /* Set the PCIe master AxCache attributes */ 188 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); 189 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); 190 191 /* Set the PCIe master AxDomain attributes */ 192 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); 193 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 194 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 195 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); 196 197 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); 198 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 199 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 200 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); 201 202 /* Enable INT A-D interrupts */ 203 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); 204 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 205 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 206 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); 207 208 return 0; 209 } 210 211 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) 212 { 213 struct armada8k_pcie *pcie = arg; 214 struct dw_pcie *pci = pcie->pci; 215 u32 val; 216 217 /* 218 * Interrupts are directly handled by the device driver of the 219 * PCI device. However, they are also latched into the PCIe 220 * controller, so we simply discard them. 221 */ 222 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); 223 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); 224 225 return IRQ_HANDLED; 226 } 227 228 static const struct dw_pcie_host_ops armada8k_pcie_host_ops = { 229 .host_init = armada8k_pcie_host_init, 230 }; 231 232 static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, 233 struct platform_device *pdev) 234 { 235 struct dw_pcie *pci = pcie->pci; 236 struct pcie_port *pp = &pci->pp; 237 struct device *dev = &pdev->dev; 238 int ret; 239 240 pp->ops = &armada8k_pcie_host_ops; 241 242 pp->irq = platform_get_irq(pdev, 0); 243 if (pp->irq < 0) 244 return pp->irq; 245 246 ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler, 247 IRQF_SHARED, "armada8k-pcie", pcie); 248 if (ret) { 249 dev_err(dev, "failed to request irq %d\n", pp->irq); 250 return ret; 251 } 252 253 ret = dw_pcie_host_init(pp); 254 if (ret) { 255 dev_err(dev, "failed to initialize host: %d\n", ret); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static const struct dw_pcie_ops dw_pcie_ops = { 263 .link_up = armada8k_pcie_link_up, 264 .start_link = armada8k_pcie_start_link, 265 }; 266 267 static int armada8k_pcie_probe(struct platform_device *pdev) 268 { 269 struct dw_pcie *pci; 270 struct armada8k_pcie *pcie; 271 struct device *dev = &pdev->dev; 272 struct resource *base; 273 int ret; 274 275 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 276 if (!pcie) 277 return -ENOMEM; 278 279 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 280 if (!pci) 281 return -ENOMEM; 282 283 pci->dev = dev; 284 pci->ops = &dw_pcie_ops; 285 286 pcie->pci = pci; 287 288 pcie->clk = devm_clk_get(dev, NULL); 289 if (IS_ERR(pcie->clk)) 290 return PTR_ERR(pcie->clk); 291 292 ret = clk_prepare_enable(pcie->clk); 293 if (ret) 294 return ret; 295 296 pcie->clk_reg = devm_clk_get(dev, "reg"); 297 if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) { 298 ret = -EPROBE_DEFER; 299 goto fail; 300 } 301 if (!IS_ERR(pcie->clk_reg)) { 302 ret = clk_prepare_enable(pcie->clk_reg); 303 if (ret) 304 goto fail_clkreg; 305 } 306 307 /* Get the dw-pcie unit configuration/control registers base. */ 308 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 309 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); 310 if (IS_ERR(pci->dbi_base)) { 311 ret = PTR_ERR(pci->dbi_base); 312 goto fail_clkreg; 313 } 314 315 ret = armada8k_pcie_setup_phys(pcie); 316 if (ret) 317 goto fail_clkreg; 318 319 platform_set_drvdata(pdev, pcie); 320 321 ret = armada8k_add_pcie_port(pcie, pdev); 322 if (ret) 323 goto disable_phy; 324 325 return 0; 326 327 disable_phy: 328 armada8k_pcie_disable_phys(pcie); 329 fail_clkreg: 330 clk_disable_unprepare(pcie->clk_reg); 331 fail: 332 clk_disable_unprepare(pcie->clk); 333 334 return ret; 335 } 336 337 static const struct of_device_id armada8k_pcie_of_match[] = { 338 { .compatible = "marvell,armada8k-pcie", }, 339 {}, 340 }; 341 342 static struct platform_driver armada8k_pcie_driver = { 343 .probe = armada8k_pcie_probe, 344 .driver = { 345 .name = "armada8k-pcie", 346 .of_match_table = of_match_ptr(armada8k_pcie_of_match), 347 .suppress_bind_attrs = true, 348 }, 349 }; 350 builtin_platform_driver(armada8k_pcie_driver); 351