1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Marvell Armada-8K SoCs 4 * 5 * Armada-8K PCIe Glue Layer Source Code 6 * 7 * Copyright (C) 2016 Marvell Technology Group Ltd. 8 * 9 * Author: Yehuda Yitshak <yehuday@marvell.com> 10 * Author: Shadi Ammouri <shadi@marvell.com> 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/of.h> 19 #include <linux/pci.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/resource.h> 23 #include <linux/of_pci.h> 24 #include <linux/of_irq.h> 25 26 #include "pcie-designware.h" 27 28 #define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4 29 30 struct armada8k_pcie { 31 struct dw_pcie *pci; 32 struct clk *clk; 33 struct clk *clk_reg; 34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; 35 unsigned int phy_count; 36 }; 37 38 #define PCIE_VENDOR_REGS_OFFSET 0x8000 39 40 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) 41 #define PCIE_APP_LTSSM_EN BIT(2) 42 #define PCIE_DEVICE_TYPE_SHIFT 4 43 #define PCIE_DEVICE_TYPE_MASK 0xF 44 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ 45 46 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8) 47 #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) 48 #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) 49 50 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) 51 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) 52 #define PCIE_INT_A_ASSERT_MASK BIT(9) 53 #define PCIE_INT_B_ASSERT_MASK BIT(10) 54 #define PCIE_INT_C_ASSERT_MASK BIT(11) 55 #define PCIE_INT_D_ASSERT_MASK BIT(12) 56 57 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) 58 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) 59 #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) 60 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60) 61 /* 62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write 63 * allocate 64 */ 65 #define ARCACHE_DEFAULT_VALUE 0x3511 66 #define AWCACHE_DEFAULT_VALUE 0x5311 67 68 #define DOMAIN_OUTER_SHAREABLE 0x2 69 #define AX_USER_DOMAIN_MASK 0x3 70 #define AX_USER_DOMAIN_SHIFT 4 71 72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) 73 74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) 75 { 76 int i; 77 78 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 79 phy_power_off(pcie->phy[i]); 80 phy_exit(pcie->phy[i]); 81 } 82 } 83 84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) 85 { 86 int ret; 87 int i; 88 89 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 90 ret = phy_init(pcie->phy[i]); 91 if (ret) 92 return ret; 93 94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, 95 pcie->phy_count); 96 if (ret) { 97 phy_exit(pcie->phy[i]); 98 return ret; 99 } 100 101 ret = phy_power_on(pcie->phy[i]); 102 if (ret) { 103 phy_exit(pcie->phy[i]); 104 return ret; 105 } 106 } 107 108 return 0; 109 } 110 111 static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie) 112 { 113 struct dw_pcie *pci = pcie->pci; 114 struct device *dev = pci->dev; 115 struct device_node *node = dev->of_node; 116 int ret = 0; 117 int i; 118 119 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 120 pcie->phy[i] = devm_of_phy_get_by_index(dev, node, i); 121 if (IS_ERR(pcie->phy[i])) { 122 if (PTR_ERR(pcie->phy[i]) != -ENODEV) 123 return PTR_ERR(pcie->phy[i]); 124 125 pcie->phy[i] = NULL; 126 continue; 127 } 128 129 pcie->phy_count++; 130 } 131 132 /* Old bindings miss the PHY handle, so just warn if there is no PHY */ 133 if (!pcie->phy_count) 134 dev_warn(dev, "No available PHY\n"); 135 136 ret = armada8k_pcie_enable_phys(pcie); 137 if (ret) 138 dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret); 139 140 return ret; 141 } 142 143 static int armada8k_pcie_link_up(struct dw_pcie *pci) 144 { 145 u32 reg; 146 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 147 148 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); 149 150 if ((reg & mask) == mask) 151 return 1; 152 153 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); 154 return 0; 155 } 156 157 static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) 158 { 159 struct dw_pcie *pci = pcie->pci; 160 u32 reg; 161 162 if (!dw_pcie_link_up(pci)) { 163 /* Disable LTSSM state machine to enable configuration */ 164 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 165 reg &= ~(PCIE_APP_LTSSM_EN); 166 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 167 } 168 169 /* Set the device to root complex mode */ 170 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 171 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); 172 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; 173 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 174 175 /* Set the PCIe master AxCache attributes */ 176 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); 177 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); 178 179 /* Set the PCIe master AxDomain attributes */ 180 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); 181 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 182 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 183 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); 184 185 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); 186 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 187 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 188 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); 189 190 /* Enable INT A-D interrupts */ 191 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); 192 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 193 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 194 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); 195 196 if (!dw_pcie_link_up(pci)) { 197 /* Configuration done. Start LTSSM */ 198 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 199 reg |= PCIE_APP_LTSSM_EN; 200 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 201 } 202 203 /* Wait until the link becomes active again */ 204 if (dw_pcie_wait_for_link(pci)) 205 dev_err(pci->dev, "Link not up after reconfiguration\n"); 206 } 207 208 static int armada8k_pcie_host_init(struct pcie_port *pp) 209 { 210 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 211 struct armada8k_pcie *pcie = to_armada8k_pcie(pci); 212 213 dw_pcie_setup_rc(pp); 214 armada8k_pcie_establish_link(pcie); 215 216 return 0; 217 } 218 219 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) 220 { 221 struct armada8k_pcie *pcie = arg; 222 struct dw_pcie *pci = pcie->pci; 223 u32 val; 224 225 /* 226 * Interrupts are directly handled by the device driver of the 227 * PCI device. However, they are also latched into the PCIe 228 * controller, so we simply discard them. 229 */ 230 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); 231 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); 232 233 return IRQ_HANDLED; 234 } 235 236 static const struct dw_pcie_host_ops armada8k_pcie_host_ops = { 237 .host_init = armada8k_pcie_host_init, 238 }; 239 240 static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, 241 struct platform_device *pdev) 242 { 243 struct dw_pcie *pci = pcie->pci; 244 struct pcie_port *pp = &pci->pp; 245 struct device *dev = &pdev->dev; 246 int ret; 247 248 pp->ops = &armada8k_pcie_host_ops; 249 250 pp->irq = platform_get_irq(pdev, 0); 251 if (pp->irq < 0) 252 return pp->irq; 253 254 ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler, 255 IRQF_SHARED, "armada8k-pcie", pcie); 256 if (ret) { 257 dev_err(dev, "failed to request irq %d\n", pp->irq); 258 return ret; 259 } 260 261 ret = dw_pcie_host_init(pp); 262 if (ret) { 263 dev_err(dev, "failed to initialize host: %d\n", ret); 264 return ret; 265 } 266 267 return 0; 268 } 269 270 static const struct dw_pcie_ops dw_pcie_ops = { 271 .link_up = armada8k_pcie_link_up, 272 }; 273 274 static int armada8k_pcie_probe(struct platform_device *pdev) 275 { 276 struct dw_pcie *pci; 277 struct armada8k_pcie *pcie; 278 struct device *dev = &pdev->dev; 279 struct resource *base; 280 int ret; 281 282 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 283 if (!pcie) 284 return -ENOMEM; 285 286 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 287 if (!pci) 288 return -ENOMEM; 289 290 pci->dev = dev; 291 pci->ops = &dw_pcie_ops; 292 293 pcie->pci = pci; 294 295 pcie->clk = devm_clk_get(dev, NULL); 296 if (IS_ERR(pcie->clk)) 297 return PTR_ERR(pcie->clk); 298 299 ret = clk_prepare_enable(pcie->clk); 300 if (ret) 301 return ret; 302 303 pcie->clk_reg = devm_clk_get(dev, "reg"); 304 if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) { 305 ret = -EPROBE_DEFER; 306 goto fail; 307 } 308 if (!IS_ERR(pcie->clk_reg)) { 309 ret = clk_prepare_enable(pcie->clk_reg); 310 if (ret) 311 goto fail_clkreg; 312 } 313 314 /* Get the dw-pcie unit configuration/control registers base. */ 315 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 316 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); 317 if (IS_ERR(pci->dbi_base)) { 318 ret = PTR_ERR(pci->dbi_base); 319 goto fail_clkreg; 320 } 321 322 ret = armada8k_pcie_setup_phys(pcie); 323 if (ret) 324 goto fail_clkreg; 325 326 platform_set_drvdata(pdev, pcie); 327 328 ret = armada8k_add_pcie_port(pcie, pdev); 329 if (ret) 330 goto disable_phy; 331 332 return 0; 333 334 disable_phy: 335 armada8k_pcie_disable_phys(pcie); 336 fail_clkreg: 337 clk_disable_unprepare(pcie->clk_reg); 338 fail: 339 clk_disable_unprepare(pcie->clk); 340 341 return ret; 342 } 343 344 static const struct of_device_id armada8k_pcie_of_match[] = { 345 { .compatible = "marvell,armada8k-pcie", }, 346 {}, 347 }; 348 349 static struct platform_driver armada8k_pcie_driver = { 350 .probe = armada8k_pcie_probe, 351 .driver = { 352 .name = "armada8k-pcie", 353 .of_match_table = of_match_ptr(armada8k_pcie_of_match), 354 .suppress_bind_attrs = true, 355 }, 356 }; 357 builtin_platform_driver(armada8k_pcie_driver); 358