1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe controller EP driver for Freescale Layerscape SoCs 4 * 5 * Copyright (C) 2018 NXP Semiconductor. 6 * 7 * Author: Xiaowei Bao <xiaowei.bao@nxp.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/of_pci.h> 13 #include <linux/of_platform.h> 14 #include <linux/of_address.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/resource.h> 18 19 #include "pcie-designware.h" 20 21 #define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/ 22 23 struct ls_pcie_ep { 24 struct dw_pcie *pci; 25 }; 26 27 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) 28 29 static int ls_pcie_establish_link(struct dw_pcie *pci) 30 { 31 return 0; 32 } 33 34 static const struct dw_pcie_ops ls_pcie_ep_ops = { 35 .start_link = ls_pcie_establish_link, 36 }; 37 38 static const struct of_device_id ls_pcie_ep_of_match[] = { 39 { .compatible = "fsl,ls-pcie-ep",}, 40 { }, 41 }; 42 43 static const struct pci_epc_features ls_pcie_epc_features = { 44 .linkup_notifier = false, 45 .msi_capable = true, 46 .msix_capable = false, 47 .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), 48 }; 49 50 static const struct pci_epc_features* 51 ls_pcie_ep_get_features(struct dw_pcie_ep *ep) 52 { 53 return &ls_pcie_epc_features; 54 } 55 56 static void ls_pcie_ep_init(struct dw_pcie_ep *ep) 57 { 58 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 59 enum pci_barno bar; 60 61 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 62 dw_pcie_ep_reset_bar(pci, bar); 63 } 64 65 static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 66 enum pci_epc_irq_type type, u16 interrupt_num) 67 { 68 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 69 70 switch (type) { 71 case PCI_EPC_IRQ_LEGACY: 72 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 73 case PCI_EPC_IRQ_MSI: 74 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 75 case PCI_EPC_IRQ_MSIX: 76 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 77 default: 78 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 79 return -EINVAL; 80 } 81 } 82 83 static const struct dw_pcie_ep_ops pcie_ep_ops = { 84 .ep_init = ls_pcie_ep_init, 85 .raise_irq = ls_pcie_ep_raise_irq, 86 .get_features = ls_pcie_ep_get_features, 87 }; 88 89 static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie, 90 struct platform_device *pdev) 91 { 92 struct dw_pcie *pci = pcie->pci; 93 struct device *dev = pci->dev; 94 struct dw_pcie_ep *ep; 95 struct resource *res; 96 int ret; 97 98 ep = &pci->ep; 99 ep->ops = &pcie_ep_ops; 100 101 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 102 if (!res) 103 return -EINVAL; 104 105 ep->phys_base = res->start; 106 ep->addr_size = resource_size(res); 107 108 ret = dw_pcie_ep_init(ep); 109 if (ret) { 110 dev_err(dev, "failed to initialize endpoint\n"); 111 return ret; 112 } 113 114 return 0; 115 } 116 117 static int __init ls_pcie_ep_probe(struct platform_device *pdev) 118 { 119 struct device *dev = &pdev->dev; 120 struct dw_pcie *pci; 121 struct ls_pcie_ep *pcie; 122 struct resource *dbi_base; 123 int ret; 124 125 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 126 if (!pcie) 127 return -ENOMEM; 128 129 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 130 if (!pci) 131 return -ENOMEM; 132 133 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 134 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); 135 if (IS_ERR(pci->dbi_base)) 136 return PTR_ERR(pci->dbi_base); 137 138 pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET; 139 pci->dev = dev; 140 pci->ops = &ls_pcie_ep_ops; 141 pcie->pci = pci; 142 143 platform_set_drvdata(pdev, pcie); 144 145 ret = ls_add_pcie_ep(pcie, pdev); 146 147 return ret; 148 } 149 150 static struct platform_driver ls_pcie_ep_driver = { 151 .driver = { 152 .name = "layerscape-pcie-ep", 153 .of_match_table = ls_pcie_ep_of_match, 154 .suppress_bind_attrs = true, 155 }, 156 }; 157 builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe); 158