1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 30 #include "../../pci.h" 31 #include "pcie-designware.h" 32 33 #define PCIE_VENDORID_MASK 0xffff 34 #define PCIE_DEVICEID_SHIFT 16 35 36 /* Application registers */ 37 #define PID 0x000 38 #define RTL GENMASK(15, 11) 39 #define RTL_SHIFT 11 40 #define AM6_PCI_PG1_RTL_VER 0x15 41 42 #define CMD_STATUS 0x004 43 #define LTSSM_EN_VAL BIT(0) 44 #define OB_XLAT_EN_VAL BIT(1) 45 #define DBI_CS2 BIT(5) 46 47 #define CFG_SETUP 0x008 48 #define CFG_BUS(x) (((x) & 0xff) << 16) 49 #define CFG_DEVICE(x) (((x) & 0x1f) << 8) 50 #define CFG_FUNC(x) ((x) & 0x7) 51 #define CFG_TYPE1 BIT(24) 52 53 #define OB_SIZE 0x030 54 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 55 #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 56 #define OB_ENABLEN BIT(0) 57 #define OB_WIN_SIZE 8 /* 8MB */ 58 59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 61 #define PCIE_EP_IRQ_SET 0x64 62 #define PCIE_EP_IRQ_CLR 0x68 63 #define INT_ENABLE BIT(0) 64 65 /* IRQ register defines */ 66 #define IRQ_EOI 0x050 67 68 #define MSI_IRQ 0x054 69 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 70 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 71 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 72 #define MSI_IRQ_OFFSET 4 73 74 #define IRQ_STATUS(n) (0x184 + ((n) << 4)) 75 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 76 #define INTx_EN BIT(0) 77 78 #define ERR_IRQ_STATUS 0x1c4 79 #define ERR_IRQ_ENABLE_SET 0x1c8 80 #define ERR_AER BIT(5) /* ECRC error */ 81 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 82 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 83 #define ERR_CORR BIT(3) /* Correctable error */ 84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */ 85 #define ERR_FATAL BIT(1) /* Fatal error */ 86 #define ERR_SYS BIT(0) /* System error */ 87 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 88 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 89 90 /* PCIE controller device IDs */ 91 #define PCIE_RC_K2HK 0xb008 92 #define PCIE_RC_K2E 0xb009 93 #define PCIE_RC_K2L 0xb00a 94 #define PCIE_RC_K2G 0xb00b 95 96 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 97 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 98 99 #define EP 0x0 100 #define LEG_EP 0x1 101 #define RC 0x2 102 103 #define KS_PCIE_SYSCLOCKOUTEN BIT(0) 104 105 #define AM654_PCIE_DEV_TYPE_MASK 0x3 106 #define AM654_WIN_SIZE SZ_64K 107 108 #define APP_ADDR_SPACE_0 (16 * SZ_1K) 109 110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 111 112 #define PCI_DEVICE_ID_TI_AM654X 0xb00c 113 114 struct ks_pcie_of_data { 115 enum dw_pcie_device_mode mode; 116 const struct dw_pcie_host_ops *host_ops; 117 const struct dw_pcie_ep_ops *ep_ops; 118 u32 version; 119 }; 120 121 struct keystone_pcie { 122 struct dw_pcie *pci; 123 /* PCI Device ID */ 124 u32 device_id; 125 int intx_host_irqs[PCI_NUM_INTX]; 126 127 int msi_host_irq; 128 int num_lanes; 129 u32 num_viewport; 130 struct phy **phy; 131 struct device_link **link; 132 struct device_node *msi_intc_np; 133 struct irq_domain *intx_irq_domain; 134 struct device_node *np; 135 136 /* Application register space */ 137 void __iomem *va_app_base; /* DT 1st resource */ 138 struct resource app; 139 bool is_am6; 140 }; 141 142 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 143 { 144 return readl(ks_pcie->va_app_base + offset); 145 } 146 147 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 148 u32 val) 149 { 150 writel(val, ks_pcie->va_app_base + offset); 151 } 152 153 static void ks_pcie_msi_irq_ack(struct irq_data *data) 154 { 155 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 156 struct keystone_pcie *ks_pcie; 157 u32 irq = data->hwirq; 158 struct dw_pcie *pci; 159 u32 reg_offset; 160 u32 bit_pos; 161 162 pci = to_dw_pcie_from_pp(pp); 163 ks_pcie = to_keystone_pcie(pci); 164 165 reg_offset = irq % 8; 166 bit_pos = irq >> 3; 167 168 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 169 BIT(bit_pos)); 170 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 171 } 172 173 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 174 { 175 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 176 struct keystone_pcie *ks_pcie; 177 struct dw_pcie *pci; 178 u64 msi_target; 179 180 pci = to_dw_pcie_from_pp(pp); 181 ks_pcie = to_keystone_pcie(pci); 182 183 msi_target = ks_pcie->app.start + MSI_IRQ; 184 msg->address_lo = lower_32_bits(msi_target); 185 msg->address_hi = upper_32_bits(msi_target); 186 msg->data = data->hwirq; 187 188 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 189 (int)data->hwirq, msg->address_hi, msg->address_lo); 190 } 191 192 static void ks_pcie_msi_mask(struct irq_data *data) 193 { 194 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 195 struct keystone_pcie *ks_pcie; 196 u32 irq = data->hwirq; 197 struct dw_pcie *pci; 198 unsigned long flags; 199 u32 reg_offset; 200 u32 bit_pos; 201 202 raw_spin_lock_irqsave(&pp->lock, flags); 203 204 pci = to_dw_pcie_from_pp(pp); 205 ks_pcie = to_keystone_pcie(pci); 206 207 reg_offset = irq % 8; 208 bit_pos = irq >> 3; 209 210 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 211 BIT(bit_pos)); 212 213 raw_spin_unlock_irqrestore(&pp->lock, flags); 214 } 215 216 static void ks_pcie_msi_unmask(struct irq_data *data) 217 { 218 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 219 struct keystone_pcie *ks_pcie; 220 u32 irq = data->hwirq; 221 struct dw_pcie *pci; 222 unsigned long flags; 223 u32 reg_offset; 224 u32 bit_pos; 225 226 raw_spin_lock_irqsave(&pp->lock, flags); 227 228 pci = to_dw_pcie_from_pp(pp); 229 ks_pcie = to_keystone_pcie(pci); 230 231 reg_offset = irq % 8; 232 bit_pos = irq >> 3; 233 234 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 235 BIT(bit_pos)); 236 237 raw_spin_unlock_irqrestore(&pp->lock, flags); 238 } 239 240 static struct irq_chip ks_pcie_msi_irq_chip = { 241 .name = "KEYSTONE-PCI-MSI", 242 .irq_ack = ks_pcie_msi_irq_ack, 243 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 244 .irq_mask = ks_pcie_msi_mask, 245 .irq_unmask = ks_pcie_msi_unmask, 246 }; 247 248 /** 249 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 250 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 251 * PCIe host controller driver information. 252 * 253 * Since modification of dbi_cs2 involves different clock domain, read the 254 * status back to ensure the transition is complete. 255 */ 256 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 257 { 258 u32 val; 259 260 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 261 val |= DBI_CS2; 262 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 263 264 do { 265 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 266 } while (!(val & DBI_CS2)); 267 } 268 269 /** 270 * ks_pcie_clear_dbi_mode() - Disable DBI mode 271 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 272 * PCIe host controller driver information. 273 * 274 * Since modification of dbi_cs2 involves different clock domain, read the 275 * status back to ensure the transition is complete. 276 */ 277 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 278 { 279 u32 val; 280 281 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 282 val &= ~DBI_CS2; 283 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 284 285 do { 286 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 287 } while (val & DBI_CS2); 288 } 289 290 static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 291 { 292 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 293 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 294 295 /* Configure and set up BAR0 */ 296 ks_pcie_set_dbi_mode(ks_pcie); 297 298 /* Enable BAR0 */ 299 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 301 302 ks_pcie_clear_dbi_mode(ks_pcie); 303 304 /* 305 * For BAR0, just setting bus address for inbound writes (MSI) should 306 * be sufficient. Use physical address to avoid any conflicts. 307 */ 308 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 309 310 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 311 return dw_pcie_allocate_domains(pp); 312 } 313 314 static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie, 315 int offset) 316 { 317 struct dw_pcie *pci = ks_pcie->pci; 318 struct device *dev = pci->dev; 319 u32 pending; 320 321 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 322 323 if (BIT(0) & pending) { 324 dev_dbg(dev, ": irq: irq_offset %d", offset); 325 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); 326 } 327 328 /* EOI the INTx interrupt */ 329 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 330 } 331 332 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 333 { 334 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 335 } 336 337 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 338 { 339 u32 reg; 340 struct device *dev = ks_pcie->pci->dev; 341 342 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 343 if (!reg) 344 return IRQ_NONE; 345 346 if (reg & ERR_SYS) 347 dev_err(dev, "System Error\n"); 348 349 if (reg & ERR_FATAL) 350 dev_err(dev, "Fatal Error\n"); 351 352 if (reg & ERR_NONFATAL) 353 dev_dbg(dev, "Non Fatal Error\n"); 354 355 if (reg & ERR_CORR) 356 dev_dbg(dev, "Correctable Error\n"); 357 358 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 359 dev_err(dev, "AXI tag lookup fatal Error\n"); 360 361 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 362 dev_err(dev, "ECRC Error\n"); 363 364 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 365 366 return IRQ_HANDLED; 367 } 368 369 static void ks_pcie_ack_intx_irq(struct irq_data *d) 370 { 371 } 372 373 static void ks_pcie_mask_intx_irq(struct irq_data *d) 374 { 375 } 376 377 static void ks_pcie_unmask_intx_irq(struct irq_data *d) 378 { 379 } 380 381 static struct irq_chip ks_pcie_intx_irq_chip = { 382 .name = "Keystone-PCI-INTX-IRQ", 383 .irq_ack = ks_pcie_ack_intx_irq, 384 .irq_mask = ks_pcie_mask_intx_irq, 385 .irq_unmask = ks_pcie_unmask_intx_irq, 386 }; 387 388 static int ks_pcie_init_intx_irq_map(struct irq_domain *d, 389 unsigned int irq, irq_hw_number_t hw_irq) 390 { 391 irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip, 392 handle_level_irq); 393 irq_set_chip_data(irq, d->host_data); 394 395 return 0; 396 } 397 398 static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 399 .map = ks_pcie_init_intx_irq_map, 400 .xlate = irq_domain_xlate_onetwocell, 401 }; 402 403 static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 404 { 405 u32 val; 406 u32 num_viewport = ks_pcie->num_viewport; 407 struct dw_pcie *pci = ks_pcie->pci; 408 struct dw_pcie_rp *pp = &pci->pp; 409 struct resource_entry *entry; 410 struct resource *mem; 411 u64 start, end; 412 int i; 413 414 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 415 if (!entry) 416 return -ENODEV; 417 418 mem = entry->res; 419 start = mem->start; 420 end = mem->end; 421 422 /* Disable BARs for inbound access */ 423 ks_pcie_set_dbi_mode(ks_pcie); 424 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 425 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 426 ks_pcie_clear_dbi_mode(ks_pcie); 427 428 if (ks_pcie->is_am6) 429 return 0; 430 431 val = ilog2(OB_WIN_SIZE); 432 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 433 434 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 435 for (i = 0; i < num_viewport && (start < end); i++) { 436 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 437 lower_32_bits(start) | OB_ENABLEN); 438 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 439 upper_32_bits(start)); 440 start += OB_WIN_SIZE * SZ_1M; 441 } 442 443 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 444 val |= OB_XLAT_EN_VAL; 445 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 446 447 return 0; 448 } 449 450 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 451 unsigned int devfn, int where) 452 { 453 struct dw_pcie_rp *pp = bus->sysdata; 454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 455 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 456 u32 reg; 457 458 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 459 CFG_FUNC(PCI_FUNC(devfn)); 460 if (!pci_is_root_bus(bus->parent)) 461 reg |= CFG_TYPE1; 462 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 463 464 return pp->va_cfg0_base + where; 465 } 466 467 static struct pci_ops ks_child_pcie_ops = { 468 .map_bus = ks_pcie_other_map_bus, 469 .read = pci_generic_config_read, 470 .write = pci_generic_config_write, 471 }; 472 473 static struct pci_ops ks_pcie_ops = { 474 .map_bus = dw_pcie_own_conf_map_bus, 475 .read = pci_generic_config_read, 476 .write = pci_generic_config_write, 477 }; 478 479 /** 480 * ks_pcie_link_up() - Check if link up 481 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 482 * controller driver information. 483 */ 484 static int ks_pcie_link_up(struct dw_pcie *pci) 485 { 486 u32 val; 487 488 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 489 val &= PORT_LOGIC_LTSSM_STATE_MASK; 490 return (val == PORT_LOGIC_LTSSM_STATE_L0); 491 } 492 493 static void ks_pcie_stop_link(struct dw_pcie *pci) 494 { 495 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 496 u32 val; 497 498 /* Disable Link training */ 499 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 500 val &= ~LTSSM_EN_VAL; 501 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 502 } 503 504 static int ks_pcie_start_link(struct dw_pcie *pci) 505 { 506 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 507 u32 val; 508 509 /* Initiate Link Training */ 510 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 511 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 512 513 return 0; 514 } 515 516 static void ks_pcie_quirk(struct pci_dev *dev) 517 { 518 struct pci_bus *bus = dev->bus; 519 struct keystone_pcie *ks_pcie; 520 struct device *bridge_dev; 521 struct pci_dev *bridge; 522 u32 val; 523 524 static const struct pci_device_id rc_pci_devids[] = { 525 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 526 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 527 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 528 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 529 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 530 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 531 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 532 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 533 { 0, }, 534 }; 535 static const struct pci_device_id am6_pci_devids[] = { 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), 537 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 538 { 0, }, 539 }; 540 541 if (pci_is_root_bus(bus)) 542 bridge = dev; 543 544 /* look for the host bridge */ 545 while (!pci_is_root_bus(bus)) { 546 bridge = bus->self; 547 bus = bus->parent; 548 } 549 550 if (!bridge) 551 return; 552 553 /* 554 * Keystone PCI controller has a h/w limitation of 555 * 256 bytes maximum read request size. It can't handle 556 * anything higher than this. So force this limit on 557 * all downstream devices. 558 */ 559 if (pci_match_id(rc_pci_devids, bridge)) { 560 if (pcie_get_readrq(dev) > 256) { 561 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); 562 pcie_set_readrq(dev, 256); 563 } 564 } 565 566 /* 567 * Memory transactions fail with PCI controller in AM654 PG1.0 568 * when MRRS is set to more than 128 bytes. Force the MRRS to 569 * 128 bytes in all downstream devices. 570 */ 571 if (pci_match_id(am6_pci_devids, bridge)) { 572 bridge_dev = pci_get_host_bridge_device(dev); 573 if (!bridge_dev || !bridge_dev->parent) 574 return; 575 576 ks_pcie = dev_get_drvdata(bridge_dev->parent); 577 if (!ks_pcie) 578 return; 579 580 val = ks_pcie_app_readl(ks_pcie, PID); 581 val &= RTL; 582 val >>= RTL_SHIFT; 583 if (val != AM6_PCI_PG1_RTL_VER) 584 return; 585 586 if (pcie_get_readrq(dev) > 128) { 587 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); 588 pcie_set_readrq(dev, 128); 589 } 590 } 591 } 592 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 593 594 static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 595 { 596 unsigned int irq = desc->irq_data.hwirq; 597 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 598 u32 offset = irq - ks_pcie->msi_host_irq; 599 struct dw_pcie *pci = ks_pcie->pci; 600 struct dw_pcie_rp *pp = &pci->pp; 601 struct device *dev = pci->dev; 602 struct irq_chip *chip = irq_desc_get_chip(desc); 603 u32 vector, reg, pos; 604 605 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 606 607 /* 608 * The chained irq handler installation would have replaced normal 609 * interrupt driver handler so we need to take care of mask/unmask and 610 * ack operation. 611 */ 612 chained_irq_enter(chip, desc); 613 614 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 615 /* 616 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 617 * shows 1, 9, 17, 25 and so forth 618 */ 619 for (pos = 0; pos < 4; pos++) { 620 if (!(reg & BIT(pos))) 621 continue; 622 623 vector = offset + (pos << 3); 624 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 625 generic_handle_domain_irq(pp->irq_domain, vector); 626 } 627 628 chained_irq_exit(chip, desc); 629 } 630 631 /** 632 * ks_pcie_intx_irq_handler() - Handle INTX interrupt 633 * @desc: Pointer to irq descriptor 634 * 635 * Traverse through pending INTX interrupts and invoke handler for each. Also 636 * takes care of interrupt controller level mask/ack operation. 637 */ 638 static void ks_pcie_intx_irq_handler(struct irq_desc *desc) 639 { 640 unsigned int irq = irq_desc_get_irq(desc); 641 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 642 struct dw_pcie *pci = ks_pcie->pci; 643 struct device *dev = pci->dev; 644 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; 645 struct irq_chip *chip = irq_desc_get_chip(desc); 646 647 dev_dbg(dev, ": Handling INTX irq %d\n", irq); 648 649 /* 650 * The chained irq handler installation would have replaced normal 651 * interrupt driver handler so we need to take care of mask/unmask and 652 * ack operation. 653 */ 654 chained_irq_enter(chip, desc); 655 ks_pcie_handle_intx_irq(ks_pcie, irq_offset); 656 chained_irq_exit(chip, desc); 657 } 658 659 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 660 { 661 struct device *dev = ks_pcie->pci->dev; 662 struct device_node *np = ks_pcie->np; 663 struct device_node *intc_np; 664 struct irq_data *irq_data; 665 int irq_count, irq, ret, i; 666 667 if (!IS_ENABLED(CONFIG_PCI_MSI)) 668 return 0; 669 670 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 671 if (!intc_np) { 672 if (ks_pcie->is_am6) 673 return 0; 674 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 675 return -EINVAL; 676 } 677 678 irq_count = of_irq_count(intc_np); 679 if (!irq_count) { 680 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 681 ret = -EINVAL; 682 goto err; 683 } 684 685 for (i = 0; i < irq_count; i++) { 686 irq = irq_of_parse_and_map(intc_np, i); 687 if (!irq) { 688 ret = -EINVAL; 689 goto err; 690 } 691 692 if (!ks_pcie->msi_host_irq) { 693 irq_data = irq_get_irq_data(irq); 694 if (!irq_data) { 695 ret = -EINVAL; 696 goto err; 697 } 698 ks_pcie->msi_host_irq = irq_data->hwirq; 699 } 700 701 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 702 ks_pcie); 703 } 704 705 of_node_put(intc_np); 706 return 0; 707 708 err: 709 of_node_put(intc_np); 710 return ret; 711 } 712 713 static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie) 714 { 715 struct device *dev = ks_pcie->pci->dev; 716 struct irq_domain *intx_irq_domain; 717 struct device_node *np = ks_pcie->np; 718 struct device_node *intc_np; 719 int irq_count, irq, ret = 0, i; 720 721 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 722 if (!intc_np) { 723 /* 724 * Since INTX interrupts are modeled as edge-interrupts in 725 * AM6, keep it disabled for now. 726 */ 727 if (ks_pcie->is_am6) 728 return 0; 729 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 730 return -EINVAL; 731 } 732 733 irq_count = of_irq_count(intc_np); 734 if (!irq_count) { 735 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 736 ret = -EINVAL; 737 goto err; 738 } 739 740 for (i = 0; i < irq_count; i++) { 741 irq = irq_of_parse_and_map(intc_np, i); 742 if (!irq) { 743 ret = -EINVAL; 744 goto err; 745 } 746 ks_pcie->intx_host_irqs[i] = irq; 747 748 irq_set_chained_handler_and_data(irq, 749 ks_pcie_intx_irq_handler, 750 ks_pcie); 751 } 752 753 intx_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX, 754 &ks_pcie_intx_irq_domain_ops, NULL); 755 if (!intx_irq_domain) { 756 dev_err(dev, "Failed to add irq domain for INTX irqs\n"); 757 ret = -EINVAL; 758 goto err; 759 } 760 ks_pcie->intx_irq_domain = intx_irq_domain; 761 762 for (i = 0; i < PCI_NUM_INTX; i++) 763 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 764 765 err: 766 of_node_put(intc_np); 767 return ret; 768 } 769 770 #ifdef CONFIG_ARM 771 /* 772 * When a PCI device does not exist during config cycles, keystone host 773 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 774 * This handler always returns 0 for this kind of fault. 775 */ 776 static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 777 struct pt_regs *regs) 778 { 779 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 780 781 if ((instr & 0x0e100090) == 0x00100090) { 782 int reg = (instr >> 12) & 15; 783 784 regs->uregs[reg] = -1; 785 regs->ARM_pc += 4; 786 } 787 788 return 0; 789 } 790 #endif 791 792 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 793 { 794 int ret; 795 unsigned int id; 796 struct regmap *devctrl_regs; 797 struct dw_pcie *pci = ks_pcie->pci; 798 struct device *dev = pci->dev; 799 struct device_node *np = dev->of_node; 800 struct of_phandle_args args; 801 unsigned int offset = 0; 802 803 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 804 if (IS_ERR(devctrl_regs)) 805 return PTR_ERR(devctrl_regs); 806 807 /* Do not error out to maintain old DT compatibility */ 808 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 809 if (!ret) 810 offset = args.args[0]; 811 812 ret = regmap_read(devctrl_regs, offset, &id); 813 if (ret) 814 return ret; 815 816 dw_pcie_dbi_ro_wr_en(pci); 817 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 818 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 819 dw_pcie_dbi_ro_wr_dis(pci); 820 821 return 0; 822 } 823 824 static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 825 { 826 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 827 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 828 int ret; 829 830 pp->bridge->ops = &ks_pcie_ops; 831 if (!ks_pcie->is_am6) 832 pp->bridge->child_ops = &ks_child_pcie_ops; 833 834 ret = ks_pcie_config_intx_irq(ks_pcie); 835 if (ret) 836 return ret; 837 838 ret = ks_pcie_config_msi_irq(ks_pcie); 839 if (ret) 840 return ret; 841 842 ks_pcie_stop_link(pci); 843 ret = ks_pcie_setup_rc_app_regs(ks_pcie); 844 if (ret) 845 return ret; 846 847 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 848 pci->dbi_base + PCI_IO_BASE); 849 850 ret = ks_pcie_init_id(ks_pcie); 851 if (ret < 0) 852 return ret; 853 854 #ifdef CONFIG_ARM 855 /* 856 * PCIe access errors that result into OCP errors are caught by ARM as 857 * "External aborts" 858 */ 859 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 860 "Asynchronous external abort"); 861 #endif 862 863 return 0; 864 } 865 866 static const struct dw_pcie_host_ops ks_pcie_host_ops = { 867 .init = ks_pcie_host_init, 868 .msi_init = ks_pcie_msi_host_init, 869 }; 870 871 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 872 .init = ks_pcie_host_init, 873 }; 874 875 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 876 { 877 struct keystone_pcie *ks_pcie = priv; 878 879 return ks_pcie_handle_error_irq(ks_pcie); 880 } 881 882 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 883 u32 reg, size_t size, u32 val) 884 { 885 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 886 887 ks_pcie_set_dbi_mode(ks_pcie); 888 dw_pcie_write(base + reg, size, val); 889 ks_pcie_clear_dbi_mode(ks_pcie); 890 } 891 892 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 893 .start_link = ks_pcie_start_link, 894 .stop_link = ks_pcie_stop_link, 895 .link_up = ks_pcie_link_up, 896 .write_dbi2 = ks_pcie_am654_write_dbi2, 897 }; 898 899 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 900 { 901 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 902 int flags; 903 904 ep->page_size = AM654_WIN_SIZE; 905 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 906 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 907 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 908 } 909 910 static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie) 911 { 912 struct dw_pcie *pci = ks_pcie->pci; 913 u8 int_pin; 914 915 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 916 if (int_pin == 0 || int_pin > 4) 917 return; 918 919 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 920 INT_ENABLE); 921 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 922 mdelay(1); 923 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 924 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 925 INT_ENABLE); 926 } 927 928 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 929 unsigned int type, u16 interrupt_num) 930 { 931 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 932 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 933 934 switch (type) { 935 case PCI_IRQ_INTX: 936 ks_pcie_am654_raise_intx_irq(ks_pcie); 937 break; 938 case PCI_IRQ_MSI: 939 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 940 break; 941 case PCI_IRQ_MSIX: 942 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 943 break; 944 default: 945 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 946 return -EINVAL; 947 } 948 949 return 0; 950 } 951 952 static const struct pci_epc_features ks_pcie_am654_epc_features = { 953 .linkup_notifier = false, 954 .msi_capable = true, 955 .msix_capable = true, 956 .bar[BAR_0] = { .type = BAR_RESERVED, }, 957 .bar[BAR_1] = { .type = BAR_RESERVED, }, 958 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 959 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 960 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, 961 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 962 .align = SZ_1M, 963 }; 964 965 static const struct pci_epc_features* 966 ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 967 { 968 return &ks_pcie_am654_epc_features; 969 } 970 971 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 972 .init = ks_pcie_am654_ep_init, 973 .raise_irq = ks_pcie_am654_raise_irq, 974 .get_features = &ks_pcie_am654_get_features, 975 }; 976 977 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 978 { 979 int num_lanes = ks_pcie->num_lanes; 980 981 while (num_lanes--) { 982 phy_power_off(ks_pcie->phy[num_lanes]); 983 phy_exit(ks_pcie->phy[num_lanes]); 984 } 985 } 986 987 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 988 { 989 int i; 990 int ret; 991 int num_lanes = ks_pcie->num_lanes; 992 993 for (i = 0; i < num_lanes; i++) { 994 ret = phy_reset(ks_pcie->phy[i]); 995 if (ret < 0) 996 goto err_phy; 997 998 ret = phy_init(ks_pcie->phy[i]); 999 if (ret < 0) 1000 goto err_phy; 1001 1002 ret = phy_power_on(ks_pcie->phy[i]); 1003 if (ret < 0) { 1004 phy_exit(ks_pcie->phy[i]); 1005 goto err_phy; 1006 } 1007 } 1008 1009 return 0; 1010 1011 err_phy: 1012 while (--i >= 0) { 1013 phy_power_off(ks_pcie->phy[i]); 1014 phy_exit(ks_pcie->phy[i]); 1015 } 1016 1017 return ret; 1018 } 1019 1020 static int ks_pcie_set_mode(struct device *dev) 1021 { 1022 struct device_node *np = dev->of_node; 1023 struct of_phandle_args args; 1024 unsigned int offset = 0; 1025 struct regmap *syscon; 1026 u32 val; 1027 u32 mask; 1028 int ret = 0; 1029 1030 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1031 if (IS_ERR(syscon)) 1032 return 0; 1033 1034 /* Do not error out to maintain old DT compatibility */ 1035 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1036 if (!ret) 1037 offset = args.args[0]; 1038 1039 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1040 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1041 1042 ret = regmap_update_bits(syscon, offset, mask, val); 1043 if (ret) { 1044 dev_err(dev, "failed to set pcie mode\n"); 1045 return ret; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int ks_pcie_am654_set_mode(struct device *dev, 1052 enum dw_pcie_device_mode mode) 1053 { 1054 struct device_node *np = dev->of_node; 1055 struct of_phandle_args args; 1056 unsigned int offset = 0; 1057 struct regmap *syscon; 1058 u32 val; 1059 u32 mask; 1060 int ret = 0; 1061 1062 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1063 if (IS_ERR(syscon)) 1064 return 0; 1065 1066 /* Do not error out to maintain old DT compatibility */ 1067 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1068 if (!ret) 1069 offset = args.args[0]; 1070 1071 mask = AM654_PCIE_DEV_TYPE_MASK; 1072 1073 switch (mode) { 1074 case DW_PCIE_RC_TYPE: 1075 val = RC; 1076 break; 1077 case DW_PCIE_EP_TYPE: 1078 val = EP; 1079 break; 1080 default: 1081 dev_err(dev, "INVALID device type %d\n", mode); 1082 return -EINVAL; 1083 } 1084 1085 ret = regmap_update_bits(syscon, offset, mask, val); 1086 if (ret) { 1087 dev_err(dev, "failed to set pcie mode\n"); 1088 return ret; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1095 .host_ops = &ks_pcie_host_ops, 1096 .version = DW_PCIE_VER_365A, 1097 }; 1098 1099 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1100 .host_ops = &ks_pcie_am654_host_ops, 1101 .mode = DW_PCIE_RC_TYPE, 1102 .version = DW_PCIE_VER_490A, 1103 }; 1104 1105 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1106 .ep_ops = &ks_pcie_am654_ep_ops, 1107 .mode = DW_PCIE_EP_TYPE, 1108 .version = DW_PCIE_VER_490A, 1109 }; 1110 1111 static const struct of_device_id ks_pcie_of_match[] = { 1112 { 1113 .type = "pci", 1114 .data = &ks_pcie_rc_of_data, 1115 .compatible = "ti,keystone-pcie", 1116 }, 1117 { 1118 .data = &ks_pcie_am654_rc_of_data, 1119 .compatible = "ti,am654-pcie-rc", 1120 }, 1121 { 1122 .data = &ks_pcie_am654_ep_of_data, 1123 .compatible = "ti,am654-pcie-ep", 1124 }, 1125 { }, 1126 }; 1127 1128 static int ks_pcie_probe(struct platform_device *pdev) 1129 { 1130 const struct dw_pcie_host_ops *host_ops; 1131 const struct dw_pcie_ep_ops *ep_ops; 1132 struct device *dev = &pdev->dev; 1133 struct device_node *np = dev->of_node; 1134 const struct ks_pcie_of_data *data; 1135 enum dw_pcie_device_mode mode; 1136 struct dw_pcie *pci; 1137 struct keystone_pcie *ks_pcie; 1138 struct device_link **link; 1139 struct gpio_desc *gpiod; 1140 struct resource *res; 1141 void __iomem *base; 1142 u32 num_viewport; 1143 struct phy **phy; 1144 u32 num_lanes; 1145 char name[10]; 1146 u32 version; 1147 int ret; 1148 int irq; 1149 int i; 1150 1151 data = of_device_get_match_data(dev); 1152 if (!data) 1153 return -EINVAL; 1154 1155 version = data->version; 1156 host_ops = data->host_ops; 1157 ep_ops = data->ep_ops; 1158 mode = data->mode; 1159 1160 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1161 if (!ks_pcie) 1162 return -ENOMEM; 1163 1164 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1165 if (!pci) 1166 return -ENOMEM; 1167 1168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1169 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1170 if (IS_ERR(ks_pcie->va_app_base)) 1171 return PTR_ERR(ks_pcie->va_app_base); 1172 1173 ks_pcie->app = *res; 1174 1175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1176 base = devm_pci_remap_cfg_resource(dev, res); 1177 if (IS_ERR(base)) 1178 return PTR_ERR(base); 1179 1180 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1181 ks_pcie->is_am6 = true; 1182 1183 pci->dbi_base = base; 1184 pci->dbi_base2 = base; 1185 pci->dev = dev; 1186 pci->ops = &ks_pcie_dw_pcie_ops; 1187 pci->version = version; 1188 1189 irq = platform_get_irq(pdev, 0); 1190 if (irq < 0) 1191 return irq; 1192 1193 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1194 "ks-pcie-error-irq", ks_pcie); 1195 if (ret < 0) { 1196 dev_err(dev, "failed to request error IRQ %d\n", 1197 irq); 1198 return ret; 1199 } 1200 1201 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1202 if (ret) 1203 num_lanes = 1; 1204 1205 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1206 if (!phy) 1207 return -ENOMEM; 1208 1209 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1210 if (!link) 1211 return -ENOMEM; 1212 1213 for (i = 0; i < num_lanes; i++) { 1214 snprintf(name, sizeof(name), "pcie-phy%d", i); 1215 phy[i] = devm_phy_optional_get(dev, name); 1216 if (IS_ERR(phy[i])) { 1217 ret = PTR_ERR(phy[i]); 1218 goto err_link; 1219 } 1220 1221 if (!phy[i]) 1222 continue; 1223 1224 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1225 if (!link[i]) { 1226 ret = -EINVAL; 1227 goto err_link; 1228 } 1229 } 1230 1231 ks_pcie->np = np; 1232 ks_pcie->pci = pci; 1233 ks_pcie->link = link; 1234 ks_pcie->num_lanes = num_lanes; 1235 ks_pcie->phy = phy; 1236 1237 gpiod = devm_gpiod_get_optional(dev, "reset", 1238 GPIOD_OUT_LOW); 1239 if (IS_ERR(gpiod)) { 1240 ret = PTR_ERR(gpiod); 1241 if (ret != -EPROBE_DEFER) 1242 dev_err(dev, "Failed to get reset GPIO\n"); 1243 goto err_link; 1244 } 1245 1246 /* Obtain references to the PHYs */ 1247 for (i = 0; i < num_lanes; i++) 1248 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1249 1250 ret = ks_pcie_enable_phy(ks_pcie); 1251 1252 /* Release references to the PHYs */ 1253 for (i = 0; i < num_lanes; i++) 1254 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1255 1256 if (ret) { 1257 dev_err(dev, "failed to enable phy\n"); 1258 goto err_link; 1259 } 1260 1261 platform_set_drvdata(pdev, ks_pcie); 1262 pm_runtime_enable(dev); 1263 ret = pm_runtime_get_sync(dev); 1264 if (ret < 0) { 1265 dev_err(dev, "pm_runtime_get_sync failed\n"); 1266 goto err_get_sync; 1267 } 1268 1269 if (dw_pcie_ver_is_ge(pci, 480A)) 1270 ret = ks_pcie_am654_set_mode(dev, mode); 1271 else 1272 ret = ks_pcie_set_mode(dev); 1273 if (ret < 0) 1274 goto err_get_sync; 1275 1276 switch (mode) { 1277 case DW_PCIE_RC_TYPE: 1278 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1279 ret = -ENODEV; 1280 goto err_get_sync; 1281 } 1282 1283 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1284 if (ret < 0) { 1285 dev_err(dev, "unable to read *num-viewport* property\n"); 1286 goto err_get_sync; 1287 } 1288 1289 /* 1290 * "Power Sequencing and Reset Signal Timings" table in 1291 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1292 * indicates PERST# should be deasserted after minimum of 100us 1293 * once REFCLK is stable. The REFCLK to the connector in RC 1294 * mode is selected while enabling the PHY. So deassert PERST# 1295 * after 100 us. 1296 */ 1297 if (gpiod) { 1298 usleep_range(100, 200); 1299 gpiod_set_value_cansleep(gpiod, 1); 1300 } 1301 1302 ks_pcie->num_viewport = num_viewport; 1303 pci->pp.ops = host_ops; 1304 ret = dw_pcie_host_init(&pci->pp); 1305 if (ret < 0) 1306 goto err_get_sync; 1307 break; 1308 case DW_PCIE_EP_TYPE: 1309 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1310 ret = -ENODEV; 1311 goto err_get_sync; 1312 } 1313 1314 pci->ep.ops = ep_ops; 1315 ret = dw_pcie_ep_init(&pci->ep); 1316 if (ret < 0) 1317 goto err_get_sync; 1318 1319 ret = dw_pcie_ep_init_registers(&pci->ep); 1320 if (ret) { 1321 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1322 goto err_ep_init; 1323 } 1324 1325 pci_epc_init_notify(pci->ep.epc); 1326 1327 break; 1328 default: 1329 dev_err(dev, "INVALID device type %d\n", mode); 1330 } 1331 1332 ks_pcie_enable_error_irq(ks_pcie); 1333 1334 return 0; 1335 1336 err_ep_init: 1337 dw_pcie_ep_deinit(&pci->ep); 1338 err_get_sync: 1339 pm_runtime_put(dev); 1340 pm_runtime_disable(dev); 1341 ks_pcie_disable_phy(ks_pcie); 1342 1343 err_link: 1344 while (--i >= 0 && link[i]) 1345 device_link_del(link[i]); 1346 1347 return ret; 1348 } 1349 1350 static void ks_pcie_remove(struct platform_device *pdev) 1351 { 1352 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1353 struct device_link **link = ks_pcie->link; 1354 int num_lanes = ks_pcie->num_lanes; 1355 struct device *dev = &pdev->dev; 1356 1357 pm_runtime_put(dev); 1358 pm_runtime_disable(dev); 1359 ks_pcie_disable_phy(ks_pcie); 1360 while (num_lanes--) 1361 device_link_del(link[num_lanes]); 1362 } 1363 1364 static struct platform_driver ks_pcie_driver = { 1365 .probe = ks_pcie_probe, 1366 .remove_new = ks_pcie_remove, 1367 .driver = { 1368 .name = "keystone-pcie", 1369 .of_match_table = ks_pcie_of_match, 1370 }, 1371 }; 1372 builtin_platform_driver(ks_pcie_driver); 1373