1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Kishon Vijay Abraham I <kishon@ti.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqchip/chained_irq.h> 17 #include <linux/irqdomain.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_pci.h> 22 #include <linux/pci.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/resource.h> 27 #include <linux/types.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/regmap.h> 30 #include <linux/gpio/consumer.h> 31 32 #include "../../pci.h" 33 #include "pcie-designware.h" 34 35 /* PCIe controller wrapper DRA7XX configuration registers */ 36 37 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 38 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 39 #define ERR_SYS BIT(0) 40 #define ERR_FATAL BIT(1) 41 #define ERR_NONFATAL BIT(2) 42 #define ERR_COR BIT(3) 43 #define ERR_AXI BIT(4) 44 #define ERR_ECRC BIT(5) 45 #define PME_TURN_OFF BIT(8) 46 #define PME_TO_ACK BIT(9) 47 #define PM_PME BIT(10) 48 #define LINK_REQ_RST BIT(11) 49 #define LINK_UP_EVT BIT(12) 50 #define CFG_BME_EVT BIT(13) 51 #define CFG_MSE_EVT BIT(14) 52 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ 53 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ 54 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) 55 56 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 57 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 58 #define INTA BIT(0) 59 #define INTB BIT(1) 60 #define INTC BIT(2) 61 #define INTD BIT(3) 62 #define MSI BIT(4) 63 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) 64 65 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100 66 #define DEVICE_TYPE_EP 0x0 67 #define DEVICE_TYPE_LEG_EP 0x1 68 #define DEVICE_TYPE_RC 0x4 69 70 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 71 #define LTSSM_EN 0x1 72 73 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C 74 #define LINK_UP BIT(16) 75 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF 76 77 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 78 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 79 80 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c 81 #define MSI_REQ_GRANT BIT(0) 82 #define MSI_VECTOR_SHIFT 7 83 84 #define PCIE_1LANE_2LANE_SELECTION BIT(13) 85 #define PCIE_B1C0_MODE_SEL BIT(2) 86 #define PCIE_B0_B1_TSYNCEN BIT(0) 87 88 struct dra7xx_pcie { 89 struct dw_pcie *pci; 90 void __iomem *base; /* DT ti_conf */ 91 int phy_count; /* DT phy-names count */ 92 struct phy **phy; 93 struct irq_domain *irq_domain; 94 struct clk *clk; 95 enum dw_pcie_device_mode mode; 96 }; 97 98 struct dra7xx_pcie_of_data { 99 enum dw_pcie_device_mode mode; 100 u32 b1co_mode_sel_mask; 101 }; 102 103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) 104 105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) 106 { 107 return readl(pcie->base + offset); 108 } 109 110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, 111 u32 value) 112 { 113 writel(value, pcie->base + offset); 114 } 115 116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) 117 { 118 return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; 119 } 120 121 static bool dra7xx_pcie_link_up(struct dw_pcie *pci) 122 { 123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 124 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); 125 126 return reg & LINK_UP; 127 } 128 129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci) 130 { 131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 132 u32 reg; 133 134 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 135 reg &= ~LTSSM_EN; 136 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 137 } 138 139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci) 140 { 141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 142 struct device *dev = pci->dev; 143 u32 reg; 144 145 if (dw_pcie_link_up(pci)) { 146 dev_err(dev, "link is already up\n"); 147 return 0; 148 } 149 150 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 151 reg |= LTSSM_EN; 152 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 153 154 return 0; 155 } 156 157 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) 158 { 159 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, 160 LEG_EP_INTERRUPTS | MSI); 161 162 dra7xx_pcie_writel(dra7xx, 163 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, 164 MSI | LEG_EP_INTERRUPTS); 165 } 166 167 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) 168 { 169 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, 170 INTERRUPTS); 171 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, 172 INTERRUPTS); 173 } 174 175 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) 176 { 177 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 178 dra7xx_pcie_enable_msi_interrupts(dra7xx); 179 } 180 181 static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp) 182 { 183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 185 186 dra7xx_pcie_enable_interrupts(dra7xx); 187 188 return 0; 189 } 190 191 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 192 irq_hw_number_t hwirq) 193 { 194 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 195 irq_set_chip_data(irq, domain->host_data); 196 197 return 0; 198 } 199 200 static const struct irq_domain_ops intx_domain_ops = { 201 .map = dra7xx_pcie_intx_map, 202 .xlate = pci_irqd_intx_xlate, 203 }; 204 205 static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index) 206 { 207 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 208 unsigned long val; 209 int pos; 210 211 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 212 (index * MSI_REG_CTRL_BLOCK_SIZE)); 213 if (!val) 214 return 0; 215 216 pos = find_first_bit(&val, MAX_MSI_IRQS_PER_CTRL); 217 while (pos != MAX_MSI_IRQS_PER_CTRL) { 218 generic_handle_domain_irq(pp->irq_domain, 219 (index * MAX_MSI_IRQS_PER_CTRL) + pos); 220 pos++; 221 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos); 222 } 223 224 return 1; 225 } 226 227 static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp) 228 { 229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 230 int ret, i, count, num_ctrls; 231 232 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 233 234 /** 235 * Need to make sure all MSI status bits read 0 before exiting. 236 * Else, new MSI IRQs are not registered by the wrapper. Have an 237 * upperbound for the loop and exit the IRQ in case of IRQ flood 238 * to avoid locking up system in interrupt context. 239 */ 240 count = 0; 241 do { 242 ret = 0; 243 244 for (i = 0; i < num_ctrls; i++) 245 ret |= dra7xx_pcie_handle_msi(pp, i); 246 count++; 247 } while (ret && count <= 1000); 248 249 if (count > 1000) 250 dev_warn_ratelimited(pci->dev, 251 "Too many MSI IRQs to handle\n"); 252 } 253 254 static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc) 255 { 256 struct irq_chip *chip = irq_desc_get_chip(desc); 257 struct dra7xx_pcie *dra7xx; 258 struct dw_pcie_rp *pp; 259 struct dw_pcie *pci; 260 unsigned long reg; 261 u32 bit; 262 263 chained_irq_enter(chip, desc); 264 265 pp = irq_desc_get_handler_data(desc); 266 pci = to_dw_pcie_from_pp(pp); 267 dra7xx = to_dra7xx_pcie(pci); 268 269 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); 270 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); 271 272 switch (reg) { 273 case MSI: 274 dra7xx_pcie_handle_msi_irq(pp); 275 break; 276 case INTA: 277 case INTB: 278 case INTC: 279 case INTD: 280 for_each_set_bit(bit, ®, PCI_NUM_INTX) 281 generic_handle_domain_irq(dra7xx->irq_domain, bit); 282 break; 283 } 284 285 chained_irq_exit(chip, desc); 286 } 287 288 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) 289 { 290 struct dra7xx_pcie *dra7xx = arg; 291 struct dw_pcie *pci = dra7xx->pci; 292 struct device *dev = pci->dev; 293 struct dw_pcie_ep *ep = &pci->ep; 294 u32 reg; 295 296 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); 297 298 if (reg & ERR_SYS) 299 dev_dbg(dev, "System Error\n"); 300 301 if (reg & ERR_FATAL) 302 dev_dbg(dev, "Fatal Error\n"); 303 304 if (reg & ERR_NONFATAL) 305 dev_dbg(dev, "Non Fatal Error\n"); 306 307 if (reg & ERR_COR) 308 dev_dbg(dev, "Correctable Error\n"); 309 310 if (reg & ERR_AXI) 311 dev_dbg(dev, "AXI tag lookup fatal Error\n"); 312 313 if (reg & ERR_ECRC) 314 dev_dbg(dev, "ECRC Error\n"); 315 316 if (reg & PME_TURN_OFF) 317 dev_dbg(dev, 318 "Power Management Event Turn-Off message received\n"); 319 320 if (reg & PME_TO_ACK) 321 dev_dbg(dev, 322 "Power Management Turn-Off Ack message received\n"); 323 324 if (reg & PM_PME) 325 dev_dbg(dev, "PM Power Management Event message received\n"); 326 327 if (reg & LINK_REQ_RST) 328 dev_dbg(dev, "Link Request Reset\n"); 329 330 if (reg & LINK_UP_EVT) { 331 if (dra7xx->mode == DW_PCIE_EP_TYPE) 332 dw_pcie_ep_linkup(ep); 333 dev_dbg(dev, "Link-up state change\n"); 334 } 335 336 if (reg & CFG_BME_EVT) 337 dev_dbg(dev, "CFG 'Bus Master Enable' change\n"); 338 339 if (reg & CFG_MSE_EVT) 340 dev_dbg(dev, "CFG 'Memory Space Enable' change\n"); 341 342 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); 343 344 return IRQ_HANDLED; 345 } 346 347 static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp) 348 { 349 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 350 struct device *dev = pci->dev; 351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 352 struct device_node *node = dev->of_node; 353 struct device_node *pcie_intc_node = of_get_next_child(node, NULL); 354 355 if (!pcie_intc_node) { 356 dev_err(dev, "No PCIe Intc node found\n"); 357 return -ENODEV; 358 } 359 360 irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler, 361 pp); 362 dra7xx->irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), 363 PCI_NUM_INTX, &intx_domain_ops, pp); 364 of_node_put(pcie_intc_node); 365 if (!dra7xx->irq_domain) { 366 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 367 return -ENODEV; 368 } 369 370 return 0; 371 } 372 373 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { 374 .init = dra7xx_pcie_host_init, 375 }; 376 377 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) 378 { 379 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 380 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 381 enum pci_barno bar; 382 383 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 384 dw_pcie_ep_reset_bar(pci, bar); 385 386 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 387 } 388 389 static void dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie *dra7xx) 390 { 391 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1); 392 mdelay(1); 393 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1); 394 } 395 396 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, 397 u8 interrupt_num) 398 { 399 u32 reg; 400 401 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; 402 reg |= MSI_REQ_GRANT; 403 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); 404 } 405 406 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 407 unsigned int type, u16 interrupt_num) 408 { 409 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 410 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 411 412 switch (type) { 413 case PCI_IRQ_INTX: 414 dra7xx_pcie_raise_intx_irq(dra7xx); 415 break; 416 case PCI_IRQ_MSI: 417 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num); 418 break; 419 default: 420 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 421 } 422 423 return 0; 424 } 425 426 static const struct pci_epc_features dra7xx_pcie_epc_features = { 427 .linkup_notifier = true, 428 .msi_capable = true, 429 }; 430 431 static const struct pci_epc_features* 432 dra7xx_pcie_get_features(struct dw_pcie_ep *ep) 433 { 434 return &dra7xx_pcie_epc_features; 435 } 436 437 static const struct dw_pcie_ep_ops pcie_ep_ops = { 438 .init = dra7xx_pcie_ep_init, 439 .raise_irq = dra7xx_pcie_raise_irq, 440 .get_features = dra7xx_pcie_get_features, 441 }; 442 443 static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, 444 struct platform_device *pdev) 445 { 446 int ret; 447 struct dw_pcie_ep *ep; 448 struct device *dev = &pdev->dev; 449 struct dw_pcie *pci = dra7xx->pci; 450 451 ep = &pci->ep; 452 ep->ops = &pcie_ep_ops; 453 454 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics"); 455 if (IS_ERR(pci->dbi_base)) 456 return PTR_ERR(pci->dbi_base); 457 458 pci->dbi_base2 = 459 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2"); 460 if (IS_ERR(pci->dbi_base2)) 461 return PTR_ERR(pci->dbi_base2); 462 463 ret = dw_pcie_ep_init(ep); 464 if (ret) { 465 dev_err(dev, "failed to initialize endpoint\n"); 466 return ret; 467 } 468 469 ret = dw_pcie_ep_init_registers(ep); 470 if (ret) { 471 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 472 dw_pcie_ep_deinit(ep); 473 return ret; 474 } 475 476 pci_epc_init_notify(ep->epc); 477 478 return 0; 479 } 480 481 static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 482 struct platform_device *pdev) 483 { 484 int ret; 485 struct dw_pcie *pci = dra7xx->pci; 486 struct dw_pcie_rp *pp = &pci->pp; 487 struct device *dev = pci->dev; 488 489 pp->irq = platform_get_irq(pdev, 1); 490 if (pp->irq < 0) 491 return pp->irq; 492 493 /* MSI IRQ is muxed */ 494 pp->msi_irq[0] = -ENODEV; 495 496 ret = dra7xx_pcie_init_irq_domain(pp); 497 if (ret < 0) 498 return ret; 499 500 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics"); 501 if (IS_ERR(pci->dbi_base)) 502 return PTR_ERR(pci->dbi_base); 503 504 pp->ops = &dra7xx_pcie_host_ops; 505 506 ret = dw_pcie_host_init(pp); 507 if (ret) { 508 dev_err(dev, "failed to initialize host\n"); 509 return ret; 510 } 511 512 return 0; 513 } 514 515 static const struct dw_pcie_ops dw_pcie_ops = { 516 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, 517 .start_link = dra7xx_pcie_establish_link, 518 .stop_link = dra7xx_pcie_stop_link, 519 .link_up = dra7xx_pcie_link_up, 520 }; 521 522 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) 523 { 524 int phy_count = dra7xx->phy_count; 525 526 while (phy_count--) { 527 phy_power_off(dra7xx->phy[phy_count]); 528 phy_exit(dra7xx->phy[phy_count]); 529 } 530 } 531 532 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) 533 { 534 int phy_count = dra7xx->phy_count; 535 int ret; 536 int i; 537 538 for (i = 0; i < phy_count; i++) { 539 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE); 540 if (ret < 0) 541 goto err_phy; 542 543 ret = phy_init(dra7xx->phy[i]); 544 if (ret < 0) 545 goto err_phy; 546 547 ret = phy_power_on(dra7xx->phy[i]); 548 if (ret < 0) { 549 phy_exit(dra7xx->phy[i]); 550 goto err_phy; 551 } 552 } 553 554 return 0; 555 556 err_phy: 557 while (--i >= 0) { 558 phy_power_off(dra7xx->phy[i]); 559 phy_exit(dra7xx->phy[i]); 560 } 561 562 return ret; 563 } 564 565 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = { 566 .mode = DW_PCIE_RC_TYPE, 567 }; 568 569 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { 570 .mode = DW_PCIE_EP_TYPE, 571 }; 572 573 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { 574 .b1co_mode_sel_mask = BIT(2), 575 .mode = DW_PCIE_RC_TYPE, 576 }; 577 578 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = { 579 .b1co_mode_sel_mask = GENMASK(3, 2), 580 .mode = DW_PCIE_RC_TYPE, 581 }; 582 583 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { 584 .b1co_mode_sel_mask = BIT(2), 585 .mode = DW_PCIE_EP_TYPE, 586 }; 587 588 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = { 589 .b1co_mode_sel_mask = GENMASK(3, 2), 590 .mode = DW_PCIE_EP_TYPE, 591 }; 592 593 static const struct of_device_id of_dra7xx_pcie_match[] = { 594 { 595 .compatible = "ti,dra7-pcie", 596 .data = &dra7xx_pcie_rc_of_data, 597 }, 598 { 599 .compatible = "ti,dra7-pcie-ep", 600 .data = &dra7xx_pcie_ep_of_data, 601 }, 602 { 603 .compatible = "ti,dra746-pcie-rc", 604 .data = &dra746_pcie_rc_of_data, 605 }, 606 { 607 .compatible = "ti,dra726-pcie-rc", 608 .data = &dra726_pcie_rc_of_data, 609 }, 610 { 611 .compatible = "ti,dra746-pcie-ep", 612 .data = &dra746_pcie_ep_of_data, 613 }, 614 { 615 .compatible = "ti,dra726-pcie-ep", 616 .data = &dra726_pcie_ep_of_data, 617 }, 618 {}, 619 }; 620 MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match); 621 622 /* 623 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 624 * @dra7xx: the dra7xx device where the workaround should be applied 625 * 626 * Access to the PCIe slave port that are not 32-bit aligned will result 627 * in incorrect mapping to TLP Address and Byte enable fields. Therefore, 628 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 629 * 0x3. 630 * 631 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. 632 */ 633 static int dra7xx_pcie_unaligned_memaccess(struct device *dev) 634 { 635 int ret; 636 struct device_node *np = dev->of_node; 637 unsigned int args[2]; 638 struct regmap *regmap; 639 640 regmap = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-unaligned-access", 641 2, args); 642 if (IS_ERR(regmap)) { 643 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); 644 return -EINVAL; 645 } 646 647 ret = regmap_update_bits(regmap, args[0], args[1], args[1]); 648 if (ret) 649 dev_err(dev, "failed to enable unaligned access\n"); 650 651 return ret; 652 } 653 654 static int dra7xx_pcie_configure_two_lane(struct device *dev, 655 u32 b1co_mode_sel_mask) 656 { 657 struct device_node *np = dev->of_node; 658 struct regmap *pcie_syscon; 659 unsigned int pcie_reg; 660 u32 mask; 661 u32 val; 662 663 pcie_syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-lane-sel", 664 1, &pcie_reg); 665 if (IS_ERR(pcie_syscon)) { 666 dev_err(dev, "unable to get ti,syscon-lane-sel\n"); 667 return -EINVAL; 668 } 669 670 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN; 671 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN; 672 regmap_update_bits(pcie_syscon, pcie_reg, mask, val); 673 674 return 0; 675 } 676 677 static int dra7xx_pcie_probe(struct platform_device *pdev) 678 { 679 u32 reg; 680 int ret; 681 int irq; 682 int i; 683 int phy_count; 684 struct phy **phy; 685 struct device_link **link; 686 void __iomem *base; 687 struct dw_pcie *pci; 688 struct dra7xx_pcie *dra7xx; 689 struct device *dev = &pdev->dev; 690 struct device_node *np = dev->of_node; 691 char name[10]; 692 struct gpio_desc *reset; 693 const struct dra7xx_pcie_of_data *data; 694 enum dw_pcie_device_mode mode; 695 u32 b1co_mode_sel_mask; 696 697 data = of_device_get_match_data(dev); 698 if (!data) 699 return -EINVAL; 700 701 mode = (enum dw_pcie_device_mode)data->mode; 702 b1co_mode_sel_mask = data->b1co_mode_sel_mask; 703 704 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); 705 if (!dra7xx) 706 return -ENOMEM; 707 708 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 709 if (!pci) 710 return -ENOMEM; 711 712 pci->dev = dev; 713 pci->ops = &dw_pcie_ops; 714 715 irq = platform_get_irq(pdev, 0); 716 if (irq < 0) 717 return irq; 718 719 base = devm_platform_ioremap_resource_byname(pdev, "ti_conf"); 720 if (IS_ERR(base)) 721 return PTR_ERR(base); 722 723 phy_count = of_property_count_strings(np, "phy-names"); 724 if (phy_count < 0) { 725 dev_err(dev, "unable to find the strings\n"); 726 return phy_count; 727 } 728 729 phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); 730 if (!phy) 731 return -ENOMEM; 732 733 link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); 734 if (!link) 735 return -ENOMEM; 736 737 dra7xx->clk = devm_clk_get_optional(dev, NULL); 738 if (IS_ERR(dra7xx->clk)) 739 return dev_err_probe(dev, PTR_ERR(dra7xx->clk), 740 "clock request failed"); 741 742 ret = clk_prepare_enable(dra7xx->clk); 743 if (ret) 744 return ret; 745 746 for (i = 0; i < phy_count; i++) { 747 snprintf(name, sizeof(name), "pcie-phy%d", i); 748 phy[i] = devm_phy_get(dev, name); 749 if (IS_ERR(phy[i])) 750 return PTR_ERR(phy[i]); 751 752 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 753 if (!link[i]) { 754 ret = -EINVAL; 755 goto err_link; 756 } 757 } 758 759 dra7xx->base = base; 760 dra7xx->phy = phy; 761 dra7xx->pci = pci; 762 dra7xx->phy_count = phy_count; 763 764 if (phy_count == 2) { 765 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); 766 if (ret < 0) 767 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */ 768 } 769 770 ret = dra7xx_pcie_enable_phy(dra7xx); 771 if (ret) { 772 dev_err(dev, "failed to enable phy\n"); 773 return ret; 774 } 775 776 platform_set_drvdata(pdev, dra7xx); 777 778 pm_runtime_enable(dev); 779 ret = pm_runtime_get_sync(dev); 780 if (ret < 0) { 781 dev_err(dev, "pm_runtime_get_sync failed\n"); 782 goto err_get_sync; 783 } 784 785 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); 786 if (IS_ERR(reset)) { 787 ret = PTR_ERR(reset); 788 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 789 goto err_gpio; 790 } 791 792 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 793 reg &= ~LTSSM_EN; 794 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 795 796 switch (mode) { 797 case DW_PCIE_RC_TYPE: 798 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) { 799 ret = -ENODEV; 800 goto err_gpio; 801 } 802 803 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 804 DEVICE_TYPE_RC); 805 806 ret = dra7xx_pcie_unaligned_memaccess(dev); 807 if (ret) 808 dev_err(dev, "WA for Errata i870 not applied\n"); 809 810 ret = dra7xx_add_pcie_port(dra7xx, pdev); 811 if (ret < 0) 812 goto err_gpio; 813 break; 814 case DW_PCIE_EP_TYPE: 815 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) { 816 ret = -ENODEV; 817 goto err_gpio; 818 } 819 820 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 821 DEVICE_TYPE_EP); 822 823 ret = dra7xx_pcie_unaligned_memaccess(dev); 824 if (ret) 825 goto err_gpio; 826 827 ret = dra7xx_add_pcie_ep(dra7xx, pdev); 828 if (ret < 0) 829 goto err_gpio; 830 break; 831 default: 832 dev_err(dev, "INVALID device type %d\n", mode); 833 } 834 dra7xx->mode = mode; 835 836 ret = devm_request_threaded_irq(dev, irq, NULL, dra7xx_pcie_irq_handler, 837 IRQF_SHARED | IRQF_ONESHOT, 838 "dra7xx-pcie-main", dra7xx); 839 if (ret) { 840 dev_err(dev, "failed to request irq\n"); 841 goto err_deinit; 842 } 843 844 return 0; 845 846 err_deinit: 847 if (dra7xx->mode == DW_PCIE_RC_TYPE) 848 dw_pcie_host_deinit(&dra7xx->pci->pp); 849 else 850 dw_pcie_ep_deinit(&dra7xx->pci->ep); 851 852 err_gpio: 853 err_get_sync: 854 pm_runtime_put(dev); 855 pm_runtime_disable(dev); 856 dra7xx_pcie_disable_phy(dra7xx); 857 858 err_link: 859 while (--i >= 0) 860 device_link_del(link[i]); 861 862 return ret; 863 } 864 865 static int dra7xx_pcie_suspend(struct device *dev) 866 { 867 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 868 struct dw_pcie *pci = dra7xx->pci; 869 u32 val; 870 871 if (dra7xx->mode != DW_PCIE_RC_TYPE) 872 return 0; 873 874 /* clear MSE */ 875 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 876 val &= ~PCI_COMMAND_MEMORY; 877 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 878 879 return 0; 880 } 881 882 static int dra7xx_pcie_resume(struct device *dev) 883 { 884 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 885 struct dw_pcie *pci = dra7xx->pci; 886 u32 val; 887 888 if (dra7xx->mode != DW_PCIE_RC_TYPE) 889 return 0; 890 891 /* set MSE */ 892 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 893 val |= PCI_COMMAND_MEMORY; 894 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 895 896 return 0; 897 } 898 899 static int dra7xx_pcie_suspend_noirq(struct device *dev) 900 { 901 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 902 903 dra7xx_pcie_disable_phy(dra7xx); 904 905 return 0; 906 } 907 908 static int dra7xx_pcie_resume_noirq(struct device *dev) 909 { 910 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 911 int ret; 912 913 ret = dra7xx_pcie_enable_phy(dra7xx); 914 if (ret) { 915 dev_err(dev, "failed to enable phy\n"); 916 return ret; 917 } 918 919 return 0; 920 } 921 922 static void dra7xx_pcie_shutdown(struct platform_device *pdev) 923 { 924 struct device *dev = &pdev->dev; 925 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 926 int ret; 927 928 dra7xx_pcie_stop_link(dra7xx->pci); 929 930 ret = pm_runtime_put_sync(dev); 931 if (ret < 0) 932 dev_dbg(dev, "pm_runtime_put_sync failed\n"); 933 934 pm_runtime_disable(dev); 935 dra7xx_pcie_disable_phy(dra7xx); 936 937 clk_disable_unprepare(dra7xx->clk); 938 } 939 940 static const struct dev_pm_ops dra7xx_pcie_pm_ops = { 941 SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) 942 NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, 943 dra7xx_pcie_resume_noirq) 944 }; 945 946 static struct platform_driver dra7xx_pcie_driver = { 947 .probe = dra7xx_pcie_probe, 948 .driver = { 949 .name = "dra7-pcie", 950 .of_match_table = of_dra7xx_pcie_match, 951 .suppress_bind_attrs = true, 952 .pm = &dra7xx_pcie_pm_ops, 953 }, 954 .shutdown = dra7xx_pcie_shutdown, 955 }; 956 module_platform_driver(dra7xx_pcie_driver); 957 958 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); 959 MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs"); 960 MODULE_LICENSE("GPL v2"); 961