1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (c) 2017 Cadence 3 // Cadence PCIe controller driver. 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 6 #ifndef _PCIE_CADENCE_H 7 #define _PCIE_CADENCE_H 8 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/pci-epf.h> 12 #include <linux/phy/phy.h> 13 14 /* Parameters for the waiting for link up routine */ 15 #define LINK_WAIT_MAX_RETRIES 10 16 #define LINK_WAIT_USLEEP_MIN 90000 17 #define LINK_WAIT_USLEEP_MAX 100000 18 19 /* 20 * Local Management Registers 21 */ 22 #define CDNS_PCIE_LM_BASE 0x00100000 23 24 /* Vendor ID Register */ 25 #define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) 26 #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) 27 #define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 28 #define CDNS_PCIE_LM_ID_VENDOR(vid) \ 29 (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) 30 #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) 31 #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 32 #define CDNS_PCIE_LM_ID_SUBSYS(sub) \ 33 (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) 34 35 /* Root Port Requester ID Register */ 36 #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) 37 #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) 38 #define CDNS_PCIE_LM_RP_RID_SHIFT 0 39 #define CDNS_PCIE_LM_RP_RID_(rid) \ 40 (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) 41 42 /* Endpoint Bus and Device Number Register */ 43 #define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) 44 #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) 45 #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 46 #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) 47 #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 48 49 /* Endpoint Function f BAR b Configuration Registers */ 50 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ 51 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) 52 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ 53 (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) 54 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ 55 (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) 56 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ 57 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) 58 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ 59 (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) 60 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ 61 (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) 62 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ 63 (GENMASK(4, 0) << ((b) * 8)) 64 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ 65 (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) 66 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ 67 (GENMASK(7, 5) << ((b) * 8)) 68 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ 69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) 70 71 /* Endpoint Function Configuration Register */ 72 #define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) 73 74 /* Root Complex BAR Configuration Register */ 75 #define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) 76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) 77 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ 78 (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) 79 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) 80 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ 81 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) 82 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) 83 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ 84 (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) 85 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) 86 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ 87 (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) 88 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) 89 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 90 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) 91 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) 92 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 93 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) 94 #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) 95 96 /* BAR control values applicable to both Endpoint Function and Root Complex */ 97 #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 98 #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 99 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 100 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 101 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 102 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 103 104 #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ 105 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) 106 #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ 107 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) 108 #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ 109 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) 110 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ 111 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) 112 #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ 113 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) 114 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ 115 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) 116 #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ 117 (((aperture) - 2) << ((bar) * 8)) 118 119 /* PTM Control Register */ 120 #define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) 121 #define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) 122 123 /* 124 * Endpoint Function Registers (PCI configuration space for endpoint functions) 125 */ 126 #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) 127 128 /* 129 * Endpoint PF Registers 130 */ 131 #define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) 132 #define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) 133 134 /* 135 * Root Port Registers (PCI configuration space for the root port function) 136 */ 137 #define CDNS_PCIE_RP_BASE 0x00200000 138 #define CDNS_PCIE_RP_CAP_OFFSET 0xc0 139 140 /* 141 * Address Translation Registers 142 */ 143 #define CDNS_PCIE_AT_BASE 0x00400000 144 145 /* Region r Outbound AXI to PCIe Address Translation Register 0 */ 146 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ 147 (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) 148 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) 149 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ 150 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) 151 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) 152 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ 153 (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) 154 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) 155 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ 156 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) 157 158 /* Region r Outbound AXI to PCIe Address Translation Register 1 */ 159 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ 160 (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) 161 162 /* Region r Outbound PCIe Descriptor Register 0 */ 163 #define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ 164 (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) 165 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) 166 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 167 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 168 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa 169 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb 170 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc 171 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd 172 /* Bit 23 MUST be set in RC mode. */ 173 #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) 174 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) 175 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ 176 (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) 177 178 /* Region r Outbound PCIe Descriptor Register 1 */ 179 #define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ 180 (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) 181 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) 182 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ 183 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) 184 185 /* Region r AXI Region Base Address Register 0 */ 186 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ 187 (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) 188 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) 189 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ 190 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) 191 192 /* Region r AXI Region Base Address Register 1 */ 193 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ 194 (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) 195 196 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */ 197 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ 198 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) 199 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) 200 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ 201 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) 202 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ 203 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) 204 205 /* AXI link down register */ 206 #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) 207 208 /* LTSSM Capabilities register */ 209 #define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) 210 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) 211 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 212 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ 213 (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ 214 CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) 215 216 enum cdns_pcie_rp_bar { 217 RP_BAR_UNDEFINED = -1, 218 RP_BAR0, 219 RP_BAR1, 220 RP_NO_BAR 221 }; 222 223 #define CDNS_PCIE_RP_MAX_IB 0x3 224 #define CDNS_PCIE_MAX_OB 32 225 226 struct cdns_pcie_rp_ib_bar { 227 u64 size; 228 bool free; 229 }; 230 231 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ 232 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ 233 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) 234 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ 235 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) 236 237 /* Normal/Vendor specific message access: offset inside some outbound region */ 238 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) 239 #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ 240 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) 241 #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) 242 #define CDNS_PCIE_NORMAL_MSG_CODE(code) \ 243 (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) 244 #define CDNS_PCIE_MSG_DATA BIT(16) 245 246 struct cdns_pcie; 247 248 struct cdns_pcie_ops { 249 int (*start_link)(struct cdns_pcie *pcie); 250 void (*stop_link)(struct cdns_pcie *pcie); 251 bool (*link_up)(struct cdns_pcie *pcie); 252 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); 253 }; 254 255 /** 256 * struct cdns_pcie - private data for Cadence PCIe controller drivers 257 * @reg_base: IO mapped register base 258 * @mem_res: start/end offsets in the physical system memory to map PCI accesses 259 * @dev: PCIe controller 260 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. 261 * @phy_count: number of supported PHY devices 262 * @phy: list of pointers to specific PHY control blocks 263 * @link: list of pointers to corresponding device link representations 264 * @ops: Platform-specific ops to control various inputs from Cadence PCIe 265 * wrapper 266 */ 267 struct cdns_pcie { 268 void __iomem *reg_base; 269 struct resource *mem_res; 270 struct device *dev; 271 bool is_rc; 272 int phy_count; 273 struct phy **phy; 274 struct device_link **link; 275 const struct cdns_pcie_ops *ops; 276 }; 277 278 /** 279 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver 280 * @pcie: Cadence PCIe controller 281 * @cfg_res: start/end offsets in the physical system memory to map PCI 282 * configuration space accesses 283 * @cfg_base: IO mapped window to access the PCI configuration space of a 284 * single function at a time 285 * @vendor_id: PCI vendor ID 286 * @device_id: PCI device ID 287 * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or 288 * available 289 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 290 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk 291 */ 292 struct cdns_pcie_rc { 293 struct cdns_pcie pcie; 294 struct resource *cfg_res; 295 void __iomem *cfg_base; 296 u32 vendor_id; 297 u32 device_id; 298 bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; 299 unsigned int quirk_retrain_flag:1; 300 unsigned int quirk_detect_quiet_flag:1; 301 }; 302 303 /** 304 * struct cdns_pcie_epf - Structure to hold info about endpoint function 305 * @epf: Info about virtual functions attached to the physical function 306 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers 307 */ 308 struct cdns_pcie_epf { 309 struct cdns_pcie_epf *epf; 310 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; 311 }; 312 313 /** 314 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver 315 * @pcie: Cadence PCIe controller 316 * @max_regions: maximum number of regions supported by hardware 317 * @ob_region_map: bitmask of mapped outbound regions 318 * @ob_addr: base addresses in the AXI bus where the outbound regions start 319 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ 320 * dedicated outbound regions is mapped. 321 * @irq_cpu_addr: base address in the CPU space where a write access triggers 322 * the sending of a memory write (MSI) / normal message (INTX 323 * IRQ) TLP through the PCIe bus. 324 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ 325 * dedicated outbound region. 326 * @irq_pci_fn: the latest PCI function that has updated the mapping of 327 * the MSI/INTX IRQ dedicated outbound region. 328 * @irq_pending: bitmask of asserted INTX IRQs. 329 * @lock: spin lock to disable interrupts while modifying PCIe controller 330 * registers fields (RMW) accessible by both remote RC and EP to 331 * minimize time between read and write 332 * @epf: Structure to hold info about endpoint function 333 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk 334 * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag 335 */ 336 struct cdns_pcie_ep { 337 struct cdns_pcie pcie; 338 u32 max_regions; 339 unsigned long ob_region_map; 340 phys_addr_t *ob_addr; 341 phys_addr_t irq_phys_addr; 342 void __iomem *irq_cpu_addr; 343 u64 irq_pci_addr; 344 u8 irq_pci_fn; 345 u8 irq_pending; 346 /* protect writing to PCI_STATUS while raising INTX interrupts */ 347 spinlock_t lock; 348 struct cdns_pcie_epf *epf; 349 unsigned int quirk_detect_quiet_flag:1; 350 unsigned int quirk_disable_flr:1; 351 }; 352 353 354 /* Register access */ 355 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) 356 { 357 writel(value, pcie->reg_base + reg); 358 } 359 360 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) 361 { 362 return readl(pcie->reg_base + reg); 363 } 364 365 static inline u16 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) 366 { 367 return readw(pcie->reg_base + reg); 368 } 369 370 static inline u8 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) 371 { 372 return readb(pcie->reg_base + reg); 373 } 374 375 static inline int cdns_pcie_read_cfg_byte(struct cdns_pcie *pcie, int where, 376 u8 *val) 377 { 378 *val = cdns_pcie_readb(pcie, where); 379 return PCIBIOS_SUCCESSFUL; 380 } 381 382 static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int where, 383 u16 *val) 384 { 385 *val = cdns_pcie_readw(pcie, where); 386 return PCIBIOS_SUCCESSFUL; 387 } 388 389 static inline int cdns_pcie_read_cfg_dword(struct cdns_pcie *pcie, int where, 390 u32 *val) 391 { 392 *val = cdns_pcie_readl(pcie, where); 393 return PCIBIOS_SUCCESSFUL; 394 } 395 396 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) 397 { 398 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 399 unsigned int offset = (unsigned long)addr & 0x3; 400 u32 val = readl(aligned_addr); 401 402 if (!IS_ALIGNED((uintptr_t)addr, size)) { 403 pr_warn("Address %p and size %d are not aligned\n", addr, size); 404 return 0; 405 } 406 407 if (size > 2) 408 return val; 409 410 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); 411 } 412 413 static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) 414 { 415 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 416 unsigned int offset = (unsigned long)addr & 0x3; 417 u32 mask; 418 u32 val; 419 420 if (!IS_ALIGNED((uintptr_t)addr, size)) { 421 pr_warn("Address %p and size %d are not aligned\n", addr, size); 422 return; 423 } 424 425 if (size > 2) { 426 writel(value, addr); 427 return; 428 } 429 430 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); 431 val = readl(aligned_addr) & mask; 432 val |= value << (offset * 8); 433 writel(val, aligned_addr); 434 } 435 436 /* Root Port register access */ 437 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, 438 u32 reg, u8 value) 439 { 440 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 441 442 cdns_pcie_write_sz(addr, 0x1, value); 443 } 444 445 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, 446 u32 reg, u16 value) 447 { 448 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 449 450 cdns_pcie_write_sz(addr, 0x2, value); 451 } 452 453 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) 454 { 455 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 456 457 return cdns_pcie_read_sz(addr, 0x2); 458 } 459 460 /* Endpoint Function register access */ 461 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, 462 u32 reg, u8 value) 463 { 464 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 465 466 cdns_pcie_write_sz(addr, 0x1, value); 467 } 468 469 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, 470 u32 reg, u16 value) 471 { 472 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 473 474 cdns_pcie_write_sz(addr, 0x2, value); 475 } 476 477 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, 478 u32 reg, u32 value) 479 { 480 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 481 } 482 483 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) 484 { 485 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 486 487 return cdns_pcie_read_sz(addr, 0x2); 488 } 489 490 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) 491 { 492 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 493 } 494 495 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) 496 { 497 if (pcie->ops && pcie->ops->start_link) 498 return pcie->ops->start_link(pcie); 499 500 return 0; 501 } 502 503 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) 504 { 505 if (pcie->ops && pcie->ops->stop_link) 506 pcie->ops->stop_link(pcie); 507 } 508 509 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) 510 { 511 if (pcie->ops && pcie->ops->link_up) 512 return pcie->ops->link_up(pcie); 513 514 return true; 515 } 516 517 #if IS_ENABLED(CONFIG_PCIE_CADENCE_HOST) 518 int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc); 519 int cdns_pcie_host_init(struct cdns_pcie_rc *rc); 520 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); 521 void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); 522 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 523 int where); 524 #else 525 static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) 526 { 527 return 0; 528 } 529 530 static inline int cdns_pcie_host_init(struct cdns_pcie_rc *rc) 531 { 532 return 0; 533 } 534 535 static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 536 { 537 return 0; 538 } 539 540 static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) 541 { 542 } 543 544 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 545 int where) 546 { 547 return NULL; 548 } 549 #endif 550 551 #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) 552 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); 553 void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); 554 #else 555 static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 556 { 557 return 0; 558 } 559 560 static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) 561 { 562 } 563 #endif 564 565 u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); 566 u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); 567 568 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); 569 570 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, 571 u32 r, bool is_io, 572 u64 cpu_addr, u64 pci_addr, size_t size); 573 574 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, 575 u8 busnr, u8 fn, 576 u32 r, u64 cpu_addr); 577 578 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); 579 void cdns_pcie_disable_phy(struct cdns_pcie *pcie); 580 int cdns_pcie_enable_phy(struct cdns_pcie *pcie); 581 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); 582 extern const struct dev_pm_ops cdns_pcie_pm_ops; 583 584 #endif /* _PCIE_CADENCE_H */ 585