1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017 Cadence 3 // Cadence PCIe endpoint controller driver. 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 6 #include <linux/delay.h> 7 #include <linux/kernel.h> 8 #include <linux/of.h> 9 #include <linux/pci-epc.h> 10 #include <linux/platform_device.h> 11 #include <linux/sizes.h> 12 13 #include "pcie-cadence.h" 14 15 #define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ 16 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 17 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 18 19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) 20 { 21 u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; 22 u32 first_vf_offset, stride; 23 24 if (vfn == 0) 25 return fn; 26 27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); 28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); 29 fn = fn + first_vf_offset + ((vfn - 1) * stride); 30 31 return fn; 32 } 33 34 static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, 35 struct pci_epf_header *hdr) 36 { 37 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 38 u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; 39 struct cdns_pcie *pcie = &ep->pcie; 40 u32 reg; 41 42 if (vfn > 1) { 43 dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); 44 return -EINVAL; 45 } else if (vfn == 1) { 46 reg = cap + PCI_SRIOV_VF_DID; 47 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); 48 return 0; 49 } 50 51 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); 52 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); 53 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); 54 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, 55 hdr->subclass_code | hdr->baseclass_code << 8); 56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, 57 hdr->cache_line_size); 58 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); 59 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); 60 61 /* 62 * Vendor ID can only be modified from function 0, all other functions 63 * use the same vendor ID as function 0. 64 */ 65 if (fn == 0) { 66 /* Update the vendor IDs. */ 67 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | 68 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); 69 70 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); 71 } 72 73 return 0; 74 } 75 76 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, 77 struct pci_epf_bar *epf_bar) 78 { 79 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 80 struct cdns_pcie_epf *epf = &ep->epf[fn]; 81 struct cdns_pcie *pcie = &ep->pcie; 82 dma_addr_t bar_phys = epf_bar->phys_addr; 83 enum pci_barno bar = epf_bar->barno; 84 int flags = epf_bar->flags; 85 u32 addr0, addr1, reg, cfg, b, aperture, ctrl; 86 u64 sz; 87 88 /* BAR size is 2^(aperture + 7) */ 89 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); 90 /* 91 * roundup_pow_of_two() returns an unsigned long, which is not suited 92 * for 64bit values. 93 */ 94 sz = 1ULL << fls64(sz - 1); 95 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ 96 97 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 98 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS; 99 } else { 100 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); 101 bool is_64bits = sz > SZ_2G; 102 103 if (is_64bits && (bar & 1)) 104 return -EINVAL; 105 106 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) 107 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; 108 109 if (is_64bits && is_prefetch) 110 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; 111 else if (is_prefetch) 112 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; 113 else if (is_64bits) 114 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS; 115 else 116 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS; 117 } 118 119 addr0 = lower_32_bits(bar_phys); 120 addr1 = upper_32_bits(bar_phys); 121 122 if (vfn == 1) 123 reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn); 124 else 125 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn); 126 b = (bar < BAR_4) ? bar : bar - BAR_4; 127 128 if (vfn == 0 || vfn == 1) { 129 cfg = cdns_pcie_readl(pcie, reg); 130 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | 131 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); 132 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | 133 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); 134 cdns_pcie_writel(pcie, reg, cfg); 135 } 136 137 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 138 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 139 addr0); 140 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 141 addr1); 142 143 if (vfn > 0) 144 epf = &epf->epf[vfn - 1]; 145 epf->epf_bar[bar] = epf_bar; 146 147 return 0; 148 } 149 150 static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, 151 struct pci_epf_bar *epf_bar) 152 { 153 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 154 struct cdns_pcie_epf *epf = &ep->epf[fn]; 155 struct cdns_pcie *pcie = &ep->pcie; 156 enum pci_barno bar = epf_bar->barno; 157 u32 reg, cfg, b, ctrl; 158 159 if (vfn == 1) 160 reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn); 161 else 162 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn); 163 b = (bar < BAR_4) ? bar : bar - BAR_4; 164 165 if (vfn == 0 || vfn == 1) { 166 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; 167 cfg = cdns_pcie_readl(pcie, reg); 168 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | 169 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); 170 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); 171 cdns_pcie_writel(pcie, reg, cfg); 172 } 173 174 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 175 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); 176 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); 177 178 if (vfn > 0) 179 epf = &epf->epf[vfn - 1]; 180 epf->epf_bar[bar] = NULL; 181 } 182 183 static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, 184 phys_addr_t addr, u64 pci_addr, size_t size) 185 { 186 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 187 struct cdns_pcie *pcie = &ep->pcie; 188 u32 r; 189 190 r = find_first_zero_bit(&ep->ob_region_map, 191 sizeof(ep->ob_region_map) * BITS_PER_LONG); 192 if (r >= ep->max_regions - 1) { 193 dev_err(&epc->dev, "no free outbound region\n"); 194 return -EINVAL; 195 } 196 197 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 198 cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size); 199 200 set_bit(r, &ep->ob_region_map); 201 ep->ob_addr[r] = addr; 202 203 return 0; 204 } 205 206 static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, 207 phys_addr_t addr) 208 { 209 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 210 struct cdns_pcie *pcie = &ep->pcie; 211 u32 r; 212 213 for (r = 0; r < ep->max_regions - 1; r++) 214 if (ep->ob_addr[r] == addr) 215 break; 216 217 if (r == ep->max_regions - 1) 218 return; 219 220 cdns_pcie_reset_outbound_region(pcie, r); 221 222 ep->ob_addr[r] = 0; 223 clear_bit(r, &ep->ob_region_map); 224 } 225 226 static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) 227 { 228 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 229 struct cdns_pcie *pcie = &ep->pcie; 230 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 231 u16 flags; 232 233 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 234 235 /* 236 * Set the Multiple Message Capable bitfield into the Message Control 237 * register. 238 */ 239 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 240 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); 241 flags |= PCI_MSI_FLAGS_64BIT; 242 flags &= ~PCI_MSI_FLAGS_MASKBIT; 243 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); 244 245 return 0; 246 } 247 248 static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) 249 { 250 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 251 struct cdns_pcie *pcie = &ep->pcie; 252 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 253 u16 flags, mme; 254 255 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 256 257 /* Validate that the MSI feature is actually enabled. */ 258 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 259 if (!(flags & PCI_MSI_FLAGS_ENABLE)) 260 return -EINVAL; 261 262 /* 263 * Get the Multiple Message Enable bitfield from the Message Control 264 * register. 265 */ 266 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 267 268 return mme; 269 } 270 271 static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) 272 { 273 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 274 struct cdns_pcie *pcie = &ep->pcie; 275 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 276 u32 val, reg; 277 278 func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); 279 280 reg = cap + PCI_MSIX_FLAGS; 281 val = cdns_pcie_ep_fn_readw(pcie, func_no, reg); 282 if (!(val & PCI_MSIX_FLAGS_ENABLE)) 283 return -EINVAL; 284 285 val &= PCI_MSIX_FLAGS_QSIZE; 286 287 return val; 288 } 289 290 static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, 291 u16 interrupts, enum pci_barno bir, 292 u32 offset) 293 { 294 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 295 struct cdns_pcie *pcie = &ep->pcie; 296 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 297 u32 val, reg; 298 299 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 300 301 reg = cap + PCI_MSIX_FLAGS; 302 val = cdns_pcie_ep_fn_readw(pcie, fn, reg); 303 val &= ~PCI_MSIX_FLAGS_QSIZE; 304 val |= interrupts; 305 cdns_pcie_ep_fn_writew(pcie, fn, reg, val); 306 307 /* Set MSIX BAR and offset */ 308 reg = cap + PCI_MSIX_TABLE; 309 val = offset | bir; 310 cdns_pcie_ep_fn_writel(pcie, fn, reg, val); 311 312 /* Set PBA BAR and offset. BAR must match MSIX BAR */ 313 reg = cap + PCI_MSIX_PBA; 314 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; 315 cdns_pcie_ep_fn_writel(pcie, fn, reg, val); 316 317 return 0; 318 } 319 320 static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, 321 bool is_asserted) 322 { 323 struct cdns_pcie *pcie = &ep->pcie; 324 unsigned long flags; 325 u32 offset; 326 u16 status; 327 u8 msg_code; 328 329 intx &= 3; 330 331 /* Set the outbound region if needed. */ 332 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || 333 ep->irq_pci_fn != fn)) { 334 /* First region was reserved for IRQ writes. */ 335 cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, 336 ep->irq_phys_addr); 337 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; 338 ep->irq_pci_fn = fn; 339 } 340 341 if (is_asserted) { 342 ep->irq_pending |= BIT(intx); 343 msg_code = MSG_CODE_ASSERT_INTA + intx; 344 } else { 345 ep->irq_pending &= ~BIT(intx); 346 msg_code = MSG_CODE_DEASSERT_INTA + intx; 347 } 348 349 spin_lock_irqsave(&ep->lock, flags); 350 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); 351 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { 352 status ^= PCI_STATUS_INTERRUPT; 353 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); 354 } 355 spin_unlock_irqrestore(&ep->lock, flags); 356 357 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | 358 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | 359 CDNS_PCIE_MSG_NO_DATA; 360 writel(0, ep->irq_cpu_addr + offset); 361 } 362 363 static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 364 u8 intx) 365 { 366 u16 cmd; 367 368 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); 369 if (cmd & PCI_COMMAND_INTX_DISABLE) 370 return -EINVAL; 371 372 cdns_pcie_ep_assert_intx(ep, fn, intx, true); 373 /* 374 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq() 375 */ 376 mdelay(1); 377 cdns_pcie_ep_assert_intx(ep, fn, intx, false); 378 return 0; 379 } 380 381 static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 382 u8 interrupt_num) 383 { 384 struct cdns_pcie *pcie = &ep->pcie; 385 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 386 u16 flags, mme, data, data_mask; 387 u8 msi_count; 388 u64 pci_addr, pci_addr_mask = 0xff; 389 390 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 391 392 /* Check whether the MSI feature has been enabled by the PCI host. */ 393 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 394 if (!(flags & PCI_MSI_FLAGS_ENABLE)) 395 return -EINVAL; 396 397 /* Get the number of enabled MSIs */ 398 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 399 msi_count = 1 << mme; 400 if (!interrupt_num || interrupt_num > msi_count) 401 return -EINVAL; 402 403 /* Compute the data value to be written. */ 404 data_mask = msi_count - 1; 405 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); 406 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); 407 408 /* Get the PCI address where to write the data into. */ 409 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); 410 pci_addr <<= 32; 411 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); 412 pci_addr &= GENMASK_ULL(63, 2); 413 414 /* Set the outbound region if needed. */ 415 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || 416 ep->irq_pci_fn != fn)) { 417 /* First region was reserved for IRQ writes. */ 418 cdns_pcie_set_outbound_region(pcie, 0, fn, 0, 419 false, 420 ep->irq_phys_addr, 421 pci_addr & ~pci_addr_mask, 422 pci_addr_mask + 1); 423 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); 424 ep->irq_pci_fn = fn; 425 } 426 writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); 427 428 return 0; 429 } 430 431 static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, 432 phys_addr_t addr, u8 interrupt_num, 433 u32 entry_size, u32 *msi_data, 434 u32 *msi_addr_offset) 435 { 436 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 437 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 438 struct cdns_pcie *pcie = &ep->pcie; 439 u64 pci_addr, pci_addr_mask = 0xff; 440 u16 flags, mme, data, data_mask; 441 u8 msi_count; 442 int ret; 443 int i; 444 445 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 446 447 /* Check whether the MSI feature has been enabled by the PCI host. */ 448 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 449 if (!(flags & PCI_MSI_FLAGS_ENABLE)) 450 return -EINVAL; 451 452 /* Get the number of enabled MSIs */ 453 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 454 msi_count = 1 << mme; 455 if (!interrupt_num || interrupt_num > msi_count) 456 return -EINVAL; 457 458 /* Compute the data value to be written. */ 459 data_mask = msi_count - 1; 460 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); 461 data = data & ~data_mask; 462 463 /* Get the PCI address where to write the data into. */ 464 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); 465 pci_addr <<= 32; 466 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); 467 pci_addr &= GENMASK_ULL(63, 2); 468 469 for (i = 0; i < interrupt_num; i++) { 470 ret = cdns_pcie_ep_map_addr(epc, fn, vfn, addr, 471 pci_addr & ~pci_addr_mask, 472 entry_size); 473 if (ret) 474 return ret; 475 addr = addr + entry_size; 476 } 477 478 *msi_data = data; 479 *msi_addr_offset = pci_addr & pci_addr_mask; 480 481 return 0; 482 } 483 484 static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 485 u16 interrupt_num) 486 { 487 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 488 u32 tbl_offset, msg_data, reg; 489 struct cdns_pcie *pcie = &ep->pcie; 490 struct pci_epf_msix_tbl *msix_tbl; 491 struct cdns_pcie_epf *epf; 492 u64 pci_addr_mask = 0xff; 493 u64 msg_addr; 494 u16 flags; 495 u8 bir; 496 497 epf = &ep->epf[fn]; 498 if (vfn > 0) 499 epf = &epf->epf[vfn - 1]; 500 501 fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); 502 503 /* Check whether the MSI-X feature has been enabled by the PCI host. */ 504 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); 505 if (!(flags & PCI_MSIX_FLAGS_ENABLE)) 506 return -EINVAL; 507 508 reg = cap + PCI_MSIX_TABLE; 509 tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); 510 bir = tbl_offset & PCI_MSIX_TABLE_BIR; 511 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 512 513 msix_tbl = epf->epf_bar[bir]->addr + tbl_offset; 514 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; 515 msg_data = msix_tbl[(interrupt_num - 1)].msg_data; 516 517 /* Set the outbound region if needed. */ 518 if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) || 519 ep->irq_pci_fn != fn) { 520 /* First region was reserved for IRQ writes. */ 521 cdns_pcie_set_outbound_region(pcie, 0, fn, 0, 522 false, 523 ep->irq_phys_addr, 524 msg_addr & ~pci_addr_mask, 525 pci_addr_mask + 1); 526 ep->irq_pci_addr = (msg_addr & ~pci_addr_mask); 527 ep->irq_pci_fn = fn; 528 } 529 writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); 530 531 return 0; 532 } 533 534 static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, 535 enum pci_epc_irq_type type, 536 u16 interrupt_num) 537 { 538 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 539 struct cdns_pcie *pcie = &ep->pcie; 540 struct device *dev = pcie->dev; 541 542 switch (type) { 543 case PCI_EPC_IRQ_LEGACY: 544 if (vfn > 0) { 545 dev_err(dev, "Cannot raise legacy interrupts for VF\n"); 546 return -EINVAL; 547 } 548 return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0); 549 550 case PCI_EPC_IRQ_MSI: 551 return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num); 552 553 case PCI_EPC_IRQ_MSIX: 554 return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num); 555 556 default: 557 break; 558 } 559 560 return -EINVAL; 561 } 562 563 static int cdns_pcie_ep_start(struct pci_epc *epc) 564 { 565 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 566 struct cdns_pcie *pcie = &ep->pcie; 567 struct device *dev = pcie->dev; 568 int ret; 569 570 /* 571 * BIT(0) is hardwired to 1, hence function 0 is always enabled 572 * and can't be disabled anyway. 573 */ 574 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); 575 576 ret = cdns_pcie_start_link(pcie); 577 if (ret) { 578 dev_err(dev, "Failed to start link\n"); 579 return ret; 580 } 581 582 return 0; 583 } 584 585 static const struct pci_epc_features cdns_pcie_epc_vf_features = { 586 .linkup_notifier = false, 587 .msi_capable = true, 588 .msix_capable = true, 589 .align = 65536, 590 }; 591 592 static const struct pci_epc_features cdns_pcie_epc_features = { 593 .linkup_notifier = false, 594 .msi_capable = true, 595 .msix_capable = true, 596 .align = 256, 597 }; 598 599 static const struct pci_epc_features* 600 cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) 601 { 602 if (!vfunc_no) 603 return &cdns_pcie_epc_features; 604 605 return &cdns_pcie_epc_vf_features; 606 } 607 608 static const struct pci_epc_ops cdns_pcie_epc_ops = { 609 .write_header = cdns_pcie_ep_write_header, 610 .set_bar = cdns_pcie_ep_set_bar, 611 .clear_bar = cdns_pcie_ep_clear_bar, 612 .map_addr = cdns_pcie_ep_map_addr, 613 .unmap_addr = cdns_pcie_ep_unmap_addr, 614 .set_msi = cdns_pcie_ep_set_msi, 615 .get_msi = cdns_pcie_ep_get_msi, 616 .set_msix = cdns_pcie_ep_set_msix, 617 .get_msix = cdns_pcie_ep_get_msix, 618 .raise_irq = cdns_pcie_ep_raise_irq, 619 .map_msi_irq = cdns_pcie_ep_map_msi_irq, 620 .start = cdns_pcie_ep_start, 621 .get_features = cdns_pcie_ep_get_features, 622 }; 623 624 625 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 626 { 627 struct device *dev = ep->pcie.dev; 628 struct platform_device *pdev = to_platform_device(dev); 629 struct device_node *np = dev->of_node; 630 struct cdns_pcie *pcie = &ep->pcie; 631 struct cdns_pcie_epf *epf; 632 struct resource *res; 633 struct pci_epc *epc; 634 int ret; 635 int i; 636 637 pcie->is_rc = false; 638 639 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); 640 if (IS_ERR(pcie->reg_base)) { 641 dev_err(dev, "missing \"reg\"\n"); 642 return PTR_ERR(pcie->reg_base); 643 } 644 645 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); 646 if (!res) { 647 dev_err(dev, "missing \"mem\"\n"); 648 return -EINVAL; 649 } 650 pcie->mem_res = res; 651 652 ep->max_regions = CDNS_PCIE_MAX_OB; 653 of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); 654 655 ep->ob_addr = devm_kcalloc(dev, 656 ep->max_regions, sizeof(*ep->ob_addr), 657 GFP_KERNEL); 658 if (!ep->ob_addr) 659 return -ENOMEM; 660 661 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */ 662 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); 663 664 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops); 665 if (IS_ERR(epc)) { 666 dev_err(dev, "failed to create epc device\n"); 667 return PTR_ERR(epc); 668 } 669 670 epc_set_drvdata(epc, ep); 671 672 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) 673 epc->max_functions = 1; 674 675 ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), 676 GFP_KERNEL); 677 if (!ep->epf) 678 return -ENOMEM; 679 680 epc->max_vfs = devm_kcalloc(dev, epc->max_functions, 681 sizeof(*epc->max_vfs), GFP_KERNEL); 682 if (!epc->max_vfs) 683 return -ENOMEM; 684 685 ret = of_property_read_u8_array(np, "max-virtual-functions", 686 epc->max_vfs, epc->max_functions); 687 if (ret == 0) { 688 for (i = 0; i < epc->max_functions; i++) { 689 epf = &ep->epf[i]; 690 if (epc->max_vfs[i] == 0) 691 continue; 692 epf->epf = devm_kcalloc(dev, epc->max_vfs[i], 693 sizeof(*ep->epf), GFP_KERNEL); 694 if (!epf->epf) 695 return -ENOMEM; 696 } 697 } 698 699 ret = pci_epc_mem_init(epc, pcie->mem_res->start, 700 resource_size(pcie->mem_res), PAGE_SIZE); 701 if (ret < 0) { 702 dev_err(dev, "failed to initialize the memory space\n"); 703 return ret; 704 } 705 706 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, 707 SZ_128K); 708 if (!ep->irq_cpu_addr) { 709 dev_err(dev, "failed to reserve memory space for MSI\n"); 710 ret = -ENOMEM; 711 goto free_epc_mem; 712 } 713 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; 714 /* Reserve region 0 for IRQs */ 715 set_bit(0, &ep->ob_region_map); 716 717 if (ep->quirk_detect_quiet_flag) 718 cdns_pcie_detect_quiet_min_delay_set(&ep->pcie); 719 720 spin_lock_init(&ep->lock); 721 722 return 0; 723 724 free_epc_mem: 725 pci_epc_mem_exit(epc); 726 727 return ret; 728 } 729