1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pci.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 23 #include "../../pci.h" 24 #include "pcie-cadence.h" 25 26 #define ENABLE_REG_SYS_2 0x108 27 #define STATUS_REG_SYS_2 0x508 28 #define STATUS_CLR_REG_SYS_2 0x708 29 #define LINK_DOWN BIT(1) 30 31 #define J721E_PCIE_USER_CMD_STATUS 0x4 32 #define LINK_TRAINING_ENABLE BIT(0) 33 34 #define J721E_PCIE_USER_LINKSTATUS 0x14 35 #define LINK_STATUS GENMASK(1, 0) 36 37 enum link_status { 38 NO_RECEIVERS_DETECTED, 39 LINK_TRAINING_IN_PROGRESS, 40 LINK_UP_DL_IN_PROGRESS, 41 LINK_UP_DL_COMPLETED, 42 }; 43 44 #define J721E_MODE_RC BIT(7) 45 #define LANE_COUNT_MASK BIT(8) 46 #define LANE_COUNT(n) ((n) << 8) 47 48 #define GENERATION_SEL_MASK GENMASK(1, 0) 49 50 #define MAX_LANES 2 51 52 struct j721e_pcie { 53 struct device *dev; 54 struct clk *refclk; 55 u32 mode; 56 u32 num_lanes; 57 struct cdns_pcie *cdns_pcie; 58 void __iomem *user_cfg_base; 59 void __iomem *intd_cfg_base; 60 }; 61 62 enum j721e_pcie_mode { 63 PCI_MODE_RC, 64 PCI_MODE_EP, 65 }; 66 67 struct j721e_pcie_data { 68 enum j721e_pcie_mode mode; 69 bool quirk_retrain_flag; 70 }; 71 72 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 73 { 74 return readl(pcie->user_cfg_base + offset); 75 } 76 77 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 78 u32 value) 79 { 80 writel(value, pcie->user_cfg_base + offset); 81 } 82 83 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 84 { 85 return readl(pcie->intd_cfg_base + offset); 86 } 87 88 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 89 u32 value) 90 { 91 writel(value, pcie->intd_cfg_base + offset); 92 } 93 94 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 95 { 96 struct j721e_pcie *pcie = priv; 97 struct device *dev = pcie->dev; 98 u32 reg; 99 100 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 101 if (!(reg & LINK_DOWN)) 102 return IRQ_NONE; 103 104 dev_err(dev, "LINK DOWN!\n"); 105 106 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN); 107 return IRQ_HANDLED; 108 } 109 110 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 111 { 112 u32 reg; 113 114 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 115 reg |= LINK_DOWN; 116 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 117 } 118 119 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 120 { 121 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 122 u32 reg; 123 124 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 125 reg |= LINK_TRAINING_ENABLE; 126 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 127 128 return 0; 129 } 130 131 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 132 { 133 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 134 u32 reg; 135 136 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 137 reg &= ~LINK_TRAINING_ENABLE; 138 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 139 } 140 141 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 142 { 143 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 144 u32 reg; 145 146 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 147 reg &= LINK_STATUS; 148 if (reg == LINK_UP_DL_COMPLETED) 149 return true; 150 151 return false; 152 } 153 154 static const struct cdns_pcie_ops j721e_pcie_ops = { 155 .start_link = j721e_pcie_start_link, 156 .stop_link = j721e_pcie_stop_link, 157 .link_up = j721e_pcie_link_up, 158 }; 159 160 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 161 unsigned int offset) 162 { 163 struct device *dev = pcie->dev; 164 u32 mask = J721E_MODE_RC; 165 u32 mode = pcie->mode; 166 u32 val = 0; 167 int ret = 0; 168 169 if (mode == PCI_MODE_RC) 170 val = J721E_MODE_RC; 171 172 ret = regmap_update_bits(syscon, offset, mask, val); 173 if (ret) 174 dev_err(dev, "failed to set pcie mode\n"); 175 176 return ret; 177 } 178 179 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 180 struct regmap *syscon, unsigned int offset) 181 { 182 struct device *dev = pcie->dev; 183 struct device_node *np = dev->of_node; 184 int link_speed; 185 u32 val = 0; 186 int ret; 187 188 link_speed = of_pci_get_max_link_speed(np); 189 if (link_speed < 2) 190 link_speed = 2; 191 192 val = link_speed - 1; 193 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 194 if (ret) 195 dev_err(dev, "failed to set link speed\n"); 196 197 return ret; 198 } 199 200 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 201 struct regmap *syscon, unsigned int offset) 202 { 203 struct device *dev = pcie->dev; 204 u32 lanes = pcie->num_lanes; 205 u32 val = 0; 206 int ret; 207 208 val = LANE_COUNT(lanes - 1); 209 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); 210 if (ret) 211 dev_err(dev, "failed to set link count\n"); 212 213 return ret; 214 } 215 216 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 217 { 218 struct device *dev = pcie->dev; 219 struct device_node *node = dev->of_node; 220 struct of_phandle_args args; 221 unsigned int offset = 0; 222 struct regmap *syscon; 223 int ret; 224 225 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 226 if (IS_ERR(syscon)) { 227 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 228 return PTR_ERR(syscon); 229 } 230 231 /* Do not error out to maintain old DT compatibility */ 232 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 233 0, &args); 234 if (!ret) 235 offset = args.args[0]; 236 237 ret = j721e_pcie_set_mode(pcie, syscon, offset); 238 if (ret < 0) { 239 dev_err(dev, "Failed to set pci mode\n"); 240 return ret; 241 } 242 243 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 244 if (ret < 0) { 245 dev_err(dev, "Failed to set link speed\n"); 246 return ret; 247 } 248 249 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 250 if (ret < 0) { 251 dev_err(dev, "Failed to set num-lanes\n"); 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 259 int where, int size, u32 *value) 260 { 261 if (pci_is_root_bus(bus)) 262 return pci_generic_config_read32(bus, devfn, where, size, 263 value); 264 265 return pci_generic_config_read(bus, devfn, where, size, value); 266 } 267 268 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 269 int where, int size, u32 value) 270 { 271 if (pci_is_root_bus(bus)) 272 return pci_generic_config_write32(bus, devfn, where, size, 273 value); 274 275 return pci_generic_config_write(bus, devfn, where, size, value); 276 } 277 278 static struct pci_ops cdns_ti_pcie_host_ops = { 279 .map_bus = cdns_pci_map_bus, 280 .read = cdns_ti_pcie_config_read, 281 .write = cdns_ti_pcie_config_write, 282 }; 283 284 static const struct j721e_pcie_data j721e_pcie_rc_data = { 285 .mode = PCI_MODE_RC, 286 .quirk_retrain_flag = true, 287 }; 288 289 static const struct j721e_pcie_data j721e_pcie_ep_data = { 290 .mode = PCI_MODE_EP, 291 }; 292 293 static const struct of_device_id of_j721e_pcie_match[] = { 294 { 295 .compatible = "ti,j721e-pcie-host", 296 .data = &j721e_pcie_rc_data, 297 }, 298 { 299 .compatible = "ti,j721e-pcie-ep", 300 .data = &j721e_pcie_ep_data, 301 }, 302 {}, 303 }; 304 305 static int j721e_pcie_probe(struct platform_device *pdev) 306 { 307 struct device *dev = &pdev->dev; 308 struct device_node *node = dev->of_node; 309 struct pci_host_bridge *bridge; 310 struct j721e_pcie_data *data; 311 struct cdns_pcie *cdns_pcie; 312 struct j721e_pcie *pcie; 313 struct cdns_pcie_rc *rc; 314 struct cdns_pcie_ep *ep; 315 struct gpio_desc *gpiod; 316 void __iomem *base; 317 struct clk *clk; 318 u32 num_lanes; 319 u32 mode; 320 int ret; 321 int irq; 322 323 data = (struct j721e_pcie_data *)of_device_get_match_data(dev); 324 if (!data) 325 return -EINVAL; 326 327 mode = (u32)data->mode; 328 329 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 330 if (!pcie) 331 return -ENOMEM; 332 333 pcie->dev = dev; 334 pcie->mode = mode; 335 336 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 337 if (IS_ERR(base)) 338 return PTR_ERR(base); 339 pcie->intd_cfg_base = base; 340 341 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 342 if (IS_ERR(base)) 343 return PTR_ERR(base); 344 pcie->user_cfg_base = base; 345 346 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 347 if (ret || num_lanes > MAX_LANES) 348 num_lanes = 1; 349 pcie->num_lanes = num_lanes; 350 351 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 352 return -EINVAL; 353 354 irq = platform_get_irq_byname(pdev, "link_state"); 355 if (irq < 0) 356 return irq; 357 358 dev_set_drvdata(dev, pcie); 359 pm_runtime_enable(dev); 360 ret = pm_runtime_get_sync(dev); 361 if (ret < 0) { 362 dev_err(dev, "pm_runtime_get_sync failed\n"); 363 goto err_get_sync; 364 } 365 366 ret = j721e_pcie_ctrl_init(pcie); 367 if (ret < 0) { 368 dev_err(dev, "pm_runtime_get_sync failed\n"); 369 goto err_get_sync; 370 } 371 372 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 373 "j721e-pcie-link-down-irq", pcie); 374 if (ret < 0) { 375 dev_err(dev, "failed to request link state IRQ %d\n", irq); 376 goto err_get_sync; 377 } 378 379 j721e_pcie_config_link_irq(pcie); 380 381 switch (mode) { 382 case PCI_MODE_RC: 383 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { 384 ret = -ENODEV; 385 goto err_get_sync; 386 } 387 388 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 389 if (!bridge) { 390 ret = -ENOMEM; 391 goto err_get_sync; 392 } 393 394 bridge->ops = &cdns_ti_pcie_host_ops; 395 rc = pci_host_bridge_priv(bridge); 396 rc->quirk_retrain_flag = data->quirk_retrain_flag; 397 398 cdns_pcie = &rc->pcie; 399 cdns_pcie->dev = dev; 400 cdns_pcie->ops = &j721e_pcie_ops; 401 pcie->cdns_pcie = cdns_pcie; 402 403 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 404 if (IS_ERR(gpiod)) { 405 ret = PTR_ERR(gpiod); 406 if (ret != -EPROBE_DEFER) 407 dev_err(dev, "Failed to get reset GPIO\n"); 408 goto err_get_sync; 409 } 410 411 ret = cdns_pcie_init_phy(dev, cdns_pcie); 412 if (ret) { 413 dev_err(dev, "Failed to init phy\n"); 414 goto err_get_sync; 415 } 416 417 clk = devm_clk_get_optional(dev, "pcie_refclk"); 418 if (IS_ERR(clk)) { 419 ret = PTR_ERR(clk); 420 dev_err(dev, "failed to get pcie_refclk\n"); 421 goto err_pcie_setup; 422 } 423 424 ret = clk_prepare_enable(clk); 425 if (ret) { 426 dev_err(dev, "failed to enable pcie_refclk\n"); 427 goto err_get_sync; 428 } 429 pcie->refclk = clk; 430 431 /* 432 * "Power Sequencing and Reset Signal Timings" table in 433 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 434 * indicates PERST# should be deasserted after minimum of 100us 435 * once REFCLK is stable. The REFCLK to the connector in RC 436 * mode is selected while enabling the PHY. So deassert PERST# 437 * after 100 us. 438 */ 439 if (gpiod) { 440 usleep_range(100, 200); 441 gpiod_set_value_cansleep(gpiod, 1); 442 } 443 444 ret = cdns_pcie_host_setup(rc); 445 if (ret < 0) { 446 clk_disable_unprepare(pcie->refclk); 447 goto err_pcie_setup; 448 } 449 450 break; 451 case PCI_MODE_EP: 452 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { 453 ret = -ENODEV; 454 goto err_get_sync; 455 } 456 457 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 458 if (!ep) { 459 ret = -ENOMEM; 460 goto err_get_sync; 461 } 462 463 cdns_pcie = &ep->pcie; 464 cdns_pcie->dev = dev; 465 cdns_pcie->ops = &j721e_pcie_ops; 466 pcie->cdns_pcie = cdns_pcie; 467 468 ret = cdns_pcie_init_phy(dev, cdns_pcie); 469 if (ret) { 470 dev_err(dev, "Failed to init phy\n"); 471 goto err_get_sync; 472 } 473 474 ret = cdns_pcie_ep_setup(ep); 475 if (ret < 0) 476 goto err_pcie_setup; 477 478 break; 479 default: 480 dev_err(dev, "INVALID device type %d\n", mode); 481 } 482 483 return 0; 484 485 err_pcie_setup: 486 cdns_pcie_disable_phy(cdns_pcie); 487 488 err_get_sync: 489 pm_runtime_put(dev); 490 pm_runtime_disable(dev); 491 492 return ret; 493 } 494 495 static int j721e_pcie_remove(struct platform_device *pdev) 496 { 497 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 498 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 499 struct device *dev = &pdev->dev; 500 501 clk_disable_unprepare(pcie->refclk); 502 cdns_pcie_disable_phy(cdns_pcie); 503 pm_runtime_put(dev); 504 pm_runtime_disable(dev); 505 506 return 0; 507 } 508 509 static struct platform_driver j721e_pcie_driver = { 510 .probe = j721e_pcie_probe, 511 .remove = j721e_pcie_remove, 512 .driver = { 513 .name = "j721e-pcie", 514 .of_match_table = of_j721e_pcie_match, 515 .suppress_bind_attrs = true, 516 }, 517 }; 518 builtin_platform_driver(j721e_pcie_driver); 519