xref: /linux/drivers/pci/controller/cadence/pci-j721e.c (revision a1c3be890440a1769ed6f822376a3e3ab0d42994)
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3  * pci-j721e - PCIe controller driver for TI's J721E SoCs
4  *
5  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/io.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pci.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 
22 #include "../../pci.h"
23 #include "pcie-cadence.h"
24 
25 #define ENABLE_REG_SYS_2	0x108
26 #define STATUS_REG_SYS_2	0x508
27 #define STATUS_CLR_REG_SYS_2	0x708
28 #define LINK_DOWN		BIT(1)
29 
30 #define J721E_PCIE_USER_CMD_STATUS	0x4
31 #define LINK_TRAINING_ENABLE		BIT(0)
32 
33 #define J721E_PCIE_USER_LINKSTATUS	0x14
34 #define LINK_STATUS			GENMASK(1, 0)
35 
36 enum link_status {
37 	NO_RECEIVERS_DETECTED,
38 	LINK_TRAINING_IN_PROGRESS,
39 	LINK_UP_DL_IN_PROGRESS,
40 	LINK_UP_DL_COMPLETED,
41 };
42 
43 #define J721E_MODE_RC			BIT(7)
44 #define LANE_COUNT_MASK			BIT(8)
45 #define LANE_COUNT(n)			((n) << 8)
46 
47 #define GENERATION_SEL_MASK		GENMASK(1, 0)
48 
49 #define MAX_LANES			2
50 
51 struct j721e_pcie {
52 	struct device		*dev;
53 	u32			mode;
54 	u32			num_lanes;
55 	struct cdns_pcie	*cdns_pcie;
56 	void __iomem		*user_cfg_base;
57 	void __iomem		*intd_cfg_base;
58 };
59 
60 enum j721e_pcie_mode {
61 	PCI_MODE_RC,
62 	PCI_MODE_EP,
63 };
64 
65 struct j721e_pcie_data {
66 	enum j721e_pcie_mode	mode;
67 	bool quirk_retrain_flag;
68 };
69 
70 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
71 {
72 	return readl(pcie->user_cfg_base + offset);
73 }
74 
75 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
76 					  u32 value)
77 {
78 	writel(value, pcie->user_cfg_base + offset);
79 }
80 
81 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
82 {
83 	return readl(pcie->intd_cfg_base + offset);
84 }
85 
86 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
87 					  u32 value)
88 {
89 	writel(value, pcie->intd_cfg_base + offset);
90 }
91 
92 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
93 {
94 	struct j721e_pcie *pcie = priv;
95 	struct device *dev = pcie->dev;
96 	u32 reg;
97 
98 	reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
99 	if (!(reg & LINK_DOWN))
100 		return IRQ_NONE;
101 
102 	dev_err(dev, "LINK DOWN!\n");
103 
104 	j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN);
105 	return IRQ_HANDLED;
106 }
107 
108 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
109 {
110 	u32 reg;
111 
112 	reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
113 	reg |= LINK_DOWN;
114 	j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
115 }
116 
117 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
118 {
119 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
120 	u32 reg;
121 
122 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
123 	reg |= LINK_TRAINING_ENABLE;
124 	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
125 
126 	return 0;
127 }
128 
129 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
130 {
131 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
132 	u32 reg;
133 
134 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
135 	reg &= ~LINK_TRAINING_ENABLE;
136 	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
137 }
138 
139 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
140 {
141 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
142 	u32 reg;
143 
144 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
145 	reg &= LINK_STATUS;
146 	if (reg == LINK_UP_DL_COMPLETED)
147 		return true;
148 
149 	return false;
150 }
151 
152 static const struct cdns_pcie_ops j721e_pcie_ops = {
153 	.start_link = j721e_pcie_start_link,
154 	.stop_link = j721e_pcie_stop_link,
155 	.link_up = j721e_pcie_link_up,
156 };
157 
158 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
159 			       unsigned int offset)
160 {
161 	struct device *dev = pcie->dev;
162 	u32 mask = J721E_MODE_RC;
163 	u32 mode = pcie->mode;
164 	u32 val = 0;
165 	int ret = 0;
166 
167 	if (mode == PCI_MODE_RC)
168 		val = J721E_MODE_RC;
169 
170 	ret = regmap_update_bits(syscon, offset, mask, val);
171 	if (ret)
172 		dev_err(dev, "failed to set pcie mode\n");
173 
174 	return ret;
175 }
176 
177 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
178 				     struct regmap *syscon, unsigned int offset)
179 {
180 	struct device *dev = pcie->dev;
181 	struct device_node *np = dev->of_node;
182 	int link_speed;
183 	u32 val = 0;
184 	int ret;
185 
186 	link_speed = of_pci_get_max_link_speed(np);
187 	if (link_speed < 2)
188 		link_speed = 2;
189 
190 	val = link_speed - 1;
191 	ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
192 	if (ret)
193 		dev_err(dev, "failed to set link speed\n");
194 
195 	return ret;
196 }
197 
198 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
199 				     struct regmap *syscon, unsigned int offset)
200 {
201 	struct device *dev = pcie->dev;
202 	u32 lanes = pcie->num_lanes;
203 	u32 val = 0;
204 	int ret;
205 
206 	val = LANE_COUNT(lanes - 1);
207 	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
208 	if (ret)
209 		dev_err(dev, "failed to set link count\n");
210 
211 	return ret;
212 }
213 
214 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
215 {
216 	struct device *dev = pcie->dev;
217 	struct device_node *node = dev->of_node;
218 	struct of_phandle_args args;
219 	unsigned int offset = 0;
220 	struct regmap *syscon;
221 	int ret;
222 
223 	syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
224 	if (IS_ERR(syscon)) {
225 		dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
226 		return PTR_ERR(syscon);
227 	}
228 
229 	/* Do not error out to maintain old DT compatibility */
230 	ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
231 					       0, &args);
232 	if (!ret)
233 		offset = args.args[0];
234 
235 	ret = j721e_pcie_set_mode(pcie, syscon, offset);
236 	if (ret < 0) {
237 		dev_err(dev, "Failed to set pci mode\n");
238 		return ret;
239 	}
240 
241 	ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
242 	if (ret < 0) {
243 		dev_err(dev, "Failed to set link speed\n");
244 		return ret;
245 	}
246 
247 	ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
248 	if (ret < 0) {
249 		dev_err(dev, "Failed to set num-lanes\n");
250 		return ret;
251 	}
252 
253 	return 0;
254 }
255 
256 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
257 				    int where, int size, u32 *value)
258 {
259 	if (pci_is_root_bus(bus))
260 		return pci_generic_config_read32(bus, devfn, where, size,
261 						 value);
262 
263 	return pci_generic_config_read(bus, devfn, where, size, value);
264 }
265 
266 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
267 				     int where, int size, u32 value)
268 {
269 	if (pci_is_root_bus(bus))
270 		return pci_generic_config_write32(bus, devfn, where, size,
271 						  value);
272 
273 	return pci_generic_config_write(bus, devfn, where, size, value);
274 }
275 
276 static struct pci_ops cdns_ti_pcie_host_ops = {
277 	.map_bus	= cdns_pci_map_bus,
278 	.read		= cdns_ti_pcie_config_read,
279 	.write		= cdns_ti_pcie_config_write,
280 };
281 
282 static const struct j721e_pcie_data j721e_pcie_rc_data = {
283 	.mode = PCI_MODE_RC,
284 	.quirk_retrain_flag = true,
285 };
286 
287 static const struct j721e_pcie_data j721e_pcie_ep_data = {
288 	.mode = PCI_MODE_EP,
289 };
290 
291 static const struct of_device_id of_j721e_pcie_match[] = {
292 	{
293 		.compatible = "ti,j721e-pcie-host",
294 		.data = &j721e_pcie_rc_data,
295 	},
296 	{
297 		.compatible = "ti,j721e-pcie-ep",
298 		.data = &j721e_pcie_ep_data,
299 	},
300 	{},
301 };
302 
303 static int j721e_pcie_probe(struct platform_device *pdev)
304 {
305 	struct device *dev = &pdev->dev;
306 	struct device_node *node = dev->of_node;
307 	struct pci_host_bridge *bridge;
308 	struct j721e_pcie_data *data;
309 	struct cdns_pcie *cdns_pcie;
310 	struct j721e_pcie *pcie;
311 	struct cdns_pcie_rc *rc;
312 	struct cdns_pcie_ep *ep;
313 	struct gpio_desc *gpiod;
314 	void __iomem *base;
315 	u32 num_lanes;
316 	u32 mode;
317 	int ret;
318 	int irq;
319 
320 	data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
321 	if (!data)
322 		return -EINVAL;
323 
324 	mode = (u32)data->mode;
325 
326 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
327 	if (!pcie)
328 		return -ENOMEM;
329 
330 	pcie->dev = dev;
331 	pcie->mode = mode;
332 
333 	base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
334 	if (IS_ERR(base))
335 		return PTR_ERR(base);
336 	pcie->intd_cfg_base = base;
337 
338 	base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
339 	if (IS_ERR(base))
340 		return PTR_ERR(base);
341 	pcie->user_cfg_base = base;
342 
343 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
344 	if (ret || num_lanes > MAX_LANES)
345 		num_lanes = 1;
346 	pcie->num_lanes = num_lanes;
347 
348 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
349 		return -EINVAL;
350 
351 	irq = platform_get_irq_byname(pdev, "link_state");
352 	if (irq < 0)
353 		return irq;
354 
355 	dev_set_drvdata(dev, pcie);
356 	pm_runtime_enable(dev);
357 	ret = pm_runtime_get_sync(dev);
358 	if (ret < 0) {
359 		dev_err(dev, "pm_runtime_get_sync failed\n");
360 		goto err_get_sync;
361 	}
362 
363 	ret = j721e_pcie_ctrl_init(pcie);
364 	if (ret < 0) {
365 		dev_err(dev, "pm_runtime_get_sync failed\n");
366 		goto err_get_sync;
367 	}
368 
369 	ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
370 			       "j721e-pcie-link-down-irq", pcie);
371 	if (ret < 0) {
372 		dev_err(dev, "failed to request link state IRQ %d\n", irq);
373 		goto err_get_sync;
374 	}
375 
376 	j721e_pcie_config_link_irq(pcie);
377 
378 	switch (mode) {
379 	case PCI_MODE_RC:
380 		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
381 			ret = -ENODEV;
382 			goto err_get_sync;
383 		}
384 
385 		bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
386 		if (!bridge) {
387 			ret = -ENOMEM;
388 			goto err_get_sync;
389 		}
390 
391 		bridge->ops = &cdns_ti_pcie_host_ops;
392 		rc = pci_host_bridge_priv(bridge);
393 		rc->quirk_retrain_flag = data->quirk_retrain_flag;
394 
395 		cdns_pcie = &rc->pcie;
396 		cdns_pcie->dev = dev;
397 		cdns_pcie->ops = &j721e_pcie_ops;
398 		pcie->cdns_pcie = cdns_pcie;
399 
400 		gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
401 		if (IS_ERR(gpiod)) {
402 			ret = PTR_ERR(gpiod);
403 			if (ret != -EPROBE_DEFER)
404 				dev_err(dev, "Failed to get reset GPIO\n");
405 			goto err_get_sync;
406 		}
407 
408 		ret = cdns_pcie_init_phy(dev, cdns_pcie);
409 		if (ret) {
410 			dev_err(dev, "Failed to init phy\n");
411 			goto err_get_sync;
412 		}
413 
414 		/*
415 		 * "Power Sequencing and Reset Signal Timings" table in
416 		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
417 		 * indicates PERST# should be deasserted after minimum of 100us
418 		 * once REFCLK is stable. The REFCLK to the connector in RC
419 		 * mode is selected while enabling the PHY. So deassert PERST#
420 		 * after 100 us.
421 		 */
422 		if (gpiod) {
423 			usleep_range(100, 200);
424 			gpiod_set_value_cansleep(gpiod, 1);
425 		}
426 
427 		ret = cdns_pcie_host_setup(rc);
428 		if (ret < 0)
429 			goto err_pcie_setup;
430 
431 		break;
432 	case PCI_MODE_EP:
433 		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
434 			ret = -ENODEV;
435 			goto err_get_sync;
436 		}
437 
438 		ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
439 		if (!ep) {
440 			ret = -ENOMEM;
441 			goto err_get_sync;
442 		}
443 
444 		cdns_pcie = &ep->pcie;
445 		cdns_pcie->dev = dev;
446 		cdns_pcie->ops = &j721e_pcie_ops;
447 		pcie->cdns_pcie = cdns_pcie;
448 
449 		ret = cdns_pcie_init_phy(dev, cdns_pcie);
450 		if (ret) {
451 			dev_err(dev, "Failed to init phy\n");
452 			goto err_get_sync;
453 		}
454 
455 		ret = cdns_pcie_ep_setup(ep);
456 		if (ret < 0)
457 			goto err_pcie_setup;
458 
459 		break;
460 	default:
461 		dev_err(dev, "INVALID device type %d\n", mode);
462 	}
463 
464 	return 0;
465 
466 err_pcie_setup:
467 	cdns_pcie_disable_phy(cdns_pcie);
468 
469 err_get_sync:
470 	pm_runtime_put(dev);
471 	pm_runtime_disable(dev);
472 
473 	return ret;
474 }
475 
476 static int j721e_pcie_remove(struct platform_device *pdev)
477 {
478 	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
479 	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
480 	struct device *dev = &pdev->dev;
481 
482 	cdns_pcie_disable_phy(cdns_pcie);
483 	pm_runtime_put(dev);
484 	pm_runtime_disable(dev);
485 
486 	return 0;
487 }
488 
489 static struct platform_driver j721e_pcie_driver = {
490 	.probe  = j721e_pcie_probe,
491 	.remove = j721e_pcie_remove,
492 	.driver = {
493 		.name	= "j721e-pcie",
494 		.of_match_table = of_j721e_pcie_match,
495 		.suppress_bind_attrs = true,
496 	},
497 };
498 builtin_platform_driver(j721e_pcie_driver);
499