1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #include "../../pci.h" 23 #include "pcie-cadence.h" 24 25 #define ENABLE_REG_SYS_2 0x108 26 #define STATUS_REG_SYS_2 0x508 27 #define STATUS_CLR_REG_SYS_2 0x708 28 #define LINK_DOWN BIT(1) 29 #define J7200_LINK_DOWN BIT(10) 30 31 #define J721E_PCIE_USER_CMD_STATUS 0x4 32 #define LINK_TRAINING_ENABLE BIT(0) 33 34 #define J721E_PCIE_USER_LINKSTATUS 0x14 35 #define LINK_STATUS GENMASK(1, 0) 36 37 enum link_status { 38 NO_RECEIVERS_DETECTED, 39 LINK_TRAINING_IN_PROGRESS, 40 LINK_UP_DL_IN_PROGRESS, 41 LINK_UP_DL_COMPLETED, 42 }; 43 44 #define J721E_MODE_RC BIT(7) 45 #define LANE_COUNT(n) ((n) << 8) 46 47 #define GENERATION_SEL_MASK GENMASK(1, 0) 48 49 struct j721e_pcie { 50 struct cdns_pcie *cdns_pcie; 51 struct clk *refclk; 52 u32 mode; 53 u32 num_lanes; 54 u32 max_lanes; 55 void __iomem *user_cfg_base; 56 void __iomem *intd_cfg_base; 57 u32 linkdown_irq_regfield; 58 }; 59 60 enum j721e_pcie_mode { 61 PCI_MODE_RC, 62 PCI_MODE_EP, 63 }; 64 65 struct j721e_pcie_data { 66 enum j721e_pcie_mode mode; 67 unsigned int quirk_retrain_flag:1; 68 unsigned int quirk_detect_quiet_flag:1; 69 unsigned int quirk_disable_flr:1; 70 u32 linkdown_irq_regfield; 71 unsigned int byte_access_allowed:1; 72 unsigned int max_lanes; 73 }; 74 75 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 76 { 77 return readl(pcie->user_cfg_base + offset); 78 } 79 80 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 81 u32 value) 82 { 83 writel(value, pcie->user_cfg_base + offset); 84 } 85 86 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 87 { 88 return readl(pcie->intd_cfg_base + offset); 89 } 90 91 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 92 u32 value) 93 { 94 writel(value, pcie->intd_cfg_base + offset); 95 } 96 97 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 98 { 99 struct j721e_pcie *pcie = priv; 100 struct device *dev = pcie->cdns_pcie->dev; 101 u32 reg; 102 103 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 104 if (!(reg & pcie->linkdown_irq_regfield)) 105 return IRQ_NONE; 106 107 dev_err(dev, "LINK DOWN!\n"); 108 109 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 110 return IRQ_HANDLED; 111 } 112 113 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 114 { 115 u32 reg; 116 117 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 118 reg |= pcie->linkdown_irq_regfield; 119 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 120 } 121 122 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 123 { 124 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 125 u32 reg; 126 127 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 128 reg |= LINK_TRAINING_ENABLE; 129 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 130 131 return 0; 132 } 133 134 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 135 { 136 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 137 u32 reg; 138 139 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 140 reg &= ~LINK_TRAINING_ENABLE; 141 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 142 } 143 144 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 145 { 146 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 147 u32 reg; 148 149 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 150 reg &= LINK_STATUS; 151 if (reg == LINK_UP_DL_COMPLETED) 152 return true; 153 154 return false; 155 } 156 157 static const struct cdns_pcie_ops j721e_pcie_ops = { 158 .start_link = j721e_pcie_start_link, 159 .stop_link = j721e_pcie_stop_link, 160 .link_up = j721e_pcie_link_up, 161 }; 162 163 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 164 unsigned int offset) 165 { 166 struct device *dev = pcie->cdns_pcie->dev; 167 u32 mask = J721E_MODE_RC; 168 u32 mode = pcie->mode; 169 u32 val = 0; 170 int ret = 0; 171 172 if (mode == PCI_MODE_RC) 173 val = J721E_MODE_RC; 174 175 ret = regmap_update_bits(syscon, offset, mask, val); 176 if (ret) 177 dev_err(dev, "failed to set pcie mode\n"); 178 179 return ret; 180 } 181 182 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 183 struct regmap *syscon, unsigned int offset) 184 { 185 struct device *dev = pcie->cdns_pcie->dev; 186 struct device_node *np = dev->of_node; 187 int link_speed; 188 u32 val = 0; 189 int ret; 190 191 link_speed = of_pci_get_max_link_speed(np); 192 if (link_speed < 2) 193 link_speed = 2; 194 195 val = link_speed - 1; 196 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 197 if (ret) 198 dev_err(dev, "failed to set link speed\n"); 199 200 return ret; 201 } 202 203 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 204 struct regmap *syscon, unsigned int offset) 205 { 206 struct device *dev = pcie->cdns_pcie->dev; 207 u32 lanes = pcie->num_lanes; 208 u32 mask = BIT(8); 209 u32 val = 0; 210 int ret; 211 212 if (pcie->max_lanes == 4) 213 mask = GENMASK(9, 8); 214 215 val = LANE_COUNT(lanes - 1); 216 ret = regmap_update_bits(syscon, offset, mask, val); 217 if (ret) 218 dev_err(dev, "failed to set link count\n"); 219 220 return ret; 221 } 222 223 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 224 { 225 struct device *dev = pcie->cdns_pcie->dev; 226 struct device_node *node = dev->of_node; 227 struct of_phandle_args args; 228 unsigned int offset = 0; 229 struct regmap *syscon; 230 int ret; 231 232 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 233 if (IS_ERR(syscon)) { 234 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 235 return PTR_ERR(syscon); 236 } 237 238 /* Do not error out to maintain old DT compatibility */ 239 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 240 0, &args); 241 if (!ret) 242 offset = args.args[0]; 243 244 ret = j721e_pcie_set_mode(pcie, syscon, offset); 245 if (ret < 0) { 246 dev_err(dev, "Failed to set pci mode\n"); 247 return ret; 248 } 249 250 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 251 if (ret < 0) { 252 dev_err(dev, "Failed to set link speed\n"); 253 return ret; 254 } 255 256 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 257 if (ret < 0) { 258 dev_err(dev, "Failed to set num-lanes\n"); 259 return ret; 260 } 261 262 return 0; 263 } 264 265 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 266 int where, int size, u32 *value) 267 { 268 if (pci_is_root_bus(bus)) 269 return pci_generic_config_read32(bus, devfn, where, size, 270 value); 271 272 return pci_generic_config_read(bus, devfn, where, size, value); 273 } 274 275 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 276 int where, int size, u32 value) 277 { 278 if (pci_is_root_bus(bus)) 279 return pci_generic_config_write32(bus, devfn, where, size, 280 value); 281 282 return pci_generic_config_write(bus, devfn, where, size, value); 283 } 284 285 static struct pci_ops cdns_ti_pcie_host_ops = { 286 .map_bus = cdns_pci_map_bus, 287 .read = cdns_ti_pcie_config_read, 288 .write = cdns_ti_pcie_config_write, 289 }; 290 291 static const struct j721e_pcie_data j721e_pcie_rc_data = { 292 .mode = PCI_MODE_RC, 293 .quirk_retrain_flag = true, 294 .byte_access_allowed = false, 295 .linkdown_irq_regfield = LINK_DOWN, 296 .max_lanes = 2, 297 }; 298 299 static const struct j721e_pcie_data j721e_pcie_ep_data = { 300 .mode = PCI_MODE_EP, 301 .linkdown_irq_regfield = LINK_DOWN, 302 .max_lanes = 2, 303 }; 304 305 static const struct j721e_pcie_data j7200_pcie_rc_data = { 306 .mode = PCI_MODE_RC, 307 .quirk_detect_quiet_flag = true, 308 .linkdown_irq_regfield = J7200_LINK_DOWN, 309 .byte_access_allowed = true, 310 .max_lanes = 2, 311 }; 312 313 static const struct j721e_pcie_data j7200_pcie_ep_data = { 314 .mode = PCI_MODE_EP, 315 .quirk_detect_quiet_flag = true, 316 .quirk_disable_flr = true, 317 .max_lanes = 2, 318 }; 319 320 static const struct j721e_pcie_data am64_pcie_rc_data = { 321 .mode = PCI_MODE_RC, 322 .linkdown_irq_regfield = J7200_LINK_DOWN, 323 .byte_access_allowed = true, 324 .max_lanes = 1, 325 }; 326 327 static const struct j721e_pcie_data am64_pcie_ep_data = { 328 .mode = PCI_MODE_EP, 329 .linkdown_irq_regfield = J7200_LINK_DOWN, 330 .max_lanes = 1, 331 }; 332 333 static const struct j721e_pcie_data j784s4_pcie_rc_data = { 334 .mode = PCI_MODE_RC, 335 .quirk_retrain_flag = true, 336 .byte_access_allowed = false, 337 .linkdown_irq_regfield = LINK_DOWN, 338 .max_lanes = 4, 339 }; 340 341 static const struct j721e_pcie_data j784s4_pcie_ep_data = { 342 .mode = PCI_MODE_EP, 343 .linkdown_irq_regfield = LINK_DOWN, 344 .max_lanes = 4, 345 }; 346 347 static const struct of_device_id of_j721e_pcie_match[] = { 348 { 349 .compatible = "ti,j721e-pcie-host", 350 .data = &j721e_pcie_rc_data, 351 }, 352 { 353 .compatible = "ti,j721e-pcie-ep", 354 .data = &j721e_pcie_ep_data, 355 }, 356 { 357 .compatible = "ti,j7200-pcie-host", 358 .data = &j7200_pcie_rc_data, 359 }, 360 { 361 .compatible = "ti,j7200-pcie-ep", 362 .data = &j7200_pcie_ep_data, 363 }, 364 { 365 .compatible = "ti,am64-pcie-host", 366 .data = &am64_pcie_rc_data, 367 }, 368 { 369 .compatible = "ti,am64-pcie-ep", 370 .data = &am64_pcie_ep_data, 371 }, 372 { 373 .compatible = "ti,j784s4-pcie-host", 374 .data = &j784s4_pcie_rc_data, 375 }, 376 { 377 .compatible = "ti,j784s4-pcie-ep", 378 .data = &j784s4_pcie_ep_data, 379 }, 380 {}, 381 }; 382 383 static int j721e_pcie_probe(struct platform_device *pdev) 384 { 385 struct device *dev = &pdev->dev; 386 struct device_node *node = dev->of_node; 387 struct pci_host_bridge *bridge; 388 const struct j721e_pcie_data *data; 389 struct cdns_pcie *cdns_pcie; 390 struct j721e_pcie *pcie; 391 struct cdns_pcie_rc *rc = NULL; 392 struct cdns_pcie_ep *ep = NULL; 393 struct gpio_desc *gpiod; 394 void __iomem *base; 395 struct clk *clk; 396 u32 num_lanes; 397 u32 mode; 398 int ret; 399 int irq; 400 401 data = of_device_get_match_data(dev); 402 if (!data) 403 return -EINVAL; 404 405 mode = (u32)data->mode; 406 407 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 408 if (!pcie) 409 return -ENOMEM; 410 411 switch (mode) { 412 case PCI_MODE_RC: 413 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) 414 return -ENODEV; 415 416 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 417 if (!bridge) 418 return -ENOMEM; 419 420 if (!data->byte_access_allowed) 421 bridge->ops = &cdns_ti_pcie_host_ops; 422 rc = pci_host_bridge_priv(bridge); 423 rc->quirk_retrain_flag = data->quirk_retrain_flag; 424 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 425 426 cdns_pcie = &rc->pcie; 427 cdns_pcie->dev = dev; 428 cdns_pcie->ops = &j721e_pcie_ops; 429 pcie->cdns_pcie = cdns_pcie; 430 break; 431 case PCI_MODE_EP: 432 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) 433 return -ENODEV; 434 435 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 436 if (!ep) 437 return -ENOMEM; 438 439 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 440 ep->quirk_disable_flr = data->quirk_disable_flr; 441 442 cdns_pcie = &ep->pcie; 443 cdns_pcie->dev = dev; 444 cdns_pcie->ops = &j721e_pcie_ops; 445 pcie->cdns_pcie = cdns_pcie; 446 break; 447 default: 448 dev_err(dev, "INVALID device type %d\n", mode); 449 return 0; 450 } 451 452 pcie->mode = mode; 453 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 454 455 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 456 if (IS_ERR(base)) 457 return PTR_ERR(base); 458 pcie->intd_cfg_base = base; 459 460 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 461 if (IS_ERR(base)) 462 return PTR_ERR(base); 463 pcie->user_cfg_base = base; 464 465 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 466 if (ret || num_lanes > data->max_lanes) { 467 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); 468 num_lanes = 1; 469 } 470 471 pcie->num_lanes = num_lanes; 472 pcie->max_lanes = data->max_lanes; 473 474 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 475 return -EINVAL; 476 477 irq = platform_get_irq_byname(pdev, "link_state"); 478 if (irq < 0) 479 return irq; 480 481 dev_set_drvdata(dev, pcie); 482 pm_runtime_enable(dev); 483 ret = pm_runtime_get_sync(dev); 484 if (ret < 0) { 485 dev_err(dev, "pm_runtime_get_sync failed\n"); 486 goto err_get_sync; 487 } 488 489 ret = j721e_pcie_ctrl_init(pcie); 490 if (ret < 0) { 491 dev_err(dev, "pm_runtime_get_sync failed\n"); 492 goto err_get_sync; 493 } 494 495 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 496 "j721e-pcie-link-down-irq", pcie); 497 if (ret < 0) { 498 dev_err(dev, "failed to request link state IRQ %d\n", irq); 499 goto err_get_sync; 500 } 501 502 j721e_pcie_config_link_irq(pcie); 503 504 switch (mode) { 505 case PCI_MODE_RC: 506 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 507 if (IS_ERR(gpiod)) { 508 ret = PTR_ERR(gpiod); 509 if (ret != -EPROBE_DEFER) 510 dev_err(dev, "Failed to get reset GPIO\n"); 511 goto err_get_sync; 512 } 513 514 ret = cdns_pcie_init_phy(dev, cdns_pcie); 515 if (ret) { 516 dev_err(dev, "Failed to init phy\n"); 517 goto err_get_sync; 518 } 519 520 clk = devm_clk_get_optional(dev, "pcie_refclk"); 521 if (IS_ERR(clk)) { 522 ret = PTR_ERR(clk); 523 dev_err(dev, "failed to get pcie_refclk\n"); 524 goto err_pcie_setup; 525 } 526 527 ret = clk_prepare_enable(clk); 528 if (ret) { 529 dev_err(dev, "failed to enable pcie_refclk\n"); 530 goto err_pcie_setup; 531 } 532 pcie->refclk = clk; 533 534 /* 535 * "Power Sequencing and Reset Signal Timings" table in 536 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 537 * indicates PERST# should be deasserted after minimum of 100us 538 * once REFCLK is stable. The REFCLK to the connector in RC 539 * mode is selected while enabling the PHY. So deassert PERST# 540 * after 100 us. 541 */ 542 if (gpiod) { 543 usleep_range(100, 200); 544 gpiod_set_value_cansleep(gpiod, 1); 545 } 546 547 ret = cdns_pcie_host_setup(rc); 548 if (ret < 0) { 549 clk_disable_unprepare(pcie->refclk); 550 goto err_pcie_setup; 551 } 552 553 break; 554 case PCI_MODE_EP: 555 ret = cdns_pcie_init_phy(dev, cdns_pcie); 556 if (ret) { 557 dev_err(dev, "Failed to init phy\n"); 558 goto err_get_sync; 559 } 560 561 ret = cdns_pcie_ep_setup(ep); 562 if (ret < 0) 563 goto err_pcie_setup; 564 565 break; 566 } 567 568 return 0; 569 570 err_pcie_setup: 571 cdns_pcie_disable_phy(cdns_pcie); 572 573 err_get_sync: 574 pm_runtime_put(dev); 575 pm_runtime_disable(dev); 576 577 return ret; 578 } 579 580 static void j721e_pcie_remove(struct platform_device *pdev) 581 { 582 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 583 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 584 struct device *dev = &pdev->dev; 585 586 clk_disable_unprepare(pcie->refclk); 587 cdns_pcie_disable_phy(cdns_pcie); 588 pm_runtime_put(dev); 589 pm_runtime_disable(dev); 590 } 591 592 static struct platform_driver j721e_pcie_driver = { 593 .probe = j721e_pcie_probe, 594 .remove_new = j721e_pcie_remove, 595 .driver = { 596 .name = "j721e-pcie", 597 .of_match_table = of_j721e_pcie_match, 598 .suppress_bind_attrs = true, 599 }, 600 }; 601 builtin_platform_driver(j721e_pcie_driver); 602