1 #include <linux/delay.h> 2 #include <linux/pci.h> 3 #include <linux/module.h> 4 #include <linux/sched.h> 5 #include <linux/slab.h> 6 #include <linux/ioport.h> 7 #include <linux/wait.h> 8 9 #include "pci.h" 10 11 /* 12 * This interrupt-safe spinlock protects all accesses to PCI 13 * configuration space. 14 */ 15 16 static DEFINE_SPINLOCK(pci_lock); 17 18 /* 19 * Wrappers for all PCI configuration access functions. They just check 20 * alignment, do locking and call the low-level functions pointed to 21 * by pci_dev->ops. 22 */ 23 24 #define PCI_byte_BAD 0 25 #define PCI_word_BAD (pos & 1) 26 #define PCI_dword_BAD (pos & 3) 27 28 #define PCI_OP_READ(size,type,len) \ 29 int pci_bus_read_config_##size \ 30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ 31 { \ 32 int res; \ 33 unsigned long flags; \ 34 u32 data = 0; \ 35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 36 spin_lock_irqsave(&pci_lock, flags); \ 37 res = bus->ops->read(bus, devfn, pos, len, &data); \ 38 *value = (type)data; \ 39 spin_unlock_irqrestore(&pci_lock, flags); \ 40 return res; \ 41 } 42 43 #define PCI_OP_WRITE(size,type,len) \ 44 int pci_bus_write_config_##size \ 45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ 46 { \ 47 int res; \ 48 unsigned long flags; \ 49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 50 spin_lock_irqsave(&pci_lock, flags); \ 51 res = bus->ops->write(bus, devfn, pos, len, value); \ 52 spin_unlock_irqrestore(&pci_lock, flags); \ 53 return res; \ 54 } 55 56 PCI_OP_READ(byte, u8, 1) 57 PCI_OP_READ(word, u16, 2) 58 PCI_OP_READ(dword, u32, 4) 59 PCI_OP_WRITE(byte, u8, 1) 60 PCI_OP_WRITE(word, u16, 2) 61 PCI_OP_WRITE(dword, u32, 4) 62 63 EXPORT_SYMBOL(pci_bus_read_config_byte); 64 EXPORT_SYMBOL(pci_bus_read_config_word); 65 EXPORT_SYMBOL(pci_bus_read_config_dword); 66 EXPORT_SYMBOL(pci_bus_write_config_byte); 67 EXPORT_SYMBOL(pci_bus_write_config_word); 68 EXPORT_SYMBOL(pci_bus_write_config_dword); 69 70 /** 71 * pci_bus_set_ops - Set raw operations of pci bus 72 * @bus: pci bus struct 73 * @ops: new raw operations 74 * 75 * Return previous raw operations 76 */ 77 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) 78 { 79 struct pci_ops *old_ops; 80 unsigned long flags; 81 82 spin_lock_irqsave(&pci_lock, flags); 83 old_ops = bus->ops; 84 bus->ops = ops; 85 spin_unlock_irqrestore(&pci_lock, flags); 86 return old_ops; 87 } 88 EXPORT_SYMBOL(pci_bus_set_ops); 89 90 /** 91 * pci_read_vpd - Read one entry from Vital Product Data 92 * @dev: pci device struct 93 * @pos: offset in vpd space 94 * @count: number of bytes to read 95 * @buf: pointer to where to store result 96 * 97 */ 98 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) 99 { 100 if (!dev->vpd || !dev->vpd->ops) 101 return -ENODEV; 102 return dev->vpd->ops->read(dev, pos, count, buf); 103 } 104 EXPORT_SYMBOL(pci_read_vpd); 105 106 /** 107 * pci_write_vpd - Write entry to Vital Product Data 108 * @dev: pci device struct 109 * @pos: offset in vpd space 110 * @count: number of bytes to write 111 * @buf: buffer containing write data 112 * 113 */ 114 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) 115 { 116 if (!dev->vpd || !dev->vpd->ops) 117 return -ENODEV; 118 return dev->vpd->ops->write(dev, pos, count, buf); 119 } 120 EXPORT_SYMBOL(pci_write_vpd); 121 122 /* 123 * The following routines are to prevent the user from accessing PCI config 124 * space when it's unsafe to do so. Some devices require this during BIST and 125 * we're required to prevent it during D-state transitions. 126 * 127 * We have a bit per device to indicate it's blocked and a global wait queue 128 * for callers to sleep on until devices are unblocked. 129 */ 130 static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait); 131 132 static noinline void pci_wait_ucfg(struct pci_dev *dev) 133 { 134 DECLARE_WAITQUEUE(wait, current); 135 136 __add_wait_queue(&pci_ucfg_wait, &wait); 137 do { 138 set_current_state(TASK_UNINTERRUPTIBLE); 139 spin_unlock_irq(&pci_lock); 140 schedule(); 141 spin_lock_irq(&pci_lock); 142 } while (dev->block_ucfg_access); 143 __remove_wait_queue(&pci_ucfg_wait, &wait); 144 } 145 146 #define PCI_USER_READ_CONFIG(size,type) \ 147 int pci_user_read_config_##size \ 148 (struct pci_dev *dev, int pos, type *val) \ 149 { \ 150 int ret = 0; \ 151 u32 data = -1; \ 152 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 153 spin_lock_irq(&pci_lock); \ 154 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 155 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 156 pos, sizeof(type), &data); \ 157 spin_unlock_irq(&pci_lock); \ 158 *val = (type)data; \ 159 return ret; \ 160 } 161 162 #define PCI_USER_WRITE_CONFIG(size,type) \ 163 int pci_user_write_config_##size \ 164 (struct pci_dev *dev, int pos, type val) \ 165 { \ 166 int ret = -EIO; \ 167 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 168 spin_lock_irq(&pci_lock); \ 169 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 170 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 171 pos, sizeof(type), val); \ 172 spin_unlock_irq(&pci_lock); \ 173 return ret; \ 174 } 175 176 PCI_USER_READ_CONFIG(byte, u8) 177 PCI_USER_READ_CONFIG(word, u16) 178 PCI_USER_READ_CONFIG(dword, u32) 179 PCI_USER_WRITE_CONFIG(byte, u8) 180 PCI_USER_WRITE_CONFIG(word, u16) 181 PCI_USER_WRITE_CONFIG(dword, u32) 182 183 /* VPD access through PCI 2.2+ VPD capability */ 184 185 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) 186 187 struct pci_vpd_pci22 { 188 struct pci_vpd base; 189 struct mutex lock; 190 u16 flag; 191 bool busy; 192 u8 cap; 193 }; 194 195 /* 196 * Wait for last operation to complete. 197 * This code has to spin since there is no other notification from the PCI 198 * hardware. Since the VPD is often implemented by serial attachment to an 199 * EEPROM, it may take many milliseconds to complete. 200 */ 201 static int pci_vpd_pci22_wait(struct pci_dev *dev) 202 { 203 struct pci_vpd_pci22 *vpd = 204 container_of(dev->vpd, struct pci_vpd_pci22, base); 205 unsigned long timeout = jiffies + HZ/20 + 2; 206 u16 status; 207 int ret; 208 209 if (!vpd->busy) 210 return 0; 211 212 for (;;) { 213 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, 214 &status); 215 if (ret) 216 return ret; 217 218 if ((status & PCI_VPD_ADDR_F) == vpd->flag) { 219 vpd->busy = false; 220 return 0; 221 } 222 223 if (time_after(jiffies, timeout)) 224 return -ETIMEDOUT; 225 if (fatal_signal_pending(current)) 226 return -EINTR; 227 if (!cond_resched()) 228 udelay(10); 229 } 230 } 231 232 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, 233 void *arg) 234 { 235 struct pci_vpd_pci22 *vpd = 236 container_of(dev->vpd, struct pci_vpd_pci22, base); 237 int ret; 238 loff_t end = pos + count; 239 u8 *buf = arg; 240 241 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len) 242 return -EINVAL; 243 244 if (mutex_lock_killable(&vpd->lock)) 245 return -EINTR; 246 247 ret = pci_vpd_pci22_wait(dev); 248 if (ret < 0) 249 goto out; 250 251 while (pos < end) { 252 u32 val; 253 unsigned int i, skip; 254 255 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 256 pos & ~3); 257 if (ret < 0) 258 break; 259 vpd->busy = true; 260 vpd->flag = PCI_VPD_ADDR_F; 261 ret = pci_vpd_pci22_wait(dev); 262 if (ret < 0) 263 break; 264 265 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); 266 if (ret < 0) 267 break; 268 269 skip = pos & 3; 270 for (i = 0; i < sizeof(u32); i++) { 271 if (i >= skip) { 272 *buf++ = val; 273 if (++pos == end) 274 break; 275 } 276 val >>= 8; 277 } 278 } 279 out: 280 mutex_unlock(&vpd->lock); 281 return ret ? ret : count; 282 } 283 284 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, 285 const void *arg) 286 { 287 struct pci_vpd_pci22 *vpd = 288 container_of(dev->vpd, struct pci_vpd_pci22, base); 289 const u8 *buf = arg; 290 loff_t end = pos + count; 291 int ret = 0; 292 293 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len) 294 return -EINVAL; 295 296 if (mutex_lock_killable(&vpd->lock)) 297 return -EINTR; 298 299 ret = pci_vpd_pci22_wait(dev); 300 if (ret < 0) 301 goto out; 302 303 while (pos < end) { 304 u32 val; 305 306 val = *buf++; 307 val |= *buf++ << 8; 308 val |= *buf++ << 16; 309 val |= *buf++ << 24; 310 311 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); 312 if (ret < 0) 313 break; 314 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 315 pos | PCI_VPD_ADDR_F); 316 if (ret < 0) 317 break; 318 319 vpd->busy = true; 320 vpd->flag = 0; 321 ret = pci_vpd_pci22_wait(dev); 322 323 pos += sizeof(u32); 324 } 325 out: 326 mutex_unlock(&vpd->lock); 327 return ret ? ret : count; 328 } 329 330 static void pci_vpd_pci22_release(struct pci_dev *dev) 331 { 332 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); 333 } 334 335 static const struct pci_vpd_ops pci_vpd_pci22_ops = { 336 .read = pci_vpd_pci22_read, 337 .write = pci_vpd_pci22_write, 338 .release = pci_vpd_pci22_release, 339 }; 340 341 int pci_vpd_pci22_init(struct pci_dev *dev) 342 { 343 struct pci_vpd_pci22 *vpd; 344 u8 cap; 345 346 cap = pci_find_capability(dev, PCI_CAP_ID_VPD); 347 if (!cap) 348 return -ENODEV; 349 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); 350 if (!vpd) 351 return -ENOMEM; 352 353 vpd->base.len = PCI_VPD_PCI22_SIZE; 354 vpd->base.ops = &pci_vpd_pci22_ops; 355 mutex_init(&vpd->lock); 356 vpd->cap = cap; 357 vpd->busy = false; 358 dev->vpd = &vpd->base; 359 return 0; 360 } 361 362 /** 363 * pci_vpd_truncate - Set available Vital Product Data size 364 * @dev: pci device struct 365 * @size: available memory in bytes 366 * 367 * Adjust size of available VPD area. 368 */ 369 int pci_vpd_truncate(struct pci_dev *dev, size_t size) 370 { 371 if (!dev->vpd) 372 return -EINVAL; 373 374 /* limited by the access method */ 375 if (size > dev->vpd->len) 376 return -EINVAL; 377 378 dev->vpd->len = size; 379 if (dev->vpd->attr) 380 dev->vpd->attr->size = size; 381 382 return 0; 383 } 384 EXPORT_SYMBOL(pci_vpd_truncate); 385 386 /** 387 * pci_block_user_cfg_access - Block userspace PCI config reads/writes 388 * @dev: pci device struct 389 * 390 * When user access is blocked, any reads or writes to config space will 391 * sleep until access is unblocked again. We don't allow nesting of 392 * block/unblock calls. 393 */ 394 void pci_block_user_cfg_access(struct pci_dev *dev) 395 { 396 unsigned long flags; 397 int was_blocked; 398 399 spin_lock_irqsave(&pci_lock, flags); 400 was_blocked = dev->block_ucfg_access; 401 dev->block_ucfg_access = 1; 402 spin_unlock_irqrestore(&pci_lock, flags); 403 404 /* If we BUG() inside the pci_lock, we're guaranteed to hose 405 * the machine */ 406 BUG_ON(was_blocked); 407 } 408 EXPORT_SYMBOL_GPL(pci_block_user_cfg_access); 409 410 /** 411 * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes 412 * @dev: pci device struct 413 * 414 * This function allows userspace PCI config accesses to resume. 415 */ 416 void pci_unblock_user_cfg_access(struct pci_dev *dev) 417 { 418 unsigned long flags; 419 420 spin_lock_irqsave(&pci_lock, flags); 421 422 /* This indicates a problem in the caller, but we don't need 423 * to kill them, unlike a double-block above. */ 424 WARN_ON(!dev->block_ucfg_access); 425 426 dev->block_ucfg_access = 0; 427 wake_up_all(&pci_ucfg_wait); 428 spin_unlock_irqrestore(&pci_lock, flags); 429 } 430 EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access); 431