1 /* Low-level parallel-port routines for 8255-based PC-style hardware. 2 * 3 * Authors: Phil Blundell <philb@gnu.org> 4 * Tim Waugh <tim@cyberelk.demon.co.uk> 5 * Jose Renau <renau@acm.org> 6 * David Campbell <campbell@torque.net> 7 * Andrea Arcangeli 8 * 9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. 10 * 11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org> 12 * DMA support - Bert De Jonghe <bert@sophis.be> 13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. 15 * Various hacks, Fred Barnes, 04/2001 16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com> 17 */ 18 19 /* This driver should work with any hardware that is broadly compatible 20 * with that in the IBM PC. This applies to the majority of integrated 21 * I/O chipsets that are commonly available. The expected register 22 * layout is: 23 * 24 * base+0 data 25 * base+1 status 26 * base+2 control 27 * 28 * In addition, there are some optional registers: 29 * 30 * base+3 EPP address 31 * base+4 EPP data 32 * base+0x400 ECP config A 33 * base+0x401 ECP config B 34 * base+0x402 ECP control 35 * 36 * All registers are 8 bits wide and read/write. If your hardware differs 37 * only in register addresses (eg because your registers are on 32-bit 38 * word boundaries) then you can alter the constants in parport_pc.h to 39 * accommodate this. 40 * 41 * Note that the ECP registers may not start at offset 0x400 for PCI cards, 42 * but rather will start at port->base_hi. 43 */ 44 45 #include <linux/config.h> 46 #include <linux/module.h> 47 #include <linux/init.h> 48 #include <linux/sched.h> 49 #include <linux/delay.h> 50 #include <linux/errno.h> 51 #include <linux/interrupt.h> 52 #include <linux/ioport.h> 53 #include <linux/kernel.h> 54 #include <linux/slab.h> 55 #include <linux/pci.h> 56 #include <linux/pnp.h> 57 #include <linux/sysctl.h> 58 59 #include <asm/io.h> 60 #include <asm/dma.h> 61 #include <asm/uaccess.h> 62 63 #include <linux/parport.h> 64 #include <linux/parport_pc.h> 65 #include <linux/via.h> 66 #include <asm/parport.h> 67 68 #define PARPORT_PC_MAX_PORTS PARPORT_MAX 69 70 #ifdef CONFIG_ISA_DMA_API 71 #define HAS_DMA 72 #endif 73 74 /* ECR modes */ 75 #define ECR_SPP 00 76 #define ECR_PS2 01 77 #define ECR_PPF 02 78 #define ECR_ECP 03 79 #define ECR_EPP 04 80 #define ECR_VND 05 81 #define ECR_TST 06 82 #define ECR_CNF 07 83 #define ECR_MODE_MASK 0xe0 84 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v)) 85 86 #undef DEBUG 87 88 #ifdef DEBUG 89 #define DPRINTK printk 90 #else 91 #define DPRINTK(stuff...) 92 #endif 93 94 95 #define NR_SUPERIOS 3 96 static struct superio_struct { /* For Super-IO chips autodetection */ 97 int io; 98 int irq; 99 int dma; 100 } superios[NR_SUPERIOS] __devinitdata = { {0,},}; 101 102 static int user_specified; 103 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 104 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 105 static int verbose_probing; 106 #endif 107 static int pci_registered_parport; 108 static int pnp_registered_parport; 109 110 /* frob_control, but for ECR */ 111 static void frob_econtrol (struct parport *pb, unsigned char m, 112 unsigned char v) 113 { 114 unsigned char ectr = 0; 115 116 if (m != 0xff) 117 ectr = inb (ECONTROL (pb)); 118 119 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", 120 m, v, ectr, (ectr & ~m) ^ v); 121 122 outb ((ectr & ~m) ^ v, ECONTROL (pb)); 123 } 124 125 static __inline__ void frob_set_mode (struct parport *p, int mode) 126 { 127 frob_econtrol (p, ECR_MODE_MASK, mode << 5); 128 } 129 130 #ifdef CONFIG_PARPORT_PC_FIFO 131 /* Safely change the mode bits in the ECR 132 Returns: 133 0 : Success 134 -EBUSY: Could not drain FIFO in some finite amount of time, 135 mode not changed! 136 */ 137 static int change_mode(struct parport *p, int m) 138 { 139 const struct parport_pc_private *priv = p->physport->private_data; 140 unsigned char oecr; 141 int mode; 142 143 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m); 144 145 if (!priv->ecr) { 146 printk (KERN_DEBUG "change_mode: but there's no ECR!\n"); 147 return 0; 148 } 149 150 /* Bits <7:5> contain the mode. */ 151 oecr = inb (ECONTROL (p)); 152 mode = (oecr >> 5) & 0x7; 153 if (mode == m) return 0; 154 155 if (mode >= 2 && !(priv->ctr & 0x20)) { 156 /* This mode resets the FIFO, so we may 157 * have to wait for it to drain first. */ 158 unsigned long expire = jiffies + p->physport->cad->timeout; 159 int counter; 160 switch (mode) { 161 case ECR_PPF: /* Parallel Port FIFO mode */ 162 case ECR_ECP: /* ECP Parallel Port mode */ 163 /* Busy wait for 200us */ 164 for (counter = 0; counter < 40; counter++) { 165 if (inb (ECONTROL (p)) & 0x01) 166 break; 167 if (signal_pending (current)) break; 168 udelay (5); 169 } 170 171 /* Poll slowly. */ 172 while (!(inb (ECONTROL (p)) & 0x01)) { 173 if (time_after_eq (jiffies, expire)) 174 /* The FIFO is stuck. */ 175 return -EBUSY; 176 schedule_timeout_interruptible(msecs_to_jiffies(10)); 177 if (signal_pending (current)) 178 break; 179 } 180 } 181 } 182 183 if (mode >= 2 && m >= 2) { 184 /* We have to go through mode 001 */ 185 oecr &= ~(7 << 5); 186 oecr |= ECR_PS2 << 5; 187 ECR_WRITE (p, oecr); 188 } 189 190 /* Set the mode. */ 191 oecr &= ~(7 << 5); 192 oecr |= m << 5; 193 ECR_WRITE (p, oecr); 194 return 0; 195 } 196 197 #ifdef CONFIG_PARPORT_1284 198 /* Find FIFO lossage; FIFO is reset */ 199 #if 0 200 static int get_fifo_residue (struct parport *p) 201 { 202 int residue; 203 int cnfga; 204 const struct parport_pc_private *priv = p->physport->private_data; 205 206 /* Adjust for the contents of the FIFO. */ 207 for (residue = priv->fifo_depth; ; residue--) { 208 if (inb (ECONTROL (p)) & 0x2) 209 /* Full up. */ 210 break; 211 212 outb (0, FIFO (p)); 213 } 214 215 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, 216 residue); 217 218 /* Reset the FIFO. */ 219 frob_set_mode (p, ECR_PS2); 220 221 /* Now change to config mode and clean up. FIXME */ 222 frob_set_mode (p, ECR_CNF); 223 cnfga = inb (CONFIGA (p)); 224 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); 225 226 if (!(cnfga & (1<<2))) { 227 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name); 228 residue++; 229 } 230 231 /* Don't care about partial PWords until support is added for 232 * PWord != 1 byte. */ 233 234 /* Back to PS2 mode. */ 235 frob_set_mode (p, ECR_PS2); 236 237 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p))); 238 return residue; 239 } 240 #endif /* 0 */ 241 #endif /* IEEE 1284 support */ 242 #endif /* FIFO support */ 243 244 /* 245 * Clear TIMEOUT BIT in EPP MODE 246 * 247 * This is also used in SPP detection. 248 */ 249 static int clear_epp_timeout(struct parport *pb) 250 { 251 unsigned char r; 252 253 if (!(parport_pc_read_status(pb) & 0x01)) 254 return 1; 255 256 /* To clear timeout some chips require double read */ 257 parport_pc_read_status(pb); 258 r = parport_pc_read_status(pb); 259 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ 260 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ 261 r = parport_pc_read_status(pb); 262 263 return !(r & 0x01); 264 } 265 266 /* 267 * Access functions. 268 * 269 * Most of these aren't static because they may be used by the 270 * parport_xxx_yyy macros. extern __inline__ versions of several 271 * of these are in parport_pc.h. 272 */ 273 274 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs) 275 { 276 parport_generic_irq(irq, (struct parport *) dev_id, regs); 277 /* FIXME! Was it really ours? */ 278 return IRQ_HANDLED; 279 } 280 281 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s) 282 { 283 s->u.pc.ctr = 0xc; 284 if (dev->irq_func && 285 dev->port->irq != PARPORT_IRQ_NONE) 286 /* Set ackIntEn */ 287 s->u.pc.ctr |= 0x10; 288 289 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; 290 * D.Gruszka VScom */ 291 } 292 293 static void parport_pc_save_state(struct parport *p, struct parport_state *s) 294 { 295 const struct parport_pc_private *priv = p->physport->private_data; 296 s->u.pc.ctr = priv->ctr; 297 if (priv->ecr) 298 s->u.pc.ecr = inb (ECONTROL (p)); 299 } 300 301 static void parport_pc_restore_state(struct parport *p, struct parport_state *s) 302 { 303 struct parport_pc_private *priv = p->physport->private_data; 304 register unsigned char c = s->u.pc.ctr & priv->ctr_writable; 305 outb (c, CONTROL (p)); 306 priv->ctr = c; 307 if (priv->ecr) 308 ECR_WRITE (p, s->u.pc.ecr); 309 } 310 311 #ifdef CONFIG_PARPORT_1284 312 static size_t parport_pc_epp_read_data (struct parport *port, void *buf, 313 size_t length, int flags) 314 { 315 size_t got = 0; 316 317 if (flags & PARPORT_W91284PIC) { 318 unsigned char status; 319 size_t left = length; 320 321 /* use knowledge about data lines..: 322 * nFault is 0 if there is at least 1 byte in the Warp's FIFO 323 * pError is 1 if there are 16 bytes in the Warp's FIFO 324 */ 325 status = inb (STATUS (port)); 326 327 while (!(status & 0x08) && (got < length)) { 328 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) { 329 /* can grab 16 bytes from warp fifo */ 330 if (!((long)buf & 0x03)) { 331 insl (EPPDATA (port), buf, 4); 332 } else { 333 insb (EPPDATA (port), buf, 16); 334 } 335 buf += 16; 336 got += 16; 337 left -= 16; 338 } else { 339 /* grab single byte from the warp fifo */ 340 *((char *)buf) = inb (EPPDATA (port)); 341 buf++; 342 got++; 343 left--; 344 } 345 status = inb (STATUS (port)); 346 if (status & 0x01) { 347 /* EPP timeout should never occur... */ 348 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to " 349 "w91284pic (should not have done)\n", port->name); 350 clear_epp_timeout (port); 351 } 352 } 353 return got; 354 } 355 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 356 if (!(((long)buf | length) & 0x03)) { 357 insl (EPPDATA (port), buf, (length >> 2)); 358 } else { 359 insb (EPPDATA (port), buf, length); 360 } 361 if (inb (STATUS (port)) & 0x01) { 362 clear_epp_timeout (port); 363 return -EIO; 364 } 365 return length; 366 } 367 for (; got < length; got++) { 368 *((char*)buf) = inb (EPPDATA(port)); 369 buf++; 370 if (inb (STATUS (port)) & 0x01) { 371 /* EPP timeout */ 372 clear_epp_timeout (port); 373 break; 374 } 375 } 376 377 return got; 378 } 379 380 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf, 381 size_t length, int flags) 382 { 383 size_t written = 0; 384 385 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 386 if (!(((long)buf | length) & 0x03)) { 387 outsl (EPPDATA (port), buf, (length >> 2)); 388 } else { 389 outsb (EPPDATA (port), buf, length); 390 } 391 if (inb (STATUS (port)) & 0x01) { 392 clear_epp_timeout (port); 393 return -EIO; 394 } 395 return length; 396 } 397 for (; written < length; written++) { 398 outb (*((char*)buf), EPPDATA(port)); 399 buf++; 400 if (inb (STATUS(port)) & 0x01) { 401 clear_epp_timeout (port); 402 break; 403 } 404 } 405 406 return written; 407 } 408 409 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf, 410 size_t length, int flags) 411 { 412 size_t got = 0; 413 414 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 415 insb (EPPADDR (port), buf, length); 416 if (inb (STATUS (port)) & 0x01) { 417 clear_epp_timeout (port); 418 return -EIO; 419 } 420 return length; 421 } 422 for (; got < length; got++) { 423 *((char*)buf) = inb (EPPADDR (port)); 424 buf++; 425 if (inb (STATUS (port)) & 0x01) { 426 clear_epp_timeout (port); 427 break; 428 } 429 } 430 431 return got; 432 } 433 434 static size_t parport_pc_epp_write_addr (struct parport *port, 435 const void *buf, size_t length, 436 int flags) 437 { 438 size_t written = 0; 439 440 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 441 outsb (EPPADDR (port), buf, length); 442 if (inb (STATUS (port)) & 0x01) { 443 clear_epp_timeout (port); 444 return -EIO; 445 } 446 return length; 447 } 448 for (; written < length; written++) { 449 outb (*((char*)buf), EPPADDR (port)); 450 buf++; 451 if (inb (STATUS (port)) & 0x01) { 452 clear_epp_timeout (port); 453 break; 454 } 455 } 456 457 return written; 458 } 459 460 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf, 461 size_t length, int flags) 462 { 463 size_t got; 464 465 frob_set_mode (port, ECR_EPP); 466 parport_pc_data_reverse (port); 467 parport_pc_write_control (port, 0x4); 468 got = parport_pc_epp_read_data (port, buf, length, flags); 469 frob_set_mode (port, ECR_PS2); 470 471 return got; 472 } 473 474 static size_t parport_pc_ecpepp_write_data (struct parport *port, 475 const void *buf, size_t length, 476 int flags) 477 { 478 size_t written; 479 480 frob_set_mode (port, ECR_EPP); 481 parport_pc_write_control (port, 0x4); 482 parport_pc_data_forward (port); 483 written = parport_pc_epp_write_data (port, buf, length, flags); 484 frob_set_mode (port, ECR_PS2); 485 486 return written; 487 } 488 489 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf, 490 size_t length, int flags) 491 { 492 size_t got; 493 494 frob_set_mode (port, ECR_EPP); 495 parport_pc_data_reverse (port); 496 parport_pc_write_control (port, 0x4); 497 got = parport_pc_epp_read_addr (port, buf, length, flags); 498 frob_set_mode (port, ECR_PS2); 499 500 return got; 501 } 502 503 static size_t parport_pc_ecpepp_write_addr (struct parport *port, 504 const void *buf, size_t length, 505 int flags) 506 { 507 size_t written; 508 509 frob_set_mode (port, ECR_EPP); 510 parport_pc_write_control (port, 0x4); 511 parport_pc_data_forward (port); 512 written = parport_pc_epp_write_addr (port, buf, length, flags); 513 frob_set_mode (port, ECR_PS2); 514 515 return written; 516 } 517 #endif /* IEEE 1284 support */ 518 519 #ifdef CONFIG_PARPORT_PC_FIFO 520 static size_t parport_pc_fifo_write_block_pio (struct parport *port, 521 const void *buf, size_t length) 522 { 523 int ret = 0; 524 const unsigned char *bufp = buf; 525 size_t left = length; 526 unsigned long expire = jiffies + port->physport->cad->timeout; 527 const int fifo = FIFO (port); 528 int poll_for = 8; /* 80 usecs */ 529 const struct parport_pc_private *priv = port->physport->private_data; 530 const int fifo_depth = priv->fifo_depth; 531 532 port = port->physport; 533 534 /* We don't want to be interrupted every character. */ 535 parport_pc_disable_irq (port); 536 /* set nErrIntrEn and serviceIntr */ 537 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 538 539 /* Forward mode. */ 540 parport_pc_data_forward (port); /* Must be in PS2 mode */ 541 542 while (left) { 543 unsigned char byte; 544 unsigned char ecrval = inb (ECONTROL (port)); 545 int i = 0; 546 547 if (need_resched() && time_before (jiffies, expire)) 548 /* Can't yield the port. */ 549 schedule (); 550 551 /* Anyone else waiting for the port? */ 552 if (port->waithead) { 553 printk (KERN_DEBUG "Somebody wants the port\n"); 554 break; 555 } 556 557 if (ecrval & 0x02) { 558 /* FIFO is full. Wait for interrupt. */ 559 560 /* Clear serviceIntr */ 561 ECR_WRITE (port, ecrval & ~(1<<2)); 562 false_alarm: 563 ret = parport_wait_event (port, HZ); 564 if (ret < 0) break; 565 ret = 0; 566 if (!time_before (jiffies, expire)) { 567 /* Timed out. */ 568 printk (KERN_DEBUG "FIFO write timed out\n"); 569 break; 570 } 571 ecrval = inb (ECONTROL (port)); 572 if (!(ecrval & (1<<2))) { 573 if (need_resched() && 574 time_before (jiffies, expire)) 575 schedule (); 576 577 goto false_alarm; 578 } 579 580 continue; 581 } 582 583 /* Can't fail now. */ 584 expire = jiffies + port->cad->timeout; 585 586 poll: 587 if (signal_pending (current)) 588 break; 589 590 if (ecrval & 0x01) { 591 /* FIFO is empty. Blast it full. */ 592 const int n = left < fifo_depth ? left : fifo_depth; 593 outsb (fifo, bufp, n); 594 bufp += n; 595 left -= n; 596 597 /* Adjust the poll time. */ 598 if (i < (poll_for - 2)) poll_for--; 599 continue; 600 } else if (i++ < poll_for) { 601 udelay (10); 602 ecrval = inb (ECONTROL (port)); 603 goto poll; 604 } 605 606 /* Half-full (call me an optimist) */ 607 byte = *bufp++; 608 outb (byte, fifo); 609 left--; 610 } 611 612 dump_parport_state ("leave fifo_write_block_pio", port); 613 return length - left; 614 } 615 616 #ifdef HAS_DMA 617 static size_t parport_pc_fifo_write_block_dma (struct parport *port, 618 const void *buf, size_t length) 619 { 620 int ret = 0; 621 unsigned long dmaflag; 622 size_t left = length; 623 const struct parport_pc_private *priv = port->physport->private_data; 624 dma_addr_t dma_addr, dma_handle; 625 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ 626 unsigned long start = (unsigned long) buf; 627 unsigned long end = (unsigned long) buf + length - 1; 628 629 dump_parport_state ("enter fifo_write_block_dma", port); 630 if (end < MAX_DMA_ADDRESS) { 631 /* If it would cross a 64k boundary, cap it at the end. */ 632 if ((start ^ end) & ~0xffffUL) 633 maxlen = 0x10000 - (start & 0xffff); 634 635 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length, 636 PCI_DMA_TODEVICE); 637 } else { 638 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */ 639 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ 640 dma_addr = priv->dma_handle; 641 dma_handle = 0; 642 } 643 644 port = port->physport; 645 646 /* We don't want to be interrupted every character. */ 647 parport_pc_disable_irq (port); 648 /* set nErrIntrEn and serviceIntr */ 649 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 650 651 /* Forward mode. */ 652 parport_pc_data_forward (port); /* Must be in PS2 mode */ 653 654 while (left) { 655 unsigned long expire = jiffies + port->physport->cad->timeout; 656 657 size_t count = left; 658 659 if (count > maxlen) 660 count = maxlen; 661 662 if (!dma_handle) /* bounce buffer ! */ 663 memcpy(priv->dma_buf, buf, count); 664 665 dmaflag = claim_dma_lock(); 666 disable_dma(port->dma); 667 clear_dma_ff(port->dma); 668 set_dma_mode(port->dma, DMA_MODE_WRITE); 669 set_dma_addr(port->dma, dma_addr); 670 set_dma_count(port->dma, count); 671 672 /* Set DMA mode */ 673 frob_econtrol (port, 1<<3, 1<<3); 674 675 /* Clear serviceIntr */ 676 frob_econtrol (port, 1<<2, 0); 677 678 enable_dma(port->dma); 679 release_dma_lock(dmaflag); 680 681 /* assume DMA will be successful */ 682 left -= count; 683 buf += count; 684 if (dma_handle) dma_addr += count; 685 686 /* Wait for interrupt. */ 687 false_alarm: 688 ret = parport_wait_event (port, HZ); 689 if (ret < 0) break; 690 ret = 0; 691 if (!time_before (jiffies, expire)) { 692 /* Timed out. */ 693 printk (KERN_DEBUG "DMA write timed out\n"); 694 break; 695 } 696 /* Is serviceIntr set? */ 697 if (!(inb (ECONTROL (port)) & (1<<2))) { 698 cond_resched(); 699 700 goto false_alarm; 701 } 702 703 dmaflag = claim_dma_lock(); 704 disable_dma(port->dma); 705 clear_dma_ff(port->dma); 706 count = get_dma_residue(port->dma); 707 release_dma_lock(dmaflag); 708 709 cond_resched(); /* Can't yield the port. */ 710 711 /* Anyone else waiting for the port? */ 712 if (port->waithead) { 713 printk (KERN_DEBUG "Somebody wants the port\n"); 714 break; 715 } 716 717 /* update for possible DMA residue ! */ 718 buf -= count; 719 left += count; 720 if (dma_handle) dma_addr -= count; 721 } 722 723 /* Maybe got here through break, so adjust for DMA residue! */ 724 dmaflag = claim_dma_lock(); 725 disable_dma(port->dma); 726 clear_dma_ff(port->dma); 727 left += get_dma_residue(port->dma); 728 release_dma_lock(dmaflag); 729 730 /* Turn off DMA mode */ 731 frob_econtrol (port, 1<<3, 0); 732 733 if (dma_handle) 734 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE); 735 736 dump_parport_state ("leave fifo_write_block_dma", port); 737 return length - left; 738 } 739 #endif 740 741 static inline size_t parport_pc_fifo_write_block(struct parport *port, 742 const void *buf, size_t length) 743 { 744 #ifdef HAS_DMA 745 if (port->dma != PARPORT_DMA_NONE) 746 return parport_pc_fifo_write_block_dma (port, buf, length); 747 #endif 748 return parport_pc_fifo_write_block_pio (port, buf, length); 749 } 750 751 /* Parallel Port FIFO mode (ECP chipsets) */ 752 static size_t parport_pc_compat_write_block_pio (struct parport *port, 753 const void *buf, size_t length, 754 int flags) 755 { 756 size_t written; 757 int r; 758 unsigned long expire; 759 const struct parport_pc_private *priv = port->physport->private_data; 760 761 /* Special case: a timeout of zero means we cannot call schedule(). 762 * Also if O_NONBLOCK is set then use the default implementation. */ 763 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 764 return parport_ieee1284_write_compat (port, buf, 765 length, flags); 766 767 /* Set up parallel port FIFO mode.*/ 768 parport_pc_data_forward (port); /* Must be in PS2 mode */ 769 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0); 770 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */ 771 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name); 772 773 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 774 775 /* Write the data to the FIFO. */ 776 written = parport_pc_fifo_write_block(port, buf, length); 777 778 /* Finish up. */ 779 /* For some hardware we don't want to touch the mode until 780 * the FIFO is empty, so allow 4 seconds for each position 781 * in the fifo. 782 */ 783 expire = jiffies + (priv->fifo_depth * HZ * 4); 784 do { 785 /* Wait for the FIFO to empty */ 786 r = change_mode (port, ECR_PS2); 787 if (r != -EBUSY) { 788 break; 789 } 790 } while (time_before (jiffies, expire)); 791 if (r == -EBUSY) { 792 793 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 794 795 /* Prevent further data transfer. */ 796 frob_set_mode (port, ECR_TST); 797 798 /* Adjust for the contents of the FIFO. */ 799 for (written -= priv->fifo_depth; ; written++) { 800 if (inb (ECONTROL (port)) & 0x2) { 801 /* Full up. */ 802 break; 803 } 804 outb (0, FIFO (port)); 805 } 806 807 /* Reset the FIFO and return to PS2 mode. */ 808 frob_set_mode (port, ECR_PS2); 809 } 810 811 r = parport_wait_peripheral (port, 812 PARPORT_STATUS_BUSY, 813 PARPORT_STATUS_BUSY); 814 if (r) 815 printk (KERN_DEBUG 816 "%s: BUSY timeout (%d) in compat_write_block_pio\n", 817 port->name, r); 818 819 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 820 821 return written; 822 } 823 824 /* ECP */ 825 #ifdef CONFIG_PARPORT_1284 826 static size_t parport_pc_ecp_write_block_pio (struct parport *port, 827 const void *buf, size_t length, 828 int flags) 829 { 830 size_t written; 831 int r; 832 unsigned long expire; 833 const struct parport_pc_private *priv = port->physport->private_data; 834 835 /* Special case: a timeout of zero means we cannot call schedule(). 836 * Also if O_NONBLOCK is set then use the default implementation. */ 837 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 838 return parport_ieee1284_ecp_write_data (port, buf, 839 length, flags); 840 841 /* Switch to forward mode if necessary. */ 842 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 843 /* Event 47: Set nInit high. */ 844 parport_frob_control (port, 845 PARPORT_CONTROL_INIT 846 | PARPORT_CONTROL_AUTOFD, 847 PARPORT_CONTROL_INIT 848 | PARPORT_CONTROL_AUTOFD); 849 850 /* Event 49: PError goes high. */ 851 r = parport_wait_peripheral (port, 852 PARPORT_STATUS_PAPEROUT, 853 PARPORT_STATUS_PAPEROUT); 854 if (r) { 855 printk (KERN_DEBUG "%s: PError timeout (%d) " 856 "in ecp_write_block_pio\n", port->name, r); 857 } 858 } 859 860 /* Set up ECP parallel port mode.*/ 861 parport_pc_data_forward (port); /* Must be in PS2 mode */ 862 parport_pc_frob_control (port, 863 PARPORT_CONTROL_STROBE | 864 PARPORT_CONTROL_AUTOFD, 865 0); 866 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 867 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 868 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 869 870 /* Write the data to the FIFO. */ 871 written = parport_pc_fifo_write_block(port, buf, length); 872 873 /* Finish up. */ 874 /* For some hardware we don't want to touch the mode until 875 * the FIFO is empty, so allow 4 seconds for each position 876 * in the fifo. 877 */ 878 expire = jiffies + (priv->fifo_depth * (HZ * 4)); 879 do { 880 /* Wait for the FIFO to empty */ 881 r = change_mode (port, ECR_PS2); 882 if (r != -EBUSY) { 883 break; 884 } 885 } while (time_before (jiffies, expire)); 886 if (r == -EBUSY) { 887 888 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 889 890 /* Prevent further data transfer. */ 891 frob_set_mode (port, ECR_TST); 892 893 /* Adjust for the contents of the FIFO. */ 894 for (written -= priv->fifo_depth; ; written++) { 895 if (inb (ECONTROL (port)) & 0x2) { 896 /* Full up. */ 897 break; 898 } 899 outb (0, FIFO (port)); 900 } 901 902 /* Reset the FIFO and return to PS2 mode. */ 903 frob_set_mode (port, ECR_PS2); 904 905 /* Host transfer recovery. */ 906 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 907 udelay (5); 908 parport_frob_control (port, PARPORT_CONTROL_INIT, 0); 909 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 910 if (r) 911 printk (KERN_DEBUG "%s: PE,1 timeout (%d) " 912 "in ecp_write_block_pio\n", port->name, r); 913 914 parport_frob_control (port, 915 PARPORT_CONTROL_INIT, 916 PARPORT_CONTROL_INIT); 917 r = parport_wait_peripheral (port, 918 PARPORT_STATUS_PAPEROUT, 919 PARPORT_STATUS_PAPEROUT); 920 if (r) 921 printk (KERN_DEBUG "%s: PE,2 timeout (%d) " 922 "in ecp_write_block_pio\n", port->name, r); 923 } 924 925 r = parport_wait_peripheral (port, 926 PARPORT_STATUS_BUSY, 927 PARPORT_STATUS_BUSY); 928 if(r) 929 printk (KERN_DEBUG 930 "%s: BUSY timeout (%d) in ecp_write_block_pio\n", 931 port->name, r); 932 933 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 934 935 return written; 936 } 937 938 #if 0 939 static size_t parport_pc_ecp_read_block_pio (struct parport *port, 940 void *buf, size_t length, 941 int flags) 942 { 943 size_t left = length; 944 size_t fifofull; 945 int r; 946 const int fifo = FIFO(port); 947 const struct parport_pc_private *priv = port->physport->private_data; 948 const int fifo_depth = priv->fifo_depth; 949 char *bufp = buf; 950 951 port = port->physport; 952 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); 953 dump_parport_state ("enter fcn", port); 954 955 /* Special case: a timeout of zero means we cannot call schedule(). 956 * Also if O_NONBLOCK is set then use the default implementation. */ 957 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 958 return parport_ieee1284_ecp_read_data (port, buf, 959 length, flags); 960 961 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { 962 /* If the peripheral is allowed to send RLE compressed 963 * data, it is possible for a byte to expand to 128 964 * bytes in the FIFO. */ 965 fifofull = 128; 966 } else { 967 fifofull = fifo_depth; 968 } 969 970 /* If the caller wants less than a full FIFO's worth of data, 971 * go through software emulation. Otherwise we may have to throw 972 * away data. */ 973 if (length < fifofull) 974 return parport_ieee1284_ecp_read_data (port, buf, 975 length, flags); 976 977 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { 978 /* change to reverse-idle phase (must be in forward-idle) */ 979 980 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ 981 parport_frob_control (port, 982 PARPORT_CONTROL_AUTOFD 983 | PARPORT_CONTROL_STROBE, 984 PARPORT_CONTROL_AUTOFD); 985 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 986 udelay (5); 987 /* Event 39: Set nInit low to initiate bus reversal */ 988 parport_frob_control (port, 989 PARPORT_CONTROL_INIT, 990 0); 991 /* Event 40: Wait for nAckReverse (PError) to go low */ 992 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 993 if (r) { 994 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) " 995 "in ecp_read_block_pio\n", port->name, r); 996 return 0; 997 } 998 } 999 1000 /* Set up ECP FIFO mode.*/ 1001 /* parport_pc_frob_control (port, 1002 PARPORT_CONTROL_STROBE | 1003 PARPORT_CONTROL_AUTOFD, 1004 PARPORT_CONTROL_AUTOFD); */ 1005 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 1006 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 1007 1008 port->ieee1284.phase = IEEE1284_PH_REV_DATA; 1009 1010 /* the first byte must be collected manually */ 1011 dump_parport_state ("pre 43", port); 1012 /* Event 43: Wait for nAck to go low */ 1013 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); 1014 if (r) { 1015 /* timed out while reading -- no data */ 1016 printk (KERN_DEBUG "PIO read timed out (initial byte)\n"); 1017 goto out_no_data; 1018 } 1019 /* read byte */ 1020 *bufp++ = inb (DATA (port)); 1021 left--; 1022 dump_parport_state ("43-44", port); 1023 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ 1024 parport_pc_frob_control (port, 1025 PARPORT_CONTROL_AUTOFD, 1026 0); 1027 dump_parport_state ("pre 45", port); 1028 /* Event 45: Wait for nAck to go high */ 1029 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */ 1030 dump_parport_state ("post 45", port); 1031 r = 0; 1032 if (r) { 1033 /* timed out while waiting for peripheral to respond to ack */ 1034 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); 1035 1036 /* keep hold of the byte we've got already */ 1037 goto out_no_data; 1038 } 1039 /* Event 46: nAutoFd (HostAck) goes low to accept more data */ 1040 parport_pc_frob_control (port, 1041 PARPORT_CONTROL_AUTOFD, 1042 PARPORT_CONTROL_AUTOFD); 1043 1044 1045 dump_parport_state ("rev idle", port); 1046 /* Do the transfer. */ 1047 while (left > fifofull) { 1048 int ret; 1049 unsigned long expire = jiffies + port->cad->timeout; 1050 unsigned char ecrval = inb (ECONTROL (port)); 1051 1052 if (need_resched() && time_before (jiffies, expire)) 1053 /* Can't yield the port. */ 1054 schedule (); 1055 1056 /* At this point, the FIFO may already be full. In 1057 * that case ECP is already holding back the 1058 * peripheral (assuming proper design) with a delayed 1059 * handshake. Work fast to avoid a peripheral 1060 * timeout. */ 1061 1062 if (ecrval & 0x01) { 1063 /* FIFO is empty. Wait for interrupt. */ 1064 dump_parport_state ("FIFO empty", port); 1065 1066 /* Anyone else waiting for the port? */ 1067 if (port->waithead) { 1068 printk (KERN_DEBUG "Somebody wants the port\n"); 1069 break; 1070 } 1071 1072 /* Clear serviceIntr */ 1073 ECR_WRITE (port, ecrval & ~(1<<2)); 1074 false_alarm: 1075 dump_parport_state ("waiting", port); 1076 ret = parport_wait_event (port, HZ); 1077 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret); 1078 if (ret < 0) 1079 break; 1080 ret = 0; 1081 if (!time_before (jiffies, expire)) { 1082 /* Timed out. */ 1083 dump_parport_state ("timeout", port); 1084 printk (KERN_DEBUG "PIO read timed out\n"); 1085 break; 1086 } 1087 ecrval = inb (ECONTROL (port)); 1088 if (!(ecrval & (1<<2))) { 1089 if (need_resched() && 1090 time_before (jiffies, expire)) { 1091 schedule (); 1092 } 1093 goto false_alarm; 1094 } 1095 1096 /* Depending on how the FIFO threshold was 1097 * set, how long interrupt service took, and 1098 * how fast the peripheral is, we might be 1099 * lucky and have a just filled FIFO. */ 1100 continue; 1101 } 1102 1103 if (ecrval & 0x02) { 1104 /* FIFO is full. */ 1105 dump_parport_state ("FIFO full", port); 1106 insb (fifo, bufp, fifo_depth); 1107 bufp += fifo_depth; 1108 left -= fifo_depth; 1109 continue; 1110 } 1111 1112 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n"); 1113 1114 /* FIFO not filled. We will cycle this loop for a while 1115 * and either the peripheral will fill it faster, 1116 * tripping a fast empty with insb, or we empty it. */ 1117 *bufp++ = inb (fifo); 1118 left--; 1119 } 1120 1121 /* scoop up anything left in the FIFO */ 1122 while (left && !(inb (ECONTROL (port) & 0x01))) { 1123 *bufp++ = inb (fifo); 1124 left--; 1125 } 1126 1127 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; 1128 dump_parport_state ("rev idle2", port); 1129 1130 out_no_data: 1131 1132 /* Go to forward idle mode to shut the peripheral up (event 47). */ 1133 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); 1134 1135 /* event 49: PError goes high */ 1136 r = parport_wait_peripheral (port, 1137 PARPORT_STATUS_PAPEROUT, 1138 PARPORT_STATUS_PAPEROUT); 1139 if (r) { 1140 printk (KERN_DEBUG 1141 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", 1142 port->name, r); 1143 } 1144 1145 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1146 1147 /* Finish up. */ 1148 { 1149 int lost = get_fifo_residue (port); 1150 if (lost) 1151 /* Shouldn't happen with compliant peripherals. */ 1152 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", 1153 port->name, lost); 1154 } 1155 1156 dump_parport_state ("fwd idle", port); 1157 return length - left; 1158 } 1159 #endif /* 0 */ 1160 #endif /* IEEE 1284 support */ 1161 #endif /* Allowed to use FIFO/DMA */ 1162 1163 1164 /* 1165 * ****************************************** 1166 * INITIALISATION AND MODULE STUFF BELOW HERE 1167 * ****************************************** 1168 */ 1169 1170 /* GCC is not inlining extern inline function later overwriten to non-inline, 1171 so we use outlined_ variants here. */ 1172 static struct parport_operations parport_pc_ops = 1173 { 1174 .write_data = parport_pc_write_data, 1175 .read_data = parport_pc_read_data, 1176 1177 .write_control = parport_pc_write_control, 1178 .read_control = parport_pc_read_control, 1179 .frob_control = parport_pc_frob_control, 1180 1181 .read_status = parport_pc_read_status, 1182 1183 .enable_irq = parport_pc_enable_irq, 1184 .disable_irq = parport_pc_disable_irq, 1185 1186 .data_forward = parport_pc_data_forward, 1187 .data_reverse = parport_pc_data_reverse, 1188 1189 .init_state = parport_pc_init_state, 1190 .save_state = parport_pc_save_state, 1191 .restore_state = parport_pc_restore_state, 1192 1193 .epp_write_data = parport_ieee1284_epp_write_data, 1194 .epp_read_data = parport_ieee1284_epp_read_data, 1195 .epp_write_addr = parport_ieee1284_epp_write_addr, 1196 .epp_read_addr = parport_ieee1284_epp_read_addr, 1197 1198 .ecp_write_data = parport_ieee1284_ecp_write_data, 1199 .ecp_read_data = parport_ieee1284_ecp_read_data, 1200 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1201 1202 .compat_write_data = parport_ieee1284_write_compat, 1203 .nibble_read_data = parport_ieee1284_read_nibble, 1204 .byte_read_data = parport_ieee1284_read_byte, 1205 1206 .owner = THIS_MODULE, 1207 }; 1208 1209 #ifdef CONFIG_PARPORT_PC_SUPERIO 1210 /* Super-IO chipset detection, Winbond, SMSC */ 1211 static void __devinit show_parconfig_smsc37c669(int io, int key) 1212 { 1213 int cr1,cr4,cra,cr23,cr26,cr27,i=0; 1214 static const char *modes[]={ "SPP and Bidirectional (PS/2)", 1215 "EPP and SPP", 1216 "ECP", 1217 "ECP and EPP" }; 1218 1219 outb(key,io); 1220 outb(key,io); 1221 outb(1,io); 1222 cr1=inb(io+1); 1223 outb(4,io); 1224 cr4=inb(io+1); 1225 outb(0x0a,io); 1226 cra=inb(io+1); 1227 outb(0x23,io); 1228 cr23=inb(io+1); 1229 outb(0x26,io); 1230 cr26=inb(io+1); 1231 outb(0x27,io); 1232 cr27=inb(io+1); 1233 outb(0xaa,io); 1234 1235 if (verbose_probing) { 1236 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " 1237 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", 1238 cr1,cr4,cra,cr23,cr26,cr27); 1239 1240 /* The documentation calls DMA and IRQ-Lines by letters, so 1241 the board maker can/will wire them 1242 appropriately/randomly... G=reserved H=IDE-irq, */ 1243 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, " 1244 "fifo threshold=%d\n", cr23*4, 1245 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-', 1246 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f); 1247 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", 1248 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no"); 1249 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n", 1250 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03], 1251 (cr4 & 0x40) ? "1.7" : "1.9"); 1252 } 1253 1254 /* Heuristics ! BIOS setup for this mainboard device limits 1255 the choices to standard settings, i.e. io-address and IRQ 1256 are related, however DMA can be 1 or 3, assume DMA_A=DMA1, 1257 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ 1258 if(cr23*4 >=0x100) { /* if active */ 1259 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1260 i++; 1261 if(i==NR_SUPERIOS) 1262 printk(KERN_INFO "Super-IO: too many chips!\n"); 1263 else { 1264 int d; 1265 switch (cr23*4) { 1266 case 0x3bc: 1267 superios[i].io = 0x3bc; 1268 superios[i].irq = 7; 1269 break; 1270 case 0x378: 1271 superios[i].io = 0x378; 1272 superios[i].irq = 7; 1273 break; 1274 case 0x278: 1275 superios[i].io = 0x278; 1276 superios[i].irq = 5; 1277 } 1278 d=(cr26 &0x0f); 1279 if((d==1) || (d==3)) 1280 superios[i].dma= d; 1281 else 1282 superios[i].dma= PARPORT_DMA_NONE; 1283 } 1284 } 1285 } 1286 1287 1288 static void __devinit show_parconfig_winbond(int io, int key) 1289 { 1290 int cr30,cr60,cr61,cr70,cr74,crf0,i=0; 1291 static const char *modes[] = { 1292 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ 1293 "EPP-1.9 and SPP", 1294 "ECP", 1295 "ECP and EPP-1.9", 1296 "Standard (SPP)", 1297 "EPP-1.7 and SPP", /* 5 */ 1298 "undefined!", 1299 "ECP and EPP-1.7" }; 1300 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" }; 1301 1302 /* The registers are called compatible-PnP because the 1303 register layout is modelled after ISA-PnP, the access 1304 method is just another ... */ 1305 outb(key,io); 1306 outb(key,io); 1307 outb(0x07,io); /* Register 7: Select Logical Device */ 1308 outb(0x01,io+1); /* LD1 is Parallel Port */ 1309 outb(0x30,io); 1310 cr30=inb(io+1); 1311 outb(0x60,io); 1312 cr60=inb(io+1); 1313 outb(0x61,io); 1314 cr61=inb(io+1); 1315 outb(0x70,io); 1316 cr70=inb(io+1); 1317 outb(0x74,io); 1318 cr74=inb(io+1); 1319 outb(0xf0,io); 1320 crf0=inb(io+1); 1321 outb(0xaa,io); 1322 1323 if (verbose_probing) { 1324 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x " 1325 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0); 1326 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", 1327 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f ); 1328 if ((cr74 & 0x07) > 3) 1329 printk("dma=none\n"); 1330 else 1331 printk("dma=%d\n",cr74 & 0x07); 1332 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", 1333 irqtypes[crf0>>7], (crf0>>3)&0x0f); 1334 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]); 1335 } 1336 1337 if(cr30 & 0x01) { /* the settings can be interrogated later ... */ 1338 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1339 i++; 1340 if(i==NR_SUPERIOS) 1341 printk(KERN_INFO "Super-IO: too many chips!\n"); 1342 else { 1343 superios[i].io = (cr60<<8)|cr61; 1344 superios[i].irq = cr70&0x0f; 1345 superios[i].dma = (((cr74 & 0x07) > 3) ? 1346 PARPORT_DMA_NONE : (cr74 & 0x07)); 1347 } 1348 } 1349 } 1350 1351 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid) 1352 { 1353 const char *type = "unknown"; 1354 int id,progif=2; 1355 1356 if (devid == devrev) 1357 /* simple heuristics, we happened to read some 1358 non-winbond register */ 1359 return; 1360 1361 id=(devid<<8) | devrev; 1362 1363 /* Values are from public data sheets pdf files, I can just 1364 confirm 83977TF is correct :-) */ 1365 if (id == 0x9771) type="83977F/AF"; 1366 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x"; 1367 else if (id == 0x9774) type="83977ATF"; 1368 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x"; 1369 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x"; 1370 else if ((id & ~0x0f) == 0x5210) type="83627"; 1371 else if ((id & ~0x0f) == 0x6010) type="83697HF"; 1372 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;} 1373 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;} 1374 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;} 1375 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;} 1376 else progif=0; 1377 1378 if (verbose_probing) 1379 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " 1380 "devid=%02x devrev=%02x oldid=%02x type=%s\n", 1381 efer, key, devid, devrev, oldid, type); 1382 1383 if (progif == 2) 1384 show_parconfig_winbond(efer,key); 1385 } 1386 1387 static void __devinit decode_smsc(int efer, int key, int devid, int devrev) 1388 { 1389 const char *type = "unknown"; 1390 void (*func)(int io, int key); 1391 int id; 1392 1393 if (devid == devrev) 1394 /* simple heuristics, we happened to read some 1395 non-smsc register */ 1396 return; 1397 1398 func=NULL; 1399 id=(devid<<8) | devrev; 1400 1401 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;} 1402 else if (id==0x6582) type="37c665IR"; 1403 else if (devid==0x65) type="37c665GT"; 1404 else if (devid==0x66) type="37c666GT"; 1405 1406 if (verbose_probing) 1407 printk(KERN_INFO "SMSC chip at EFER=0x%x " 1408 "key=0x%02x devid=%02x devrev=%02x type=%s\n", 1409 efer, key, devid, devrev, type); 1410 1411 if (func) 1412 func(efer,key); 1413 } 1414 1415 1416 static void __devinit winbond_check(int io, int key) 1417 { 1418 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1419 1420 if (!request_region(io, 3, __FUNCTION__)) 1421 return; 1422 1423 /* First probe without key */ 1424 outb(0x20,io); 1425 x_devid=inb(io+1); 1426 outb(0x21,io); 1427 x_devrev=inb(io+1); 1428 outb(0x09,io); 1429 x_oldid=inb(io+1); 1430 1431 outb(key,io); 1432 outb(key,io); /* Write Magic Sequence to EFER, extended 1433 funtion enable register */ 1434 outb(0x20,io); /* Write EFIR, extended function index register */ 1435 devid=inb(io+1); /* Read EFDR, extended function data register */ 1436 outb(0x21,io); 1437 devrev=inb(io+1); 1438 outb(0x09,io); 1439 oldid=inb(io+1); 1440 outb(0xaa,io); /* Magic Seal */ 1441 1442 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1443 goto out; /* protection against false positives */ 1444 1445 decode_winbond(io,key,devid,devrev,oldid); 1446 out: 1447 release_region(io, 3); 1448 } 1449 1450 static void __devinit winbond_check2(int io,int key) 1451 { 1452 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1453 1454 if (!request_region(io, 3, __FUNCTION__)) 1455 return; 1456 1457 /* First probe without the key */ 1458 outb(0x20,io+2); 1459 x_devid=inb(io+2); 1460 outb(0x21,io+1); 1461 x_devrev=inb(io+2); 1462 outb(0x09,io+1); 1463 x_oldid=inb(io+2); 1464 1465 outb(key,io); /* Write Magic Byte to EFER, extended 1466 funtion enable register */ 1467 outb(0x20,io+2); /* Write EFIR, extended function index register */ 1468 devid=inb(io+2); /* Read EFDR, extended function data register */ 1469 outb(0x21,io+1); 1470 devrev=inb(io+2); 1471 outb(0x09,io+1); 1472 oldid=inb(io+2); 1473 outb(0xaa,io); /* Magic Seal */ 1474 1475 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1476 goto out; /* protection against false positives */ 1477 1478 decode_winbond(io,key,devid,devrev,oldid); 1479 out: 1480 release_region(io, 3); 1481 } 1482 1483 static void __devinit smsc_check(int io, int key) 1484 { 1485 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; 1486 1487 if (!request_region(io, 3, __FUNCTION__)) 1488 return; 1489 1490 /* First probe without the key */ 1491 outb(0x0d,io); 1492 x_oldid=inb(io+1); 1493 outb(0x0e,io); 1494 x_oldrev=inb(io+1); 1495 outb(0x20,io); 1496 x_id=inb(io+1); 1497 outb(0x21,io); 1498 x_rev=inb(io+1); 1499 1500 outb(key,io); 1501 outb(key,io); /* Write Magic Sequence to EFER, extended 1502 funtion enable register */ 1503 outb(0x0d,io); /* Write EFIR, extended function index register */ 1504 oldid=inb(io+1); /* Read EFDR, extended function data register */ 1505 outb(0x0e,io); 1506 oldrev=inb(io+1); 1507 outb(0x20,io); 1508 id=inb(io+1); 1509 outb(0x21,io); 1510 rev=inb(io+1); 1511 outb(0xaa,io); /* Magic Seal */ 1512 1513 if ((x_id == id) && (x_oldrev == oldrev) && 1514 (x_oldid == oldid) && (x_rev == rev)) 1515 goto out; /* protection against false positives */ 1516 1517 decode_smsc(io,key,oldid,oldrev); 1518 out: 1519 release_region(io, 3); 1520 } 1521 1522 1523 static void __devinit detect_and_report_winbond (void) 1524 { 1525 if (verbose_probing) 1526 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); 1527 winbond_check(0x3f0,0x87); 1528 winbond_check(0x370,0x87); 1529 winbond_check(0x2e ,0x87); 1530 winbond_check(0x4e ,0x87); 1531 winbond_check(0x3f0,0x86); 1532 winbond_check2(0x250,0x88); 1533 winbond_check2(0x250,0x89); 1534 } 1535 1536 static void __devinit detect_and_report_smsc (void) 1537 { 1538 if (verbose_probing) 1539 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); 1540 smsc_check(0x3f0,0x55); 1541 smsc_check(0x370,0x55); 1542 smsc_check(0x3f0,0x44); 1543 smsc_check(0x370,0x44); 1544 } 1545 #endif /* CONFIG_PARPORT_PC_SUPERIO */ 1546 1547 static int __devinit get_superio_dma (struct parport *p) 1548 { 1549 int i=0; 1550 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1551 i++; 1552 if (i!=NR_SUPERIOS) 1553 return superios[i].dma; 1554 return PARPORT_DMA_NONE; 1555 } 1556 1557 static int __devinit get_superio_irq (struct parport *p) 1558 { 1559 int i=0; 1560 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1561 i++; 1562 if (i!=NR_SUPERIOS) 1563 return superios[i].irq; 1564 return PARPORT_IRQ_NONE; 1565 } 1566 1567 1568 /* --- Mode detection ------------------------------------- */ 1569 1570 /* 1571 * Checks for port existence, all ports support SPP MODE 1572 * Returns: 1573 * 0 : No parallel port at this address 1574 * PARPORT_MODE_PCSPP : SPP port detected 1575 * (if the user specified an ioport himself, 1576 * this shall always be the case!) 1577 * 1578 */ 1579 static int __devinit parport_SPP_supported(struct parport *pb) 1580 { 1581 unsigned char r, w; 1582 1583 /* 1584 * first clear an eventually pending EPP timeout 1585 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset 1586 * that does not even respond to SPP cycles if an EPP 1587 * timeout is pending 1588 */ 1589 clear_epp_timeout(pb); 1590 1591 /* Do a simple read-write test to make sure the port exists. */ 1592 w = 0xc; 1593 outb (w, CONTROL (pb)); 1594 1595 /* Is there a control register that we can read from? Some 1596 * ports don't allow reads, so read_control just returns a 1597 * software copy. Some ports _do_ allow reads, so bypass the 1598 * software copy here. In addition, some bits aren't 1599 * writable. */ 1600 r = inb (CONTROL (pb)); 1601 if ((r & 0xf) == w) { 1602 w = 0xe; 1603 outb (w, CONTROL (pb)); 1604 r = inb (CONTROL (pb)); 1605 outb (0xc, CONTROL (pb)); 1606 if ((r & 0xf) == w) 1607 return PARPORT_MODE_PCSPP; 1608 } 1609 1610 if (user_specified) 1611 /* That didn't work, but the user thinks there's a 1612 * port here. */ 1613 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: " 1614 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1615 1616 /* Try the data register. The data lines aren't tri-stated at 1617 * this stage, so we expect back what we wrote. */ 1618 w = 0xaa; 1619 parport_pc_write_data (pb, w); 1620 r = parport_pc_read_data (pb); 1621 if (r == w) { 1622 w = 0x55; 1623 parport_pc_write_data (pb, w); 1624 r = parport_pc_read_data (pb); 1625 if (r == w) 1626 return PARPORT_MODE_PCSPP; 1627 } 1628 1629 if (user_specified) { 1630 /* Didn't work, but the user is convinced this is the 1631 * place. */ 1632 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: " 1633 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1634 printk (KERN_INFO "parport 0x%lx: You gave this address, " 1635 "but there is probably no parallel port there!\n", 1636 pb->base); 1637 } 1638 1639 /* It's possible that we can't read the control register or 1640 * the data register. In that case just believe the user. */ 1641 if (user_specified) 1642 return PARPORT_MODE_PCSPP; 1643 1644 return 0; 1645 } 1646 1647 /* Check for ECR 1648 * 1649 * Old style XT ports alias io ports every 0x400, hence accessing ECR 1650 * on these cards actually accesses the CTR. 1651 * 1652 * Modern cards don't do this but reading from ECR will return 0xff 1653 * regardless of what is written here if the card does NOT support 1654 * ECP. 1655 * 1656 * We first check to see if ECR is the same as CTR. If not, the low 1657 * two bits of ECR aren't writable, so we check by writing ECR and 1658 * reading it back to see if it's what we expect. 1659 */ 1660 static int __devinit parport_ECR_present(struct parport *pb) 1661 { 1662 struct parport_pc_private *priv = pb->private_data; 1663 unsigned char r = 0xc; 1664 1665 outb (r, CONTROL (pb)); 1666 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) { 1667 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */ 1668 1669 r = inb (CONTROL (pb)); 1670 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2)) 1671 goto no_reg; /* Sure that no ECR register exists */ 1672 } 1673 1674 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1) 1675 goto no_reg; 1676 1677 ECR_WRITE (pb, 0x34); 1678 if (inb (ECONTROL (pb)) != 0x35) 1679 goto no_reg; 1680 1681 priv->ecr = 1; 1682 outb (0xc, CONTROL (pb)); 1683 1684 /* Go to mode 000 */ 1685 frob_set_mode (pb, ECR_SPP); 1686 1687 return 1; 1688 1689 no_reg: 1690 outb (0xc, CONTROL (pb)); 1691 return 0; 1692 } 1693 1694 #ifdef CONFIG_PARPORT_1284 1695 /* Detect PS/2 support. 1696 * 1697 * Bit 5 (0x20) sets the PS/2 data direction; setting this high 1698 * allows us to read data from the data lines. In theory we would get back 1699 * 0xff but any peripheral attached to the port may drag some or all of the 1700 * lines down to zero. So if we get back anything that isn't the contents 1701 * of the data register we deem PS/2 support to be present. 1702 * 1703 * Some SPP ports have "half PS/2" ability - you can't turn off the line 1704 * drivers, but an external peripheral with sufficiently beefy drivers of 1705 * its own can overpower them and assert its own levels onto the bus, from 1706 * where they can then be read back as normal. Ports with this property 1707 * and the right type of device attached are likely to fail the SPP test, 1708 * (as they will appear to have stuck bits) and so the fact that they might 1709 * be misdetected here is rather academic. 1710 */ 1711 1712 static int __devinit parport_PS2_supported(struct parport *pb) 1713 { 1714 int ok = 0; 1715 1716 clear_epp_timeout(pb); 1717 1718 /* try to tri-state the buffer */ 1719 parport_pc_data_reverse (pb); 1720 1721 parport_pc_write_data(pb, 0x55); 1722 if (parport_pc_read_data(pb) != 0x55) ok++; 1723 1724 parport_pc_write_data(pb, 0xaa); 1725 if (parport_pc_read_data(pb) != 0xaa) ok++; 1726 1727 /* cancel input mode */ 1728 parport_pc_data_forward (pb); 1729 1730 if (ok) { 1731 pb->modes |= PARPORT_MODE_TRISTATE; 1732 } else { 1733 struct parport_pc_private *priv = pb->private_data; 1734 priv->ctr_writable &= ~0x20; 1735 } 1736 1737 return ok; 1738 } 1739 1740 #ifdef CONFIG_PARPORT_PC_FIFO 1741 static int __devinit parport_ECP_supported(struct parport *pb) 1742 { 1743 int i; 1744 int config, configb; 1745 int pword; 1746 struct parport_pc_private *priv = pb->private_data; 1747 /* Translate ECP intrLine to ISA irq value */ 1748 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 }; 1749 1750 /* If there is no ECR, we have no hope of supporting ECP. */ 1751 if (!priv->ecr) 1752 return 0; 1753 1754 /* Find out FIFO depth */ 1755 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1756 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */ 1757 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++) 1758 outb (0xaa, FIFO (pb)); 1759 1760 /* 1761 * Using LGS chipset it uses ECR register, but 1762 * it doesn't support ECP or FIFO MODE 1763 */ 1764 if (i == 1024) { 1765 ECR_WRITE (pb, ECR_SPP << 5); 1766 return 0; 1767 } 1768 1769 priv->fifo_depth = i; 1770 if (verbose_probing) 1771 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); 1772 1773 /* Find out writeIntrThreshold */ 1774 frob_econtrol (pb, 1<<2, 1<<2); 1775 frob_econtrol (pb, 1<<2, 0); 1776 for (i = 1; i <= priv->fifo_depth; i++) { 1777 inb (FIFO (pb)); 1778 udelay (50); 1779 if (inb (ECONTROL (pb)) & (1<<2)) 1780 break; 1781 } 1782 1783 if (i <= priv->fifo_depth) { 1784 if (verbose_probing) 1785 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", 1786 pb->base, i); 1787 } else 1788 /* Number of bytes we know we can write if we get an 1789 interrupt. */ 1790 i = 0; 1791 1792 priv->writeIntrThreshold = i; 1793 1794 /* Find out readIntrThreshold */ 1795 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */ 1796 parport_pc_data_reverse (pb); /* Must be in PS2 mode */ 1797 frob_set_mode (pb, ECR_TST); /* Test FIFO */ 1798 frob_econtrol (pb, 1<<2, 1<<2); 1799 frob_econtrol (pb, 1<<2, 0); 1800 for (i = 1; i <= priv->fifo_depth; i++) { 1801 outb (0xaa, FIFO (pb)); 1802 if (inb (ECONTROL (pb)) & (1<<2)) 1803 break; 1804 } 1805 1806 if (i <= priv->fifo_depth) { 1807 if (verbose_probing) 1808 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n", 1809 pb->base, i); 1810 } else 1811 /* Number of bytes we can read if we get an interrupt. */ 1812 i = 0; 1813 1814 priv->readIntrThreshold = i; 1815 1816 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1817 ECR_WRITE (pb, 0xf4); /* Configuration mode */ 1818 config = inb (CONFIGA (pb)); 1819 pword = (config >> 4) & 0x7; 1820 switch (pword) { 1821 case 0: 1822 pword = 2; 1823 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1824 pb->base); 1825 break; 1826 case 2: 1827 pword = 4; 1828 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1829 pb->base); 1830 break; 1831 default: 1832 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n", 1833 pb->base); 1834 /* Assume 1 */ 1835 case 1: 1836 pword = 1; 1837 } 1838 priv->pword = pword; 1839 1840 if (verbose_probing) { 1841 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword); 1842 1843 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, 1844 config & 0x80 ? "Level" : "Pulses"); 1845 1846 configb = inb (CONFIGB (pb)); 1847 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", 1848 pb->base, config, configb); 1849 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); 1850 if ((configb >>3) & 0x07) 1851 printk("%d",intrline[(configb >>3) & 0x07]); 1852 else 1853 printk("<none or set by other means>"); 1854 printk (" dma="); 1855 if( (configb & 0x03 ) == 0x00) 1856 printk("<none or set by other means>\n"); 1857 else 1858 printk("%d\n",configb & 0x07); 1859 } 1860 1861 /* Go back to mode 000 */ 1862 frob_set_mode (pb, ECR_SPP); 1863 1864 return 1; 1865 } 1866 #endif 1867 1868 static int __devinit parport_ECPPS2_supported(struct parport *pb) 1869 { 1870 const struct parport_pc_private *priv = pb->private_data; 1871 int result; 1872 unsigned char oecr; 1873 1874 if (!priv->ecr) 1875 return 0; 1876 1877 oecr = inb (ECONTROL (pb)); 1878 ECR_WRITE (pb, ECR_PS2 << 5); 1879 result = parport_PS2_supported(pb); 1880 ECR_WRITE (pb, oecr); 1881 return result; 1882 } 1883 1884 /* EPP mode detection */ 1885 1886 static int __devinit parport_EPP_supported(struct parport *pb) 1887 { 1888 const struct parport_pc_private *priv = pb->private_data; 1889 1890 /* 1891 * Theory: 1892 * Bit 0 of STR is the EPP timeout bit, this bit is 0 1893 * when EPP is possible and is set high when an EPP timeout 1894 * occurs (EPP uses the HALT line to stop the CPU while it does 1895 * the byte transfer, an EPP timeout occurs if the attached 1896 * device fails to respond after 10 micro seconds). 1897 * 1898 * This bit is cleared by either reading it (National Semi) 1899 * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? 1900 * This bit is always high in non EPP modes. 1901 */ 1902 1903 /* If EPP timeout bit clear then EPP available */ 1904 if (!clear_epp_timeout(pb)) { 1905 return 0; /* No way to clear timeout */ 1906 } 1907 1908 /* Check for Intel bug. */ 1909 if (priv->ecr) { 1910 unsigned char i; 1911 for (i = 0x00; i < 0x80; i += 0x20) { 1912 ECR_WRITE (pb, i); 1913 if (clear_epp_timeout (pb)) { 1914 /* Phony EPP in ECP. */ 1915 return 0; 1916 } 1917 } 1918 } 1919 1920 pb->modes |= PARPORT_MODE_EPP; 1921 1922 /* Set up access functions to use EPP hardware. */ 1923 pb->ops->epp_read_data = parport_pc_epp_read_data; 1924 pb->ops->epp_write_data = parport_pc_epp_write_data; 1925 pb->ops->epp_read_addr = parport_pc_epp_read_addr; 1926 pb->ops->epp_write_addr = parport_pc_epp_write_addr; 1927 1928 return 1; 1929 } 1930 1931 static int __devinit parport_ECPEPP_supported(struct parport *pb) 1932 { 1933 struct parport_pc_private *priv = pb->private_data; 1934 int result; 1935 unsigned char oecr; 1936 1937 if (!priv->ecr) { 1938 return 0; 1939 } 1940 1941 oecr = inb (ECONTROL (pb)); 1942 /* Search for SMC style EPP+ECP mode */ 1943 ECR_WRITE (pb, 0x80); 1944 outb (0x04, CONTROL (pb)); 1945 result = parport_EPP_supported(pb); 1946 1947 ECR_WRITE (pb, oecr); 1948 1949 if (result) { 1950 /* Set up access functions to use ECP+EPP hardware. */ 1951 pb->ops->epp_read_data = parport_pc_ecpepp_read_data; 1952 pb->ops->epp_write_data = parport_pc_ecpepp_write_data; 1953 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; 1954 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; 1955 } 1956 1957 return result; 1958 } 1959 1960 #else /* No IEEE 1284 support */ 1961 1962 /* Don't bother probing for modes we know we won't use. */ 1963 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } 1964 #ifdef CONFIG_PARPORT_PC_FIFO 1965 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; } 1966 #endif 1967 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; } 1968 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;} 1969 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;} 1970 1971 #endif /* No IEEE 1284 support */ 1972 1973 /* --- IRQ detection -------------------------------------- */ 1974 1975 /* Only if supports ECP mode */ 1976 static int __devinit programmable_irq_support(struct parport *pb) 1977 { 1978 int irq, intrLine; 1979 unsigned char oecr = inb (ECONTROL (pb)); 1980 static const int lookup[8] = { 1981 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 1982 }; 1983 1984 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */ 1985 1986 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07; 1987 irq = lookup[intrLine]; 1988 1989 ECR_WRITE (pb, oecr); 1990 return irq; 1991 } 1992 1993 static int __devinit irq_probe_ECP(struct parport *pb) 1994 { 1995 int i; 1996 unsigned long irqs; 1997 1998 irqs = probe_irq_on(); 1999 2000 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 2001 ECR_WRITE (pb, (ECR_TST << 5) | 0x04); 2002 ECR_WRITE (pb, ECR_TST << 5); 2003 2004 /* If Full FIFO sure that writeIntrThreshold is generated */ 2005 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) 2006 outb (0xaa, FIFO (pb)); 2007 2008 pb->irq = probe_irq_off(irqs); 2009 ECR_WRITE (pb, ECR_SPP << 5); 2010 2011 if (pb->irq <= 0) 2012 pb->irq = PARPORT_IRQ_NONE; 2013 2014 return pb->irq; 2015 } 2016 2017 /* 2018 * This detection seems that only works in National Semiconductors 2019 * This doesn't work in SMC, LGS, and Winbond 2020 */ 2021 static int __devinit irq_probe_EPP(struct parport *pb) 2022 { 2023 #ifndef ADVANCED_DETECT 2024 return PARPORT_IRQ_NONE; 2025 #else 2026 int irqs; 2027 unsigned char oecr; 2028 2029 if (pb->modes & PARPORT_MODE_PCECR) 2030 oecr = inb (ECONTROL (pb)); 2031 2032 irqs = probe_irq_on(); 2033 2034 if (pb->modes & PARPORT_MODE_PCECR) 2035 frob_econtrol (pb, 0x10, 0x10); 2036 2037 clear_epp_timeout(pb); 2038 parport_pc_frob_control (pb, 0x20, 0x20); 2039 parport_pc_frob_control (pb, 0x10, 0x10); 2040 clear_epp_timeout(pb); 2041 2042 /* Device isn't expecting an EPP read 2043 * and generates an IRQ. 2044 */ 2045 parport_pc_read_epp(pb); 2046 udelay(20); 2047 2048 pb->irq = probe_irq_off (irqs); 2049 if (pb->modes & PARPORT_MODE_PCECR) 2050 ECR_WRITE (pb, oecr); 2051 parport_pc_write_control(pb, 0xc); 2052 2053 if (pb->irq <= 0) 2054 pb->irq = PARPORT_IRQ_NONE; 2055 2056 return pb->irq; 2057 #endif /* Advanced detection */ 2058 } 2059 2060 static int __devinit irq_probe_SPP(struct parport *pb) 2061 { 2062 /* Don't even try to do this. */ 2063 return PARPORT_IRQ_NONE; 2064 } 2065 2066 /* We will attempt to share interrupt requests since other devices 2067 * such as sound cards and network cards seem to like using the 2068 * printer IRQs. 2069 * 2070 * When ECP is available we can autoprobe for IRQs. 2071 * NOTE: If we can autoprobe it, we can register the IRQ. 2072 */ 2073 static int __devinit parport_irq_probe(struct parport *pb) 2074 { 2075 struct parport_pc_private *priv = pb->private_data; 2076 2077 if (priv->ecr) { 2078 pb->irq = programmable_irq_support(pb); 2079 2080 if (pb->irq == PARPORT_IRQ_NONE) 2081 pb->irq = irq_probe_ECP(pb); 2082 } 2083 2084 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && 2085 (pb->modes & PARPORT_MODE_EPP)) 2086 pb->irq = irq_probe_EPP(pb); 2087 2088 clear_epp_timeout(pb); 2089 2090 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) 2091 pb->irq = irq_probe_EPP(pb); 2092 2093 clear_epp_timeout(pb); 2094 2095 if (pb->irq == PARPORT_IRQ_NONE) 2096 pb->irq = irq_probe_SPP(pb); 2097 2098 if (pb->irq == PARPORT_IRQ_NONE) 2099 pb->irq = get_superio_irq(pb); 2100 2101 return pb->irq; 2102 } 2103 2104 /* --- DMA detection -------------------------------------- */ 2105 2106 /* Only if chipset conforms to ECP ISA Interface Standard */ 2107 static int __devinit programmable_dma_support (struct parport *p) 2108 { 2109 unsigned char oecr = inb (ECONTROL (p)); 2110 int dma; 2111 2112 frob_set_mode (p, ECR_CNF); 2113 2114 dma = inb (CONFIGB(p)) & 0x07; 2115 /* 000: Indicates jumpered 8-bit DMA if read-only. 2116 100: Indicates jumpered 16-bit DMA if read-only. */ 2117 if ((dma & 0x03) == 0) 2118 dma = PARPORT_DMA_NONE; 2119 2120 ECR_WRITE (p, oecr); 2121 return dma; 2122 } 2123 2124 static int __devinit parport_dma_probe (struct parport *p) 2125 { 2126 const struct parport_pc_private *priv = p->private_data; 2127 if (priv->ecr) 2128 p->dma = programmable_dma_support(p); /* ask ECP chipset first */ 2129 if (p->dma == PARPORT_DMA_NONE) { 2130 /* ask known Super-IO chips proper, although these 2131 claim ECP compatible, some don't report their DMA 2132 conforming to ECP standards */ 2133 p->dma = get_superio_dma(p); 2134 } 2135 2136 return p->dma; 2137 } 2138 2139 /* --- Initialisation code -------------------------------- */ 2140 2141 static LIST_HEAD(ports_list); 2142 static DEFINE_SPINLOCK(ports_lock); 2143 2144 struct parport *parport_pc_probe_port (unsigned long int base, 2145 unsigned long int base_hi, 2146 int irq, int dma, 2147 struct pci_dev *dev) 2148 { 2149 struct parport_pc_private *priv; 2150 struct parport_operations *ops; 2151 struct parport *p; 2152 int probedirq = PARPORT_IRQ_NONE; 2153 struct resource *base_res; 2154 struct resource *ECR_res = NULL; 2155 struct resource *EPP_res = NULL; 2156 2157 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL); 2158 if (!ops) 2159 goto out1; 2160 2161 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL); 2162 if (!priv) 2163 goto out2; 2164 2165 /* a misnomer, actually - it's allocate and reserve parport number */ 2166 p = parport_register_port(base, irq, dma, ops); 2167 if (!p) 2168 goto out3; 2169 2170 base_res = request_region(base, 3, p->name); 2171 if (!base_res) 2172 goto out4; 2173 2174 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations)); 2175 priv->ctr = 0xc; 2176 priv->ctr_writable = ~0x10; 2177 priv->ecr = 0; 2178 priv->fifo_depth = 0; 2179 priv->dma_buf = NULL; 2180 priv->dma_handle = 0; 2181 priv->dev = dev; 2182 INIT_LIST_HEAD(&priv->list); 2183 priv->port = p; 2184 p->base_hi = base_hi; 2185 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2186 p->private_data = priv; 2187 2188 if (base_hi) { 2189 ECR_res = request_region(base_hi, 3, p->name); 2190 if (ECR_res) 2191 parport_ECR_present(p); 2192 } 2193 2194 if (base != 0x3bc) { 2195 EPP_res = request_region(base+0x3, 5, p->name); 2196 if (EPP_res) 2197 if (!parport_EPP_supported(p)) 2198 parport_ECPEPP_supported(p); 2199 } 2200 if (!parport_SPP_supported (p)) 2201 /* No port. */ 2202 goto out5; 2203 if (priv->ecr) 2204 parport_ECPPS2_supported(p); 2205 else 2206 parport_PS2_supported(p); 2207 2208 p->size = (p->modes & PARPORT_MODE_EPP)?8:3; 2209 2210 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); 2211 if (p->base_hi && priv->ecr) 2212 printk(" (0x%lx)", p->base_hi); 2213 if (p->irq == PARPORT_IRQ_AUTO) { 2214 p->irq = PARPORT_IRQ_NONE; 2215 parport_irq_probe(p); 2216 } else if (p->irq == PARPORT_IRQ_PROBEONLY) { 2217 p->irq = PARPORT_IRQ_NONE; 2218 parport_irq_probe(p); 2219 probedirq = p->irq; 2220 p->irq = PARPORT_IRQ_NONE; 2221 } 2222 if (p->irq != PARPORT_IRQ_NONE) { 2223 printk(", irq %d", p->irq); 2224 priv->ctr_writable |= 0x10; 2225 2226 if (p->dma == PARPORT_DMA_AUTO) { 2227 p->dma = PARPORT_DMA_NONE; 2228 parport_dma_probe(p); 2229 } 2230 } 2231 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq 2232 is mandatory (see above) */ 2233 p->dma = PARPORT_DMA_NONE; 2234 2235 #ifdef CONFIG_PARPORT_PC_FIFO 2236 if (parport_ECP_supported(p) && 2237 p->dma != PARPORT_DMA_NOFIFO && 2238 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { 2239 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; 2240 p->ops->compat_write_data = parport_pc_compat_write_block_pio; 2241 #ifdef CONFIG_PARPORT_1284 2242 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; 2243 /* currently broken, but working on it.. (FB) */ 2244 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ 2245 #endif /* IEEE 1284 support */ 2246 if (p->dma != PARPORT_DMA_NONE) { 2247 printk(", dma %d", p->dma); 2248 p->modes |= PARPORT_MODE_DMA; 2249 } 2250 else printk(", using FIFO"); 2251 } 2252 else 2253 /* We can't use the DMA channel after all. */ 2254 p->dma = PARPORT_DMA_NONE; 2255 #endif /* Allowed to use FIFO/DMA */ 2256 2257 printk(" ["); 2258 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}} 2259 { 2260 int f = 0; 2261 printmode(PCSPP); 2262 printmode(TRISTATE); 2263 printmode(COMPAT) 2264 printmode(EPP); 2265 printmode(ECP); 2266 printmode(DMA); 2267 } 2268 #undef printmode 2269 #ifndef CONFIG_PARPORT_1284 2270 printk ("(,...)"); 2271 #endif /* CONFIG_PARPORT_1284 */ 2272 printk("]\n"); 2273 if (probedirq != PARPORT_IRQ_NONE) 2274 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); 2275 2276 /* If No ECP release the ports grabbed above. */ 2277 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { 2278 release_region(base_hi, 3); 2279 ECR_res = NULL; 2280 } 2281 /* Likewise for EEP ports */ 2282 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { 2283 release_region(base+3, 5); 2284 EPP_res = NULL; 2285 } 2286 if (p->irq != PARPORT_IRQ_NONE) { 2287 if (request_irq (p->irq, parport_pc_interrupt, 2288 0, p->name, p)) { 2289 printk (KERN_WARNING "%s: irq %d in use, " 2290 "resorting to polled operation\n", 2291 p->name, p->irq); 2292 p->irq = PARPORT_IRQ_NONE; 2293 p->dma = PARPORT_DMA_NONE; 2294 } 2295 2296 #ifdef CONFIG_PARPORT_PC_FIFO 2297 #ifdef HAS_DMA 2298 if (p->dma != PARPORT_DMA_NONE) { 2299 if (request_dma (p->dma, p->name)) { 2300 printk (KERN_WARNING "%s: dma %d in use, " 2301 "resorting to PIO operation\n", 2302 p->name, p->dma); 2303 p->dma = PARPORT_DMA_NONE; 2304 } else { 2305 priv->dma_buf = 2306 pci_alloc_consistent(priv->dev, 2307 PAGE_SIZE, 2308 &priv->dma_handle); 2309 if (! priv->dma_buf) { 2310 printk (KERN_WARNING "%s: " 2311 "cannot get buffer for DMA, " 2312 "resorting to PIO operation\n", 2313 p->name); 2314 free_dma(p->dma); 2315 p->dma = PARPORT_DMA_NONE; 2316 } 2317 } 2318 } 2319 #endif 2320 #endif 2321 } 2322 2323 /* Done probing. Now put the port into a sensible start-up state. */ 2324 if (priv->ecr) 2325 /* 2326 * Put the ECP detected port in PS2 mode. 2327 * Do this also for ports that have ECR but don't do ECP. 2328 */ 2329 ECR_WRITE (p, 0x34); 2330 2331 parport_pc_write_data(p, 0); 2332 parport_pc_data_forward (p); 2333 2334 /* Now that we've told the sharing engine about the port, and 2335 found out its characteristics, let the high-level drivers 2336 know about it. */ 2337 spin_lock(&ports_lock); 2338 list_add(&priv->list, &ports_list); 2339 spin_unlock(&ports_lock); 2340 parport_announce_port (p); 2341 2342 return p; 2343 2344 out5: 2345 if (ECR_res) 2346 release_region(base_hi, 3); 2347 if (EPP_res) 2348 release_region(base+0x3, 5); 2349 release_region(base, 3); 2350 out4: 2351 parport_put_port(p); 2352 out3: 2353 kfree (priv); 2354 out2: 2355 kfree (ops); 2356 out1: 2357 return NULL; 2358 } 2359 2360 EXPORT_SYMBOL (parport_pc_probe_port); 2361 2362 void parport_pc_unregister_port (struct parport *p) 2363 { 2364 struct parport_pc_private *priv = p->private_data; 2365 struct parport_operations *ops = p->ops; 2366 2367 parport_remove_port(p); 2368 spin_lock(&ports_lock); 2369 list_del_init(&priv->list); 2370 spin_unlock(&ports_lock); 2371 if (p->dma != PARPORT_DMA_NONE) 2372 free_dma(p->dma); 2373 if (p->irq != PARPORT_IRQ_NONE) 2374 free_irq(p->irq, p); 2375 release_region(p->base, 3); 2376 if (p->size > 3) 2377 release_region(p->base + 3, p->size - 3); 2378 if (p->modes & PARPORT_MODE_ECP) 2379 release_region(p->base_hi, 3); 2380 #ifdef CONFIG_PARPORT_PC_FIFO 2381 #ifdef HAS_DMA 2382 if (priv->dma_buf) 2383 pci_free_consistent(priv->dev, PAGE_SIZE, 2384 priv->dma_buf, 2385 priv->dma_handle); 2386 #endif 2387 #endif 2388 kfree (p->private_data); 2389 parport_put_port(p); 2390 kfree (ops); /* hope no-one cached it */ 2391 } 2392 2393 EXPORT_SYMBOL (parport_pc_unregister_port); 2394 2395 #ifdef CONFIG_PCI 2396 2397 /* ITE support maintained by Rich Liu <richliu@poorman.org> */ 2398 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq, 2399 int autodma, struct parport_pc_via_data *via) 2400 { 2401 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; 2402 struct resource *base_res; 2403 u32 ite8872set; 2404 u32 ite8872_lpt, ite8872_lpthi; 2405 u8 ite8872_irq, type; 2406 char *fake_name = "parport probe"; 2407 int irq; 2408 int i; 2409 2410 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n"); 2411 2412 // make sure which one chip 2413 for(i = 0; i < 5; i++) { 2414 base_res = request_region(inta_addr[i], 0x8, fake_name); 2415 if (base_res) { 2416 int test; 2417 pci_write_config_dword (pdev, 0x60, 2418 0xe7000000 | inta_addr[i]); 2419 pci_write_config_dword (pdev, 0x78, 2420 0x00000000 | inta_addr[i]); 2421 test = inb (inta_addr[i]); 2422 if (test != 0xff) break; 2423 release_region(inta_addr[i], 0x8); 2424 } 2425 } 2426 if(i >= 5) { 2427 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); 2428 return 0; 2429 } 2430 2431 type = inb (inta_addr[i] + 0x18); 2432 type &= 0x0f; 2433 2434 switch (type) { 2435 case 0x2: 2436 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n"); 2437 ite8872set = 0x64200000; 2438 break; 2439 case 0xa: 2440 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n"); 2441 ite8872set = 0x64200000; 2442 break; 2443 case 0xe: 2444 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); 2445 ite8872set = 0x64e00000; 2446 break; 2447 case 0x6: 2448 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n"); 2449 return 0; 2450 case 0x8: 2451 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); 2452 return 0; 2453 default: 2454 printk (KERN_INFO "parport_pc: unknown ITE887x\n"); 2455 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' " 2456 "output to Rich.Liu@ite.com.tw\n"); 2457 return 0; 2458 } 2459 2460 pci_read_config_byte (pdev, 0x3c, &ite8872_irq); 2461 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt); 2462 ite8872_lpt &= 0x0000ff00; 2463 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi); 2464 ite8872_lpthi &= 0x0000ff00; 2465 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt); 2466 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi); 2467 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); 2468 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function 2469 // SET Parallel IRQ 2470 pci_write_config_dword (pdev, 0x9c, 2471 ite8872set | (ite8872_irq * 0x11111)); 2472 2473 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); 2474 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", 2475 ite8872_lpt); 2476 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", 2477 ite8872_lpthi); 2478 2479 /* Let the user (or defaults) steer us away from interrupts */ 2480 irq = ite8872_irq; 2481 if (autoirq != PARPORT_IRQ_AUTO) 2482 irq = PARPORT_IRQ_NONE; 2483 2484 /* 2485 * Release the resource so that parport_pc_probe_port can get it. 2486 */ 2487 release_resource(base_res); 2488 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi, 2489 irq, PARPORT_DMA_NONE, NULL)) { 2490 printk (KERN_INFO 2491 "parport_pc: ITE 8872 parallel port: io=0x%X", 2492 ite8872_lpt); 2493 if (irq != PARPORT_IRQ_NONE) 2494 printk (", irq=%d", irq); 2495 printk ("\n"); 2496 return 1; 2497 } 2498 2499 return 0; 2500 } 2501 2502 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> 2503 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ 2504 static int __devinitdata parport_init_mode = 0; 2505 2506 /* Data for two known VIA chips */ 2507 static struct parport_pc_via_data via_686a_data __devinitdata = { 2508 0x51, 2509 0x50, 2510 0x85, 2511 0x02, 2512 0xE2, 2513 0xF0, 2514 0xE6 2515 }; 2516 static struct parport_pc_via_data via_8231_data __devinitdata = { 2517 0x45, 2518 0x44, 2519 0x50, 2520 0x04, 2521 0xF2, 2522 0xFA, 2523 0xF6 2524 }; 2525 2526 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq, 2527 int autodma, struct parport_pc_via_data *via) 2528 { 2529 u8 tmp, tmp2, siofunc; 2530 u8 ppcontrol = 0; 2531 int dma, irq; 2532 unsigned port1, port2; 2533 unsigned have_epp = 0; 2534 2535 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); 2536 2537 switch(parport_init_mode) 2538 { 2539 case 1: 2540 printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); 2541 siofunc = VIA_FUNCTION_PARPORT_SPP; 2542 break; 2543 case 2: 2544 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); 2545 siofunc = VIA_FUNCTION_PARPORT_SPP; 2546 ppcontrol = VIA_PARPORT_BIDIR; 2547 break; 2548 case 3: 2549 printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); 2550 siofunc = VIA_FUNCTION_PARPORT_EPP; 2551 ppcontrol = VIA_PARPORT_BIDIR; 2552 have_epp = 1; 2553 break; 2554 case 4: 2555 printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); 2556 siofunc = VIA_FUNCTION_PARPORT_ECP; 2557 ppcontrol = VIA_PARPORT_BIDIR; 2558 break; 2559 case 5: 2560 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); 2561 siofunc = VIA_FUNCTION_PARPORT_ECP; 2562 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; 2563 have_epp = 1; 2564 break; 2565 default: 2566 printk(KERN_DEBUG "parport_pc: probing current configuration\n"); 2567 siofunc = VIA_FUNCTION_PROBE; 2568 break; 2569 } 2570 /* 2571 * unlock super i/o configuration 2572 */ 2573 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2574 tmp |= via->via_pci_superio_config_data; 2575 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2576 2577 /* Bits 1-0: Parallel Port Mode / Enable */ 2578 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2579 tmp = inb (VIA_CONFIG_DATA); 2580 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ 2581 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2582 tmp2 = inb (VIA_CONFIG_DATA); 2583 if (siofunc == VIA_FUNCTION_PROBE) 2584 { 2585 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; 2586 ppcontrol = tmp2; 2587 } 2588 else 2589 { 2590 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; 2591 tmp |= siofunc; 2592 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2593 outb(tmp, VIA_CONFIG_DATA); 2594 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); 2595 tmp2 |= ppcontrol; 2596 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2597 outb(tmp2, VIA_CONFIG_DATA); 2598 } 2599 2600 /* Parallel Port I/O Base Address, bits 9-2 */ 2601 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2602 port1 = inb(VIA_CONFIG_DATA) << 2; 2603 2604 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1); 2605 if ((port1 == 0x3BC) && have_epp) 2606 { 2607 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2608 outb((0x378 >> 2), VIA_CONFIG_DATA); 2609 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); 2610 port1 = 0x378; 2611 } 2612 2613 /* 2614 * lock super i/o configuration 2615 */ 2616 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2617 tmp &= ~via->via_pci_superio_config_data; 2618 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2619 2620 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { 2621 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); 2622 return 0; 2623 } 2624 2625 /* Bits 7-4: PnP Routing for Parallel Port IRQ */ 2626 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); 2627 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); 2628 2629 if (siofunc == VIA_FUNCTION_PARPORT_ECP) 2630 { 2631 /* Bits 3-2: PnP Routing for Parallel Port DMA */ 2632 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); 2633 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); 2634 } 2635 else 2636 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */ 2637 dma = PARPORT_DMA_NONE; 2638 2639 /* Let the user (or defaults) steer us away from interrupts and DMA */ 2640 if (autoirq == PARPORT_IRQ_NONE) { 2641 irq = PARPORT_IRQ_NONE; 2642 dma = PARPORT_DMA_NONE; 2643 } 2644 if (autodma == PARPORT_DMA_NONE) 2645 dma = PARPORT_DMA_NONE; 2646 2647 switch (port1) { 2648 case 0x3bc: port2 = 0x7bc; break; 2649 case 0x378: port2 = 0x778; break; 2650 case 0x278: port2 = 0x678; break; 2651 default: 2652 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n", 2653 port1); 2654 return 0; 2655 } 2656 2657 /* filter bogus IRQs */ 2658 switch (irq) { 2659 case 0: 2660 case 2: 2661 case 8: 2662 case 13: 2663 irq = PARPORT_IRQ_NONE; 2664 break; 2665 2666 default: /* do nothing */ 2667 break; 2668 } 2669 2670 /* finally, do the probe with values obtained */ 2671 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) { 2672 printk (KERN_INFO 2673 "parport_pc: VIA parallel port: io=0x%X", port1); 2674 if (irq != PARPORT_IRQ_NONE) 2675 printk (", irq=%d", irq); 2676 if (dma != PARPORT_DMA_NONE) 2677 printk (", dma=%d", dma); 2678 printk ("\n"); 2679 return 1; 2680 } 2681 2682 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", 2683 port1, irq, dma); 2684 return 0; 2685 } 2686 2687 2688 enum parport_pc_sio_types { 2689 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ 2690 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ 2691 sio_ite_8872, 2692 last_sio 2693 }; 2694 2695 /* each element directly indexed from enum list, above */ 2696 static struct parport_pc_superio { 2697 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, struct parport_pc_via_data *via); 2698 struct parport_pc_via_data *via; 2699 } parport_pc_superio_info[] __devinitdata = { 2700 { sio_via_probe, &via_686a_data, }, 2701 { sio_via_probe, &via_8231_data, }, 2702 { sio_ite_8872_probe, NULL, }, 2703 }; 2704 2705 enum parport_pc_pci_cards { 2706 siig_1p_10x = last_sio, 2707 siig_2p_10x, 2708 siig_1p_20x, 2709 siig_2p_20x, 2710 lava_parallel, 2711 lava_parallel_dual_a, 2712 lava_parallel_dual_b, 2713 boca_ioppar, 2714 plx_9050, 2715 timedia_4078a, 2716 timedia_4079h, 2717 timedia_4085h, 2718 timedia_4088a, 2719 timedia_4089a, 2720 timedia_4095a, 2721 timedia_4096a, 2722 timedia_4078u, 2723 timedia_4079a, 2724 timedia_4085u, 2725 timedia_4079r, 2726 timedia_4079s, 2727 timedia_4079d, 2728 timedia_4079e, 2729 timedia_4079f, 2730 timedia_9079a, 2731 timedia_9079b, 2732 timedia_9079c, 2733 timedia_4006a, 2734 timedia_4014, 2735 timedia_4008a, 2736 timedia_4018, 2737 timedia_9018a, 2738 syba_2p_epp, 2739 syba_1p_ecp, 2740 titan_010l, 2741 titan_1284p1, 2742 titan_1284p2, 2743 avlab_1p, 2744 avlab_2p, 2745 oxsemi_954, 2746 oxsemi_840, 2747 aks_0100, 2748 mobility_pp, 2749 netmos_9705, 2750 netmos_9715, 2751 netmos_9755, 2752 netmos_9805, 2753 netmos_9815, 2754 }; 2755 2756 2757 /* each element directly indexed from enum list, above 2758 * (but offset by last_sio) */ 2759 static struct parport_pc_pci { 2760 int numports; 2761 struct { /* BAR (base address registers) numbers in the config 2762 space header */ 2763 int lo; 2764 int hi; /* -1 if not there, >6 for offset-method (max 2765 BAR is 6) */ 2766 } addr[4]; 2767 2768 /* If set, this is called immediately after pci_enable_device. 2769 * If it returns non-zero, no probing will take place and the 2770 * ports will not be used. */ 2771 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); 2772 2773 /* If set, this is called after probing for ports. If 'failed' 2774 * is non-zero we couldn't use any of the ports. */ 2775 void (*postinit_hook) (struct pci_dev *pdev, int failed); 2776 } cards[] __devinitdata = { 2777 /* siig_1p_10x */ { 1, { { 2, 3 }, } }, 2778 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2779 /* siig_1p_20x */ { 1, { { 0, 1 }, } }, 2780 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2781 /* lava_parallel */ { 1, { { 0, -1 }, } }, 2782 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, 2783 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, 2784 /* boca_ioppar */ { 1, { { 0, -1 }, } }, 2785 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, 2786 /* timedia_4078a */ { 1, { { 2, -1 }, } }, 2787 /* timedia_4079h */ { 1, { { 2, 3 }, } }, 2788 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2789 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2790 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2791 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2792 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2793 /* timedia_4078u */ { 1, { { 2, -1 }, } }, 2794 /* timedia_4079a */ { 1, { { 2, 3 }, } }, 2795 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2796 /* timedia_4079r */ { 1, { { 2, 3 }, } }, 2797 /* timedia_4079s */ { 1, { { 2, 3 }, } }, 2798 /* timedia_4079d */ { 1, { { 2, 3 }, } }, 2799 /* timedia_4079e */ { 1, { { 2, 3 }, } }, 2800 /* timedia_4079f */ { 1, { { 2, 3 }, } }, 2801 /* timedia_9079a */ { 1, { { 2, 3 }, } }, 2802 /* timedia_9079b */ { 1, { { 2, 3 }, } }, 2803 /* timedia_9079c */ { 1, { { 2, 3 }, } }, 2804 /* timedia_4006a */ { 1, { { 0, -1 }, } }, 2805 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, 2806 /* timedia_4008a */ { 1, { { 0, 1 }, } }, 2807 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2808 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2809 /* SYBA uses fixed offsets in 2810 a 1K io window */ 2811 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, 2812 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, 2813 /* titan_010l */ { 1, { { 3, -1 }, } }, 2814 /* titan_1284p1 */ { 1, { { 0, 1 }, } }, 2815 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2816 /* avlab_1p */ { 1, { { 0, 1}, } }, 2817 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, 2818 /* The Oxford Semi cards are unusual: 954 doesn't support ECP, 2819 * and 840 locks up if you write 1 to bit 2! */ 2820 /* oxsemi_954 */ { 1, { { 0, -1 }, } }, 2821 /* oxsemi_840 */ { 1, { { 0, -1 }, } }, 2822 /* aks_0100 */ { 1, { { 0, -1 }, } }, 2823 /* mobility_pp */ { 1, { { 0, 1 }, } }, 2824 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */ 2825 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2826 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2827 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */ 2828 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */ 2829 }; 2830 2831 static struct pci_device_id parport_pc_pci_tbl[] = { 2832 /* Super-IO onboard chips */ 2833 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, 2834 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, 2835 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, 2837 2838 /* PCI cards */ 2839 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, 2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, 2841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, 2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, 2843 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, 2844 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, 2845 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, 2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, 2847 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, 2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, 2849 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, 2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, 2851 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, 2852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, 2853 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, 2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, 2855 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2856 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 }, 2857 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ 2858 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, 2859 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, 2860 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, 2861 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, 2862 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, 2863 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, 2864 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, 2865 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, 2866 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, 2867 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, 2868 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, 2869 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, 2870 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, 2871 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, 2872 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, 2873 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, 2874 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, 2875 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, 2876 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, 2877 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, 2878 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, 2879 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, 2880 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, 2881 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, 2882 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, 2883 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, 2884 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, 2885 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, 2886 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, 2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, 2888 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, 2889 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, 2890 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ 2891 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */ 2892 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, 2893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, 2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, 2895 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, 2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, 2897 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, 2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, 2899 /* NetMos communication controllers */ 2900 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, 2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, 2902 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, 2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, 2904 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, 2905 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, 2906 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, 2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, 2908 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, 2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, 2910 { 0, } /* terminate list */ 2911 }; 2912 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl); 2913 2914 struct pci_parport_data { 2915 int num; 2916 struct parport *ports[2]; 2917 }; 2918 2919 static int parport_pc_pci_probe (struct pci_dev *dev, 2920 const struct pci_device_id *id) 2921 { 2922 int err, count, n, i = id->driver_data; 2923 struct pci_parport_data *data; 2924 2925 if (i < last_sio) 2926 /* This is an onboard Super-IO and has already been probed */ 2927 return 0; 2928 2929 /* This is a PCI card */ 2930 i -= last_sio; 2931 count = 0; 2932 if ((err = pci_enable_device (dev)) != 0) 2933 return err; 2934 2935 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); 2936 if (!data) 2937 return -ENOMEM; 2938 2939 if (cards[i].preinit_hook && 2940 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { 2941 kfree(data); 2942 return -ENODEV; 2943 } 2944 2945 for (n = 0; n < cards[i].numports; n++) { 2946 int lo = cards[i].addr[n].lo; 2947 int hi = cards[i].addr[n].hi; 2948 unsigned long io_lo, io_hi; 2949 io_lo = pci_resource_start (dev, lo); 2950 io_hi = 0; 2951 if ((hi >= 0) && (hi <= 6)) 2952 io_hi = pci_resource_start (dev, hi); 2953 else if (hi > 6) 2954 io_lo += hi; /* Reinterpret the meaning of 2955 "hi" as an offset (see SYBA 2956 def.) */ 2957 /* TODO: test if sharing interrupts works */ 2958 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, " 2959 "I/O at %#lx(%#lx)\n", 2960 parport_pc_pci_tbl[i + last_sio].vendor, 2961 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi); 2962 data->ports[count] = 2963 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE, 2964 PARPORT_DMA_NONE, dev); 2965 if (data->ports[count]) 2966 count++; 2967 } 2968 2969 data->num = count; 2970 2971 if (cards[i].postinit_hook) 2972 cards[i].postinit_hook (dev, count == 0); 2973 2974 if (count) { 2975 pci_set_drvdata(dev, data); 2976 return 0; 2977 } 2978 2979 kfree(data); 2980 2981 return -ENODEV; 2982 } 2983 2984 static void __devexit parport_pc_pci_remove(struct pci_dev *dev) 2985 { 2986 struct pci_parport_data *data = pci_get_drvdata(dev); 2987 int i; 2988 2989 pci_set_drvdata(dev, NULL); 2990 2991 if (data) { 2992 for (i = data->num - 1; i >= 0; i--) 2993 parport_pc_unregister_port(data->ports[i]); 2994 2995 kfree(data); 2996 } 2997 } 2998 2999 static struct pci_driver parport_pc_pci_driver = { 3000 .name = "parport_pc", 3001 .id_table = parport_pc_pci_tbl, 3002 .probe = parport_pc_pci_probe, 3003 .remove = __devexit_p(parport_pc_pci_remove), 3004 }; 3005 3006 static int __init parport_pc_init_superio (int autoirq, int autodma) 3007 { 3008 const struct pci_device_id *id; 3009 struct pci_dev *pdev = NULL; 3010 int ret = 0; 3011 3012 for_each_pci_dev(pdev) { 3013 id = pci_match_id(parport_pc_pci_tbl, pdev); 3014 if (id == NULL || id->driver_data >= last_sio) 3015 continue; 3016 3017 if (parport_pc_superio_info[id->driver_data].probe 3018 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) { 3019 ret++; 3020 } 3021 } 3022 3023 return ret; /* number of devices found */ 3024 } 3025 #else 3026 static struct pci_driver parport_pc_pci_driver; 3027 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;} 3028 #endif /* CONFIG_PCI */ 3029 3030 3031 static const struct pnp_device_id parport_pc_pnp_tbl[] = { 3032 /* Standard LPT Printer Port */ 3033 {.id = "PNP0400", .driver_data = 0}, 3034 /* ECP Printer Port */ 3035 {.id = "PNP0401", .driver_data = 0}, 3036 { } 3037 }; 3038 3039 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl); 3040 3041 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) 3042 { 3043 struct parport *pdata; 3044 unsigned long io_lo, io_hi; 3045 int dma, irq; 3046 3047 if (pnp_port_valid(dev,0) && 3048 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) { 3049 io_lo = pnp_port_start(dev,0); 3050 } else 3051 return -EINVAL; 3052 3053 if (pnp_port_valid(dev,1) && 3054 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) { 3055 io_hi = pnp_port_start(dev,1); 3056 } else 3057 io_hi = 0; 3058 3059 if (pnp_irq_valid(dev,0) && 3060 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) { 3061 irq = pnp_irq(dev,0); 3062 } else 3063 irq = PARPORT_IRQ_NONE; 3064 3065 if (pnp_dma_valid(dev,0) && 3066 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) { 3067 dma = pnp_dma(dev,0); 3068 } else 3069 dma = PARPORT_DMA_NONE; 3070 3071 printk(KERN_INFO "parport: PnPBIOS parport detected.\n"); 3072 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL))) 3073 return -ENODEV; 3074 3075 pnp_set_drvdata(dev,pdata); 3076 return 0; 3077 } 3078 3079 static void parport_pc_pnp_remove(struct pnp_dev *dev) 3080 { 3081 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); 3082 if (!pdata) 3083 return; 3084 3085 parport_pc_unregister_port(pdata); 3086 } 3087 3088 /* we only need the pnp layer to activate the device, at least for now */ 3089 static struct pnp_driver parport_pc_pnp_driver = { 3090 .name = "parport_pc", 3091 .id_table = parport_pc_pnp_tbl, 3092 .probe = parport_pc_pnp_probe, 3093 .remove = parport_pc_pnp_remove, 3094 }; 3095 3096 3097 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ 3098 static int __devinit __attribute__((unused)) 3099 parport_pc_find_isa_ports (int autoirq, int autodma) 3100 { 3101 int count = 0; 3102 3103 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL)) 3104 count++; 3105 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL)) 3106 count++; 3107 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL)) 3108 count++; 3109 3110 return count; 3111 } 3112 3113 /* This function is called by parport_pc_init if the user didn't 3114 * specify any ports to probe. Its job is to find some ports. Order 3115 * is important here -- we want ISA ports to be registered first, 3116 * followed by PCI cards (for least surprise), but before that we want 3117 * to do chipset-specific tests for some onboard ports that we know 3118 * about. 3119 * 3120 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY 3121 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO 3122 */ 3123 static int __init parport_pc_find_ports (int autoirq, int autodma) 3124 { 3125 int count = 0, r; 3126 3127 #ifdef CONFIG_PARPORT_PC_SUPERIO 3128 detect_and_report_winbond (); 3129 detect_and_report_smsc (); 3130 #endif 3131 3132 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ 3133 count += parport_pc_init_superio (autoirq, autodma); 3134 3135 /* PnP ports, skip detection if SuperIO already found them */ 3136 if (!count) { 3137 r = pnp_register_driver (&parport_pc_pnp_driver); 3138 if (r >= 0) { 3139 pnp_registered_parport = 1; 3140 count += r; 3141 } 3142 } 3143 3144 /* ISA ports and whatever (see asm/parport.h). */ 3145 count += parport_pc_find_nonpci_ports (autoirq, autodma); 3146 3147 r = pci_register_driver (&parport_pc_pci_driver); 3148 if (r) 3149 return r; 3150 pci_registered_parport = 1; 3151 count += 1; 3152 3153 return count; 3154 } 3155 3156 /* 3157 * Piles of crap below pretend to be a parser for module and kernel 3158 * parameters. Say "thank you" to whoever had come up with that 3159 * syntax and keep in mind that code below is a cleaned up version. 3160 */ 3161 3162 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 }; 3163 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = 3164 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO }; 3165 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE }; 3166 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY }; 3167 3168 static int __init parport_parse_param(const char *s, int *val, 3169 int automatic, int none, int nofifo) 3170 { 3171 if (!s) 3172 return 0; 3173 if (!strncmp(s, "auto", 4)) 3174 *val = automatic; 3175 else if (!strncmp(s, "none", 4)) 3176 *val = none; 3177 else if (nofifo && !strncmp(s, "nofifo", 4)) 3178 *val = nofifo; 3179 else { 3180 char *ep; 3181 unsigned long r = simple_strtoul(s, &ep, 0); 3182 if (ep != s) 3183 *val = r; 3184 else { 3185 printk(KERN_ERR "parport: bad specifier `%s'\n", s); 3186 return -1; 3187 } 3188 } 3189 return 0; 3190 } 3191 3192 static int __init parport_parse_irq(const char *irqstr, int *val) 3193 { 3194 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, 3195 PARPORT_IRQ_NONE, 0); 3196 } 3197 3198 static int __init parport_parse_dma(const char *dmastr, int *val) 3199 { 3200 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, 3201 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); 3202 } 3203 3204 #ifdef CONFIG_PCI 3205 static int __init parport_init_mode_setup(char *str) 3206 { 3207 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); 3208 3209 if (!strcmp (str, "spp")) 3210 parport_init_mode=1; 3211 if (!strcmp (str, "ps2")) 3212 parport_init_mode=2; 3213 if (!strcmp (str, "epp")) 3214 parport_init_mode=3; 3215 if (!strcmp (str, "ecp")) 3216 parport_init_mode=4; 3217 if (!strcmp (str, "ecpepp")) 3218 parport_init_mode=5; 3219 return 1; 3220 } 3221 #endif 3222 3223 #ifdef MODULE 3224 static const char *irq[PARPORT_PC_MAX_PORTS]; 3225 static const char *dma[PARPORT_PC_MAX_PORTS]; 3226 3227 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); 3228 module_param_array(io, int, NULL, 0); 3229 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); 3230 module_param_array(io_hi, int, NULL, 0); 3231 MODULE_PARM_DESC(irq, "IRQ line"); 3232 module_param_array(irq, charp, NULL, 0); 3233 MODULE_PARM_DESC(dma, "DMA channel"); 3234 module_param_array(dma, charp, NULL, 0); 3235 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 3236 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 3237 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); 3238 module_param(verbose_probing, int, 0644); 3239 #endif 3240 #ifdef CONFIG_PCI 3241 static char *init_mode; 3242 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); 3243 module_param(init_mode, charp, 0); 3244 #endif 3245 3246 static int __init parse_parport_params(void) 3247 { 3248 unsigned int i; 3249 int val; 3250 3251 #ifdef CONFIG_PCI 3252 if (init_mode) 3253 parport_init_mode_setup(init_mode); 3254 #endif 3255 3256 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { 3257 if (parport_parse_irq(irq[i], &val)) 3258 return 1; 3259 irqval[i] = val; 3260 if (parport_parse_dma(dma[i], &val)) 3261 return 1; 3262 dmaval[i] = val; 3263 } 3264 if (!io[0]) { 3265 /* The user can make us use any IRQs or DMAs we find. */ 3266 if (irq[0] && !parport_parse_irq(irq[0], &val)) 3267 switch (val) { 3268 case PARPORT_IRQ_NONE: 3269 case PARPORT_IRQ_AUTO: 3270 irqval[0] = val; 3271 break; 3272 default: 3273 printk (KERN_WARNING 3274 "parport_pc: irq specified " 3275 "without base address. Use 'io=' " 3276 "to specify one\n"); 3277 } 3278 3279 if (dma[0] && !parport_parse_dma(dma[0], &val)) 3280 switch (val) { 3281 case PARPORT_DMA_NONE: 3282 case PARPORT_DMA_AUTO: 3283 dmaval[0] = val; 3284 break; 3285 default: 3286 printk (KERN_WARNING 3287 "parport_pc: dma specified " 3288 "without base address. Use 'io=' " 3289 "to specify one\n"); 3290 } 3291 } 3292 return 0; 3293 } 3294 3295 #else 3296 3297 static int parport_setup_ptr __initdata = 0; 3298 3299 /* 3300 * Acceptable parameters: 3301 * 3302 * parport=0 3303 * parport=auto 3304 * parport=0xBASE[,IRQ[,DMA]] 3305 * 3306 * IRQ/DMA may be numeric or 'auto' or 'none' 3307 */ 3308 static int __init parport_setup (char *str) 3309 { 3310 char *endptr; 3311 char *sep; 3312 int val; 3313 3314 if (!str || !*str || (*str == '0' && !*(str+1))) { 3315 /* Disable parport if "parport=0" in cmdline */ 3316 io[0] = PARPORT_DISABLE; 3317 return 1; 3318 } 3319 3320 if (!strncmp (str, "auto", 4)) { 3321 irqval[0] = PARPORT_IRQ_AUTO; 3322 dmaval[0] = PARPORT_DMA_AUTO; 3323 return 1; 3324 } 3325 3326 val = simple_strtoul (str, &endptr, 0); 3327 if (endptr == str) { 3328 printk (KERN_WARNING "parport=%s not understood\n", str); 3329 return 1; 3330 } 3331 3332 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { 3333 printk(KERN_ERR "parport=%s ignored, too many ports\n", str); 3334 return 1; 3335 } 3336 3337 io[parport_setup_ptr] = val; 3338 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; 3339 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; 3340 3341 sep = strchr(str, ','); 3342 if (sep++) { 3343 if (parport_parse_irq(sep, &val)) 3344 return 1; 3345 irqval[parport_setup_ptr] = val; 3346 sep = strchr(sep, ','); 3347 if (sep++) { 3348 if (parport_parse_dma(sep, &val)) 3349 return 1; 3350 dmaval[parport_setup_ptr] = val; 3351 } 3352 } 3353 parport_setup_ptr++; 3354 return 1; 3355 } 3356 3357 static int __init parse_parport_params(void) 3358 { 3359 return io[0] == PARPORT_DISABLE; 3360 } 3361 3362 __setup ("parport=", parport_setup); 3363 3364 /* 3365 * Acceptable parameters: 3366 * 3367 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] 3368 */ 3369 #ifdef CONFIG_PCI 3370 __setup("parport_init_mode=",parport_init_mode_setup); 3371 #endif 3372 #endif 3373 3374 /* "Parser" ends here */ 3375 3376 static int __init parport_pc_init(void) 3377 { 3378 int count = 0; 3379 3380 if (parse_parport_params()) 3381 return -EINVAL; 3382 3383 if (io[0]) { 3384 int i; 3385 /* Only probe the ports we were given. */ 3386 user_specified = 1; 3387 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { 3388 if (!io[i]) 3389 break; 3390 if ((io_hi[i]) == PARPORT_IOHI_AUTO) 3391 io_hi[i] = 0x400 + io[i]; 3392 if (parport_pc_probe_port(io[i], io_hi[i], 3393 irqval[i], dmaval[i], NULL)) 3394 count++; 3395 } 3396 } else 3397 count += parport_pc_find_ports (irqval[0], dmaval[0]); 3398 3399 return 0; 3400 } 3401 3402 static void __exit parport_pc_exit(void) 3403 { 3404 if (pci_registered_parport) 3405 pci_unregister_driver (&parport_pc_pci_driver); 3406 if (pnp_registered_parport) 3407 pnp_unregister_driver (&parport_pc_pnp_driver); 3408 3409 spin_lock(&ports_lock); 3410 while (!list_empty(&ports_list)) { 3411 struct parport_pc_private *priv; 3412 struct parport *port; 3413 priv = list_entry(ports_list.next, 3414 struct parport_pc_private, list); 3415 port = priv->port; 3416 spin_unlock(&ports_lock); 3417 parport_pc_unregister_port(port); 3418 spin_lock(&ports_lock); 3419 } 3420 spin_unlock(&ports_lock); 3421 } 3422 3423 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); 3424 MODULE_DESCRIPTION("PC-style parallel port driver"); 3425 MODULE_LICENSE("GPL"); 3426 module_init(parport_pc_init) 3427 module_exit(parport_pc_exit) 3428