1 /* Low-level parallel-port routines for 8255-based PC-style hardware. 2 * 3 * Authors: Phil Blundell <philb@gnu.org> 4 * Tim Waugh <tim@cyberelk.demon.co.uk> 5 * Jose Renau <renau@acm.org> 6 * David Campbell 7 * Andrea Arcangeli 8 * 9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. 10 * 11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org> 12 * DMA support - Bert De Jonghe <bert@sophis.be> 13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. 15 * Various hacks, Fred Barnes, 04/2001 16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com> 17 */ 18 19 /* This driver should work with any hardware that is broadly compatible 20 * with that in the IBM PC. This applies to the majority of integrated 21 * I/O chipsets that are commonly available. The expected register 22 * layout is: 23 * 24 * base+0 data 25 * base+1 status 26 * base+2 control 27 * 28 * In addition, there are some optional registers: 29 * 30 * base+3 EPP address 31 * base+4 EPP data 32 * base+0x400 ECP config A 33 * base+0x401 ECP config B 34 * base+0x402 ECP control 35 * 36 * All registers are 8 bits wide and read/write. If your hardware differs 37 * only in register addresses (eg because your registers are on 32-bit 38 * word boundaries) then you can alter the constants in parport_pc.h to 39 * accommodate this. 40 * 41 * Note that the ECP registers may not start at offset 0x400 for PCI cards, 42 * but rather will start at port->base_hi. 43 */ 44 45 #include <linux/module.h> 46 #include <linux/init.h> 47 #include <linux/sched.h> 48 #include <linux/delay.h> 49 #include <linux/errno.h> 50 #include <linux/interrupt.h> 51 #include <linux/ioport.h> 52 #include <linux/kernel.h> 53 #include <linux/slab.h> 54 #include <linux/pci.h> 55 #include <linux/pnp.h> 56 #include <linux/sysctl.h> 57 58 #include <asm/io.h> 59 #include <asm/dma.h> 60 #include <asm/uaccess.h> 61 62 #include <linux/parport.h> 63 #include <linux/parport_pc.h> 64 #include <linux/via.h> 65 #include <asm/parport.h> 66 67 #define PARPORT_PC_MAX_PORTS PARPORT_MAX 68 69 #ifdef CONFIG_ISA_DMA_API 70 #define HAS_DMA 71 #endif 72 73 /* ECR modes */ 74 #define ECR_SPP 00 75 #define ECR_PS2 01 76 #define ECR_PPF 02 77 #define ECR_ECP 03 78 #define ECR_EPP 04 79 #define ECR_VND 05 80 #define ECR_TST 06 81 #define ECR_CNF 07 82 #define ECR_MODE_MASK 0xe0 83 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v)) 84 85 #undef DEBUG 86 87 #ifdef DEBUG 88 #define DPRINTK printk 89 #else 90 #define DPRINTK(stuff...) 91 #endif 92 93 94 #define NR_SUPERIOS 3 95 static struct superio_struct { /* For Super-IO chips autodetection */ 96 int io; 97 int irq; 98 int dma; 99 } superios[NR_SUPERIOS] = { {0,},}; 100 101 static int user_specified; 102 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 103 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 104 static int verbose_probing; 105 #endif 106 static int pci_registered_parport; 107 static int pnp_registered_parport; 108 109 /* frob_control, but for ECR */ 110 static void frob_econtrol (struct parport *pb, unsigned char m, 111 unsigned char v) 112 { 113 unsigned char ectr = 0; 114 115 if (m != 0xff) 116 ectr = inb (ECONTROL (pb)); 117 118 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", 119 m, v, ectr, (ectr & ~m) ^ v); 120 121 outb ((ectr & ~m) ^ v, ECONTROL (pb)); 122 } 123 124 static __inline__ void frob_set_mode (struct parport *p, int mode) 125 { 126 frob_econtrol (p, ECR_MODE_MASK, mode << 5); 127 } 128 129 #ifdef CONFIG_PARPORT_PC_FIFO 130 /* Safely change the mode bits in the ECR 131 Returns: 132 0 : Success 133 -EBUSY: Could not drain FIFO in some finite amount of time, 134 mode not changed! 135 */ 136 static int change_mode(struct parport *p, int m) 137 { 138 const struct parport_pc_private *priv = p->physport->private_data; 139 unsigned char oecr; 140 int mode; 141 142 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m); 143 144 if (!priv->ecr) { 145 printk (KERN_DEBUG "change_mode: but there's no ECR!\n"); 146 return 0; 147 } 148 149 /* Bits <7:5> contain the mode. */ 150 oecr = inb (ECONTROL (p)); 151 mode = (oecr >> 5) & 0x7; 152 if (mode == m) return 0; 153 154 if (mode >= 2 && !(priv->ctr & 0x20)) { 155 /* This mode resets the FIFO, so we may 156 * have to wait for it to drain first. */ 157 unsigned long expire = jiffies + p->physport->cad->timeout; 158 int counter; 159 switch (mode) { 160 case ECR_PPF: /* Parallel Port FIFO mode */ 161 case ECR_ECP: /* ECP Parallel Port mode */ 162 /* Busy wait for 200us */ 163 for (counter = 0; counter < 40; counter++) { 164 if (inb (ECONTROL (p)) & 0x01) 165 break; 166 if (signal_pending (current)) break; 167 udelay (5); 168 } 169 170 /* Poll slowly. */ 171 while (!(inb (ECONTROL (p)) & 0x01)) { 172 if (time_after_eq (jiffies, expire)) 173 /* The FIFO is stuck. */ 174 return -EBUSY; 175 schedule_timeout_interruptible(msecs_to_jiffies(10)); 176 if (signal_pending (current)) 177 break; 178 } 179 } 180 } 181 182 if (mode >= 2 && m >= 2) { 183 /* We have to go through mode 001 */ 184 oecr &= ~(7 << 5); 185 oecr |= ECR_PS2 << 5; 186 ECR_WRITE (p, oecr); 187 } 188 189 /* Set the mode. */ 190 oecr &= ~(7 << 5); 191 oecr |= m << 5; 192 ECR_WRITE (p, oecr); 193 return 0; 194 } 195 196 #ifdef CONFIG_PARPORT_1284 197 /* Find FIFO lossage; FIFO is reset */ 198 #if 0 199 static int get_fifo_residue (struct parport *p) 200 { 201 int residue; 202 int cnfga; 203 const struct parport_pc_private *priv = p->physport->private_data; 204 205 /* Adjust for the contents of the FIFO. */ 206 for (residue = priv->fifo_depth; ; residue--) { 207 if (inb (ECONTROL (p)) & 0x2) 208 /* Full up. */ 209 break; 210 211 outb (0, FIFO (p)); 212 } 213 214 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, 215 residue); 216 217 /* Reset the FIFO. */ 218 frob_set_mode (p, ECR_PS2); 219 220 /* Now change to config mode and clean up. FIXME */ 221 frob_set_mode (p, ECR_CNF); 222 cnfga = inb (CONFIGA (p)); 223 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); 224 225 if (!(cnfga & (1<<2))) { 226 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name); 227 residue++; 228 } 229 230 /* Don't care about partial PWords until support is added for 231 * PWord != 1 byte. */ 232 233 /* Back to PS2 mode. */ 234 frob_set_mode (p, ECR_PS2); 235 236 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p))); 237 return residue; 238 } 239 #endif /* 0 */ 240 #endif /* IEEE 1284 support */ 241 #endif /* FIFO support */ 242 243 /* 244 * Clear TIMEOUT BIT in EPP MODE 245 * 246 * This is also used in SPP detection. 247 */ 248 static int clear_epp_timeout(struct parport *pb) 249 { 250 unsigned char r; 251 252 if (!(parport_pc_read_status(pb) & 0x01)) 253 return 1; 254 255 /* To clear timeout some chips require double read */ 256 parport_pc_read_status(pb); 257 r = parport_pc_read_status(pb); 258 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ 259 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ 260 r = parport_pc_read_status(pb); 261 262 return !(r & 0x01); 263 } 264 265 /* 266 * Access functions. 267 * 268 * Most of these aren't static because they may be used by the 269 * parport_xxx_yyy macros. extern __inline__ versions of several 270 * of these are in parport_pc.h. 271 */ 272 273 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs) 274 { 275 parport_generic_irq(irq, (struct parport *) dev_id, regs); 276 /* FIXME! Was it really ours? */ 277 return IRQ_HANDLED; 278 } 279 280 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s) 281 { 282 s->u.pc.ctr = 0xc; 283 if (dev->irq_func && 284 dev->port->irq != PARPORT_IRQ_NONE) 285 /* Set ackIntEn */ 286 s->u.pc.ctr |= 0x10; 287 288 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; 289 * D.Gruszka VScom */ 290 } 291 292 static void parport_pc_save_state(struct parport *p, struct parport_state *s) 293 { 294 const struct parport_pc_private *priv = p->physport->private_data; 295 s->u.pc.ctr = priv->ctr; 296 if (priv->ecr) 297 s->u.pc.ecr = inb (ECONTROL (p)); 298 } 299 300 static void parport_pc_restore_state(struct parport *p, struct parport_state *s) 301 { 302 struct parport_pc_private *priv = p->physport->private_data; 303 register unsigned char c = s->u.pc.ctr & priv->ctr_writable; 304 outb (c, CONTROL (p)); 305 priv->ctr = c; 306 if (priv->ecr) 307 ECR_WRITE (p, s->u.pc.ecr); 308 } 309 310 #ifdef CONFIG_PARPORT_1284 311 static size_t parport_pc_epp_read_data (struct parport *port, void *buf, 312 size_t length, int flags) 313 { 314 size_t got = 0; 315 316 if (flags & PARPORT_W91284PIC) { 317 unsigned char status; 318 size_t left = length; 319 320 /* use knowledge about data lines..: 321 * nFault is 0 if there is at least 1 byte in the Warp's FIFO 322 * pError is 1 if there are 16 bytes in the Warp's FIFO 323 */ 324 status = inb (STATUS (port)); 325 326 while (!(status & 0x08) && (got < length)) { 327 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) { 328 /* can grab 16 bytes from warp fifo */ 329 if (!((long)buf & 0x03)) { 330 insl (EPPDATA (port), buf, 4); 331 } else { 332 insb (EPPDATA (port), buf, 16); 333 } 334 buf += 16; 335 got += 16; 336 left -= 16; 337 } else { 338 /* grab single byte from the warp fifo */ 339 *((char *)buf) = inb (EPPDATA (port)); 340 buf++; 341 got++; 342 left--; 343 } 344 status = inb (STATUS (port)); 345 if (status & 0x01) { 346 /* EPP timeout should never occur... */ 347 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to " 348 "w91284pic (should not have done)\n", port->name); 349 clear_epp_timeout (port); 350 } 351 } 352 return got; 353 } 354 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 355 if (!(((long)buf | length) & 0x03)) { 356 insl (EPPDATA (port), buf, (length >> 2)); 357 } else { 358 insb (EPPDATA (port), buf, length); 359 } 360 if (inb (STATUS (port)) & 0x01) { 361 clear_epp_timeout (port); 362 return -EIO; 363 } 364 return length; 365 } 366 for (; got < length; got++) { 367 *((char*)buf) = inb (EPPDATA(port)); 368 buf++; 369 if (inb (STATUS (port)) & 0x01) { 370 /* EPP timeout */ 371 clear_epp_timeout (port); 372 break; 373 } 374 } 375 376 return got; 377 } 378 379 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf, 380 size_t length, int flags) 381 { 382 size_t written = 0; 383 384 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 385 if (!(((long)buf | length) & 0x03)) { 386 outsl (EPPDATA (port), buf, (length >> 2)); 387 } else { 388 outsb (EPPDATA (port), buf, length); 389 } 390 if (inb (STATUS (port)) & 0x01) { 391 clear_epp_timeout (port); 392 return -EIO; 393 } 394 return length; 395 } 396 for (; written < length; written++) { 397 outb (*((char*)buf), EPPDATA(port)); 398 buf++; 399 if (inb (STATUS(port)) & 0x01) { 400 clear_epp_timeout (port); 401 break; 402 } 403 } 404 405 return written; 406 } 407 408 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf, 409 size_t length, int flags) 410 { 411 size_t got = 0; 412 413 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 414 insb (EPPADDR (port), buf, length); 415 if (inb (STATUS (port)) & 0x01) { 416 clear_epp_timeout (port); 417 return -EIO; 418 } 419 return length; 420 } 421 for (; got < length; got++) { 422 *((char*)buf) = inb (EPPADDR (port)); 423 buf++; 424 if (inb (STATUS (port)) & 0x01) { 425 clear_epp_timeout (port); 426 break; 427 } 428 } 429 430 return got; 431 } 432 433 static size_t parport_pc_epp_write_addr (struct parport *port, 434 const void *buf, size_t length, 435 int flags) 436 { 437 size_t written = 0; 438 439 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 440 outsb (EPPADDR (port), buf, length); 441 if (inb (STATUS (port)) & 0x01) { 442 clear_epp_timeout (port); 443 return -EIO; 444 } 445 return length; 446 } 447 for (; written < length; written++) { 448 outb (*((char*)buf), EPPADDR (port)); 449 buf++; 450 if (inb (STATUS (port)) & 0x01) { 451 clear_epp_timeout (port); 452 break; 453 } 454 } 455 456 return written; 457 } 458 459 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf, 460 size_t length, int flags) 461 { 462 size_t got; 463 464 frob_set_mode (port, ECR_EPP); 465 parport_pc_data_reverse (port); 466 parport_pc_write_control (port, 0x4); 467 got = parport_pc_epp_read_data (port, buf, length, flags); 468 frob_set_mode (port, ECR_PS2); 469 470 return got; 471 } 472 473 static size_t parport_pc_ecpepp_write_data (struct parport *port, 474 const void *buf, size_t length, 475 int flags) 476 { 477 size_t written; 478 479 frob_set_mode (port, ECR_EPP); 480 parport_pc_write_control (port, 0x4); 481 parport_pc_data_forward (port); 482 written = parport_pc_epp_write_data (port, buf, length, flags); 483 frob_set_mode (port, ECR_PS2); 484 485 return written; 486 } 487 488 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf, 489 size_t length, int flags) 490 { 491 size_t got; 492 493 frob_set_mode (port, ECR_EPP); 494 parport_pc_data_reverse (port); 495 parport_pc_write_control (port, 0x4); 496 got = parport_pc_epp_read_addr (port, buf, length, flags); 497 frob_set_mode (port, ECR_PS2); 498 499 return got; 500 } 501 502 static size_t parport_pc_ecpepp_write_addr (struct parport *port, 503 const void *buf, size_t length, 504 int flags) 505 { 506 size_t written; 507 508 frob_set_mode (port, ECR_EPP); 509 parport_pc_write_control (port, 0x4); 510 parport_pc_data_forward (port); 511 written = parport_pc_epp_write_addr (port, buf, length, flags); 512 frob_set_mode (port, ECR_PS2); 513 514 return written; 515 } 516 #endif /* IEEE 1284 support */ 517 518 #ifdef CONFIG_PARPORT_PC_FIFO 519 static size_t parport_pc_fifo_write_block_pio (struct parport *port, 520 const void *buf, size_t length) 521 { 522 int ret = 0; 523 const unsigned char *bufp = buf; 524 size_t left = length; 525 unsigned long expire = jiffies + port->physport->cad->timeout; 526 const int fifo = FIFO (port); 527 int poll_for = 8; /* 80 usecs */ 528 const struct parport_pc_private *priv = port->physport->private_data; 529 const int fifo_depth = priv->fifo_depth; 530 531 port = port->physport; 532 533 /* We don't want to be interrupted every character. */ 534 parport_pc_disable_irq (port); 535 /* set nErrIntrEn and serviceIntr */ 536 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 537 538 /* Forward mode. */ 539 parport_pc_data_forward (port); /* Must be in PS2 mode */ 540 541 while (left) { 542 unsigned char byte; 543 unsigned char ecrval = inb (ECONTROL (port)); 544 int i = 0; 545 546 if (need_resched() && time_before (jiffies, expire)) 547 /* Can't yield the port. */ 548 schedule (); 549 550 /* Anyone else waiting for the port? */ 551 if (port->waithead) { 552 printk (KERN_DEBUG "Somebody wants the port\n"); 553 break; 554 } 555 556 if (ecrval & 0x02) { 557 /* FIFO is full. Wait for interrupt. */ 558 559 /* Clear serviceIntr */ 560 ECR_WRITE (port, ecrval & ~(1<<2)); 561 false_alarm: 562 ret = parport_wait_event (port, HZ); 563 if (ret < 0) break; 564 ret = 0; 565 if (!time_before (jiffies, expire)) { 566 /* Timed out. */ 567 printk (KERN_DEBUG "FIFO write timed out\n"); 568 break; 569 } 570 ecrval = inb (ECONTROL (port)); 571 if (!(ecrval & (1<<2))) { 572 if (need_resched() && 573 time_before (jiffies, expire)) 574 schedule (); 575 576 goto false_alarm; 577 } 578 579 continue; 580 } 581 582 /* Can't fail now. */ 583 expire = jiffies + port->cad->timeout; 584 585 poll: 586 if (signal_pending (current)) 587 break; 588 589 if (ecrval & 0x01) { 590 /* FIFO is empty. Blast it full. */ 591 const int n = left < fifo_depth ? left : fifo_depth; 592 outsb (fifo, bufp, n); 593 bufp += n; 594 left -= n; 595 596 /* Adjust the poll time. */ 597 if (i < (poll_for - 2)) poll_for--; 598 continue; 599 } else if (i++ < poll_for) { 600 udelay (10); 601 ecrval = inb (ECONTROL (port)); 602 goto poll; 603 } 604 605 /* Half-full (call me an optimist) */ 606 byte = *bufp++; 607 outb (byte, fifo); 608 left--; 609 } 610 611 dump_parport_state ("leave fifo_write_block_pio", port); 612 return length - left; 613 } 614 615 #ifdef HAS_DMA 616 static size_t parport_pc_fifo_write_block_dma (struct parport *port, 617 const void *buf, size_t length) 618 { 619 int ret = 0; 620 unsigned long dmaflag; 621 size_t left = length; 622 const struct parport_pc_private *priv = port->physport->private_data; 623 dma_addr_t dma_addr, dma_handle; 624 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ 625 unsigned long start = (unsigned long) buf; 626 unsigned long end = (unsigned long) buf + length - 1; 627 628 dump_parport_state ("enter fifo_write_block_dma", port); 629 if (end < MAX_DMA_ADDRESS) { 630 /* If it would cross a 64k boundary, cap it at the end. */ 631 if ((start ^ end) & ~0xffffUL) 632 maxlen = 0x10000 - (start & 0xffff); 633 634 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length, 635 PCI_DMA_TODEVICE); 636 } else { 637 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */ 638 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ 639 dma_addr = priv->dma_handle; 640 dma_handle = 0; 641 } 642 643 port = port->physport; 644 645 /* We don't want to be interrupted every character. */ 646 parport_pc_disable_irq (port); 647 /* set nErrIntrEn and serviceIntr */ 648 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 649 650 /* Forward mode. */ 651 parport_pc_data_forward (port); /* Must be in PS2 mode */ 652 653 while (left) { 654 unsigned long expire = jiffies + port->physport->cad->timeout; 655 656 size_t count = left; 657 658 if (count > maxlen) 659 count = maxlen; 660 661 if (!dma_handle) /* bounce buffer ! */ 662 memcpy(priv->dma_buf, buf, count); 663 664 dmaflag = claim_dma_lock(); 665 disable_dma(port->dma); 666 clear_dma_ff(port->dma); 667 set_dma_mode(port->dma, DMA_MODE_WRITE); 668 set_dma_addr(port->dma, dma_addr); 669 set_dma_count(port->dma, count); 670 671 /* Set DMA mode */ 672 frob_econtrol (port, 1<<3, 1<<3); 673 674 /* Clear serviceIntr */ 675 frob_econtrol (port, 1<<2, 0); 676 677 enable_dma(port->dma); 678 release_dma_lock(dmaflag); 679 680 /* assume DMA will be successful */ 681 left -= count; 682 buf += count; 683 if (dma_handle) dma_addr += count; 684 685 /* Wait for interrupt. */ 686 false_alarm: 687 ret = parport_wait_event (port, HZ); 688 if (ret < 0) break; 689 ret = 0; 690 if (!time_before (jiffies, expire)) { 691 /* Timed out. */ 692 printk (KERN_DEBUG "DMA write timed out\n"); 693 break; 694 } 695 /* Is serviceIntr set? */ 696 if (!(inb (ECONTROL (port)) & (1<<2))) { 697 cond_resched(); 698 699 goto false_alarm; 700 } 701 702 dmaflag = claim_dma_lock(); 703 disable_dma(port->dma); 704 clear_dma_ff(port->dma); 705 count = get_dma_residue(port->dma); 706 release_dma_lock(dmaflag); 707 708 cond_resched(); /* Can't yield the port. */ 709 710 /* Anyone else waiting for the port? */ 711 if (port->waithead) { 712 printk (KERN_DEBUG "Somebody wants the port\n"); 713 break; 714 } 715 716 /* update for possible DMA residue ! */ 717 buf -= count; 718 left += count; 719 if (dma_handle) dma_addr -= count; 720 } 721 722 /* Maybe got here through break, so adjust for DMA residue! */ 723 dmaflag = claim_dma_lock(); 724 disable_dma(port->dma); 725 clear_dma_ff(port->dma); 726 left += get_dma_residue(port->dma); 727 release_dma_lock(dmaflag); 728 729 /* Turn off DMA mode */ 730 frob_econtrol (port, 1<<3, 0); 731 732 if (dma_handle) 733 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE); 734 735 dump_parport_state ("leave fifo_write_block_dma", port); 736 return length - left; 737 } 738 #endif 739 740 static inline size_t parport_pc_fifo_write_block(struct parport *port, 741 const void *buf, size_t length) 742 { 743 #ifdef HAS_DMA 744 if (port->dma != PARPORT_DMA_NONE) 745 return parport_pc_fifo_write_block_dma (port, buf, length); 746 #endif 747 return parport_pc_fifo_write_block_pio (port, buf, length); 748 } 749 750 /* Parallel Port FIFO mode (ECP chipsets) */ 751 static size_t parport_pc_compat_write_block_pio (struct parport *port, 752 const void *buf, size_t length, 753 int flags) 754 { 755 size_t written; 756 int r; 757 unsigned long expire; 758 const struct parport_pc_private *priv = port->physport->private_data; 759 760 /* Special case: a timeout of zero means we cannot call schedule(). 761 * Also if O_NONBLOCK is set then use the default implementation. */ 762 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 763 return parport_ieee1284_write_compat (port, buf, 764 length, flags); 765 766 /* Set up parallel port FIFO mode.*/ 767 parport_pc_data_forward (port); /* Must be in PS2 mode */ 768 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0); 769 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */ 770 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name); 771 772 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 773 774 /* Write the data to the FIFO. */ 775 written = parport_pc_fifo_write_block(port, buf, length); 776 777 /* Finish up. */ 778 /* For some hardware we don't want to touch the mode until 779 * the FIFO is empty, so allow 4 seconds for each position 780 * in the fifo. 781 */ 782 expire = jiffies + (priv->fifo_depth * HZ * 4); 783 do { 784 /* Wait for the FIFO to empty */ 785 r = change_mode (port, ECR_PS2); 786 if (r != -EBUSY) { 787 break; 788 } 789 } while (time_before (jiffies, expire)); 790 if (r == -EBUSY) { 791 792 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 793 794 /* Prevent further data transfer. */ 795 frob_set_mode (port, ECR_TST); 796 797 /* Adjust for the contents of the FIFO. */ 798 for (written -= priv->fifo_depth; ; written++) { 799 if (inb (ECONTROL (port)) & 0x2) { 800 /* Full up. */ 801 break; 802 } 803 outb (0, FIFO (port)); 804 } 805 806 /* Reset the FIFO and return to PS2 mode. */ 807 frob_set_mode (port, ECR_PS2); 808 } 809 810 r = parport_wait_peripheral (port, 811 PARPORT_STATUS_BUSY, 812 PARPORT_STATUS_BUSY); 813 if (r) 814 printk (KERN_DEBUG 815 "%s: BUSY timeout (%d) in compat_write_block_pio\n", 816 port->name, r); 817 818 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 819 820 return written; 821 } 822 823 /* ECP */ 824 #ifdef CONFIG_PARPORT_1284 825 static size_t parport_pc_ecp_write_block_pio (struct parport *port, 826 const void *buf, size_t length, 827 int flags) 828 { 829 size_t written; 830 int r; 831 unsigned long expire; 832 const struct parport_pc_private *priv = port->physport->private_data; 833 834 /* Special case: a timeout of zero means we cannot call schedule(). 835 * Also if O_NONBLOCK is set then use the default implementation. */ 836 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 837 return parport_ieee1284_ecp_write_data (port, buf, 838 length, flags); 839 840 /* Switch to forward mode if necessary. */ 841 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 842 /* Event 47: Set nInit high. */ 843 parport_frob_control (port, 844 PARPORT_CONTROL_INIT 845 | PARPORT_CONTROL_AUTOFD, 846 PARPORT_CONTROL_INIT 847 | PARPORT_CONTROL_AUTOFD); 848 849 /* Event 49: PError goes high. */ 850 r = parport_wait_peripheral (port, 851 PARPORT_STATUS_PAPEROUT, 852 PARPORT_STATUS_PAPEROUT); 853 if (r) { 854 printk (KERN_DEBUG "%s: PError timeout (%d) " 855 "in ecp_write_block_pio\n", port->name, r); 856 } 857 } 858 859 /* Set up ECP parallel port mode.*/ 860 parport_pc_data_forward (port); /* Must be in PS2 mode */ 861 parport_pc_frob_control (port, 862 PARPORT_CONTROL_STROBE | 863 PARPORT_CONTROL_AUTOFD, 864 0); 865 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 866 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 867 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 868 869 /* Write the data to the FIFO. */ 870 written = parport_pc_fifo_write_block(port, buf, length); 871 872 /* Finish up. */ 873 /* For some hardware we don't want to touch the mode until 874 * the FIFO is empty, so allow 4 seconds for each position 875 * in the fifo. 876 */ 877 expire = jiffies + (priv->fifo_depth * (HZ * 4)); 878 do { 879 /* Wait for the FIFO to empty */ 880 r = change_mode (port, ECR_PS2); 881 if (r != -EBUSY) { 882 break; 883 } 884 } while (time_before (jiffies, expire)); 885 if (r == -EBUSY) { 886 887 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 888 889 /* Prevent further data transfer. */ 890 frob_set_mode (port, ECR_TST); 891 892 /* Adjust for the contents of the FIFO. */ 893 for (written -= priv->fifo_depth; ; written++) { 894 if (inb (ECONTROL (port)) & 0x2) { 895 /* Full up. */ 896 break; 897 } 898 outb (0, FIFO (port)); 899 } 900 901 /* Reset the FIFO and return to PS2 mode. */ 902 frob_set_mode (port, ECR_PS2); 903 904 /* Host transfer recovery. */ 905 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 906 udelay (5); 907 parport_frob_control (port, PARPORT_CONTROL_INIT, 0); 908 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 909 if (r) 910 printk (KERN_DEBUG "%s: PE,1 timeout (%d) " 911 "in ecp_write_block_pio\n", port->name, r); 912 913 parport_frob_control (port, 914 PARPORT_CONTROL_INIT, 915 PARPORT_CONTROL_INIT); 916 r = parport_wait_peripheral (port, 917 PARPORT_STATUS_PAPEROUT, 918 PARPORT_STATUS_PAPEROUT); 919 if (r) 920 printk (KERN_DEBUG "%s: PE,2 timeout (%d) " 921 "in ecp_write_block_pio\n", port->name, r); 922 } 923 924 r = parport_wait_peripheral (port, 925 PARPORT_STATUS_BUSY, 926 PARPORT_STATUS_BUSY); 927 if(r) 928 printk (KERN_DEBUG 929 "%s: BUSY timeout (%d) in ecp_write_block_pio\n", 930 port->name, r); 931 932 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 933 934 return written; 935 } 936 937 #if 0 938 static size_t parport_pc_ecp_read_block_pio (struct parport *port, 939 void *buf, size_t length, 940 int flags) 941 { 942 size_t left = length; 943 size_t fifofull; 944 int r; 945 const int fifo = FIFO(port); 946 const struct parport_pc_private *priv = port->physport->private_data; 947 const int fifo_depth = priv->fifo_depth; 948 char *bufp = buf; 949 950 port = port->physport; 951 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); 952 dump_parport_state ("enter fcn", port); 953 954 /* Special case: a timeout of zero means we cannot call schedule(). 955 * Also if O_NONBLOCK is set then use the default implementation. */ 956 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 957 return parport_ieee1284_ecp_read_data (port, buf, 958 length, flags); 959 960 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { 961 /* If the peripheral is allowed to send RLE compressed 962 * data, it is possible for a byte to expand to 128 963 * bytes in the FIFO. */ 964 fifofull = 128; 965 } else { 966 fifofull = fifo_depth; 967 } 968 969 /* If the caller wants less than a full FIFO's worth of data, 970 * go through software emulation. Otherwise we may have to throw 971 * away data. */ 972 if (length < fifofull) 973 return parport_ieee1284_ecp_read_data (port, buf, 974 length, flags); 975 976 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { 977 /* change to reverse-idle phase (must be in forward-idle) */ 978 979 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ 980 parport_frob_control (port, 981 PARPORT_CONTROL_AUTOFD 982 | PARPORT_CONTROL_STROBE, 983 PARPORT_CONTROL_AUTOFD); 984 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 985 udelay (5); 986 /* Event 39: Set nInit low to initiate bus reversal */ 987 parport_frob_control (port, 988 PARPORT_CONTROL_INIT, 989 0); 990 /* Event 40: Wait for nAckReverse (PError) to go low */ 991 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 992 if (r) { 993 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) " 994 "in ecp_read_block_pio\n", port->name, r); 995 return 0; 996 } 997 } 998 999 /* Set up ECP FIFO mode.*/ 1000 /* parport_pc_frob_control (port, 1001 PARPORT_CONTROL_STROBE | 1002 PARPORT_CONTROL_AUTOFD, 1003 PARPORT_CONTROL_AUTOFD); */ 1004 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 1005 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 1006 1007 port->ieee1284.phase = IEEE1284_PH_REV_DATA; 1008 1009 /* the first byte must be collected manually */ 1010 dump_parport_state ("pre 43", port); 1011 /* Event 43: Wait for nAck to go low */ 1012 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); 1013 if (r) { 1014 /* timed out while reading -- no data */ 1015 printk (KERN_DEBUG "PIO read timed out (initial byte)\n"); 1016 goto out_no_data; 1017 } 1018 /* read byte */ 1019 *bufp++ = inb (DATA (port)); 1020 left--; 1021 dump_parport_state ("43-44", port); 1022 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ 1023 parport_pc_frob_control (port, 1024 PARPORT_CONTROL_AUTOFD, 1025 0); 1026 dump_parport_state ("pre 45", port); 1027 /* Event 45: Wait for nAck to go high */ 1028 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */ 1029 dump_parport_state ("post 45", port); 1030 r = 0; 1031 if (r) { 1032 /* timed out while waiting for peripheral to respond to ack */ 1033 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); 1034 1035 /* keep hold of the byte we've got already */ 1036 goto out_no_data; 1037 } 1038 /* Event 46: nAutoFd (HostAck) goes low to accept more data */ 1039 parport_pc_frob_control (port, 1040 PARPORT_CONTROL_AUTOFD, 1041 PARPORT_CONTROL_AUTOFD); 1042 1043 1044 dump_parport_state ("rev idle", port); 1045 /* Do the transfer. */ 1046 while (left > fifofull) { 1047 int ret; 1048 unsigned long expire = jiffies + port->cad->timeout; 1049 unsigned char ecrval = inb (ECONTROL (port)); 1050 1051 if (need_resched() && time_before (jiffies, expire)) 1052 /* Can't yield the port. */ 1053 schedule (); 1054 1055 /* At this point, the FIFO may already be full. In 1056 * that case ECP is already holding back the 1057 * peripheral (assuming proper design) with a delayed 1058 * handshake. Work fast to avoid a peripheral 1059 * timeout. */ 1060 1061 if (ecrval & 0x01) { 1062 /* FIFO is empty. Wait for interrupt. */ 1063 dump_parport_state ("FIFO empty", port); 1064 1065 /* Anyone else waiting for the port? */ 1066 if (port->waithead) { 1067 printk (KERN_DEBUG "Somebody wants the port\n"); 1068 break; 1069 } 1070 1071 /* Clear serviceIntr */ 1072 ECR_WRITE (port, ecrval & ~(1<<2)); 1073 false_alarm: 1074 dump_parport_state ("waiting", port); 1075 ret = parport_wait_event (port, HZ); 1076 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret); 1077 if (ret < 0) 1078 break; 1079 ret = 0; 1080 if (!time_before (jiffies, expire)) { 1081 /* Timed out. */ 1082 dump_parport_state ("timeout", port); 1083 printk (KERN_DEBUG "PIO read timed out\n"); 1084 break; 1085 } 1086 ecrval = inb (ECONTROL (port)); 1087 if (!(ecrval & (1<<2))) { 1088 if (need_resched() && 1089 time_before (jiffies, expire)) { 1090 schedule (); 1091 } 1092 goto false_alarm; 1093 } 1094 1095 /* Depending on how the FIFO threshold was 1096 * set, how long interrupt service took, and 1097 * how fast the peripheral is, we might be 1098 * lucky and have a just filled FIFO. */ 1099 continue; 1100 } 1101 1102 if (ecrval & 0x02) { 1103 /* FIFO is full. */ 1104 dump_parport_state ("FIFO full", port); 1105 insb (fifo, bufp, fifo_depth); 1106 bufp += fifo_depth; 1107 left -= fifo_depth; 1108 continue; 1109 } 1110 1111 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n"); 1112 1113 /* FIFO not filled. We will cycle this loop for a while 1114 * and either the peripheral will fill it faster, 1115 * tripping a fast empty with insb, or we empty it. */ 1116 *bufp++ = inb (fifo); 1117 left--; 1118 } 1119 1120 /* scoop up anything left in the FIFO */ 1121 while (left && !(inb (ECONTROL (port) & 0x01))) { 1122 *bufp++ = inb (fifo); 1123 left--; 1124 } 1125 1126 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; 1127 dump_parport_state ("rev idle2", port); 1128 1129 out_no_data: 1130 1131 /* Go to forward idle mode to shut the peripheral up (event 47). */ 1132 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); 1133 1134 /* event 49: PError goes high */ 1135 r = parport_wait_peripheral (port, 1136 PARPORT_STATUS_PAPEROUT, 1137 PARPORT_STATUS_PAPEROUT); 1138 if (r) { 1139 printk (KERN_DEBUG 1140 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", 1141 port->name, r); 1142 } 1143 1144 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1145 1146 /* Finish up. */ 1147 { 1148 int lost = get_fifo_residue (port); 1149 if (lost) 1150 /* Shouldn't happen with compliant peripherals. */ 1151 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", 1152 port->name, lost); 1153 } 1154 1155 dump_parport_state ("fwd idle", port); 1156 return length - left; 1157 } 1158 #endif /* 0 */ 1159 #endif /* IEEE 1284 support */ 1160 #endif /* Allowed to use FIFO/DMA */ 1161 1162 1163 /* 1164 * ****************************************** 1165 * INITIALISATION AND MODULE STUFF BELOW HERE 1166 * ****************************************** 1167 */ 1168 1169 /* GCC is not inlining extern inline function later overwriten to non-inline, 1170 so we use outlined_ variants here. */ 1171 static const struct parport_operations parport_pc_ops = 1172 { 1173 .write_data = parport_pc_write_data, 1174 .read_data = parport_pc_read_data, 1175 1176 .write_control = parport_pc_write_control, 1177 .read_control = parport_pc_read_control, 1178 .frob_control = parport_pc_frob_control, 1179 1180 .read_status = parport_pc_read_status, 1181 1182 .enable_irq = parport_pc_enable_irq, 1183 .disable_irq = parport_pc_disable_irq, 1184 1185 .data_forward = parport_pc_data_forward, 1186 .data_reverse = parport_pc_data_reverse, 1187 1188 .init_state = parport_pc_init_state, 1189 .save_state = parport_pc_save_state, 1190 .restore_state = parport_pc_restore_state, 1191 1192 .epp_write_data = parport_ieee1284_epp_write_data, 1193 .epp_read_data = parport_ieee1284_epp_read_data, 1194 .epp_write_addr = parport_ieee1284_epp_write_addr, 1195 .epp_read_addr = parport_ieee1284_epp_read_addr, 1196 1197 .ecp_write_data = parport_ieee1284_ecp_write_data, 1198 .ecp_read_data = parport_ieee1284_ecp_read_data, 1199 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1200 1201 .compat_write_data = parport_ieee1284_write_compat, 1202 .nibble_read_data = parport_ieee1284_read_nibble, 1203 .byte_read_data = parport_ieee1284_read_byte, 1204 1205 .owner = THIS_MODULE, 1206 }; 1207 1208 #ifdef CONFIG_PARPORT_PC_SUPERIO 1209 /* Super-IO chipset detection, Winbond, SMSC */ 1210 static void __devinit show_parconfig_smsc37c669(int io, int key) 1211 { 1212 int cr1,cr4,cra,cr23,cr26,cr27,i=0; 1213 static const char *const modes[]={ 1214 "SPP and Bidirectional (PS/2)", 1215 "EPP and SPP", 1216 "ECP", 1217 "ECP and EPP" }; 1218 1219 outb(key,io); 1220 outb(key,io); 1221 outb(1,io); 1222 cr1=inb(io+1); 1223 outb(4,io); 1224 cr4=inb(io+1); 1225 outb(0x0a,io); 1226 cra=inb(io+1); 1227 outb(0x23,io); 1228 cr23=inb(io+1); 1229 outb(0x26,io); 1230 cr26=inb(io+1); 1231 outb(0x27,io); 1232 cr27=inb(io+1); 1233 outb(0xaa,io); 1234 1235 if (verbose_probing) { 1236 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " 1237 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", 1238 cr1,cr4,cra,cr23,cr26,cr27); 1239 1240 /* The documentation calls DMA and IRQ-Lines by letters, so 1241 the board maker can/will wire them 1242 appropriately/randomly... G=reserved H=IDE-irq, */ 1243 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, " 1244 "fifo threshold=%d\n", cr23*4, 1245 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-', 1246 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f); 1247 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", 1248 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no"); 1249 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n", 1250 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03], 1251 (cr4 & 0x40) ? "1.7" : "1.9"); 1252 } 1253 1254 /* Heuristics ! BIOS setup for this mainboard device limits 1255 the choices to standard settings, i.e. io-address and IRQ 1256 are related, however DMA can be 1 or 3, assume DMA_A=DMA1, 1257 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ 1258 if(cr23*4 >=0x100) { /* if active */ 1259 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1260 i++; 1261 if(i==NR_SUPERIOS) 1262 printk(KERN_INFO "Super-IO: too many chips!\n"); 1263 else { 1264 int d; 1265 switch (cr23*4) { 1266 case 0x3bc: 1267 superios[i].io = 0x3bc; 1268 superios[i].irq = 7; 1269 break; 1270 case 0x378: 1271 superios[i].io = 0x378; 1272 superios[i].irq = 7; 1273 break; 1274 case 0x278: 1275 superios[i].io = 0x278; 1276 superios[i].irq = 5; 1277 } 1278 d=(cr26 &0x0f); 1279 if((d==1) || (d==3)) 1280 superios[i].dma= d; 1281 else 1282 superios[i].dma= PARPORT_DMA_NONE; 1283 } 1284 } 1285 } 1286 1287 1288 static void __devinit show_parconfig_winbond(int io, int key) 1289 { 1290 int cr30,cr60,cr61,cr70,cr74,crf0,i=0; 1291 static const char *const modes[] = { 1292 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ 1293 "EPP-1.9 and SPP", 1294 "ECP", 1295 "ECP and EPP-1.9", 1296 "Standard (SPP)", 1297 "EPP-1.7 and SPP", /* 5 */ 1298 "undefined!", 1299 "ECP and EPP-1.7" }; 1300 static char *const irqtypes[] = { 1301 "pulsed low, high-Z", 1302 "follows nACK" }; 1303 1304 /* The registers are called compatible-PnP because the 1305 register layout is modelled after ISA-PnP, the access 1306 method is just another ... */ 1307 outb(key,io); 1308 outb(key,io); 1309 outb(0x07,io); /* Register 7: Select Logical Device */ 1310 outb(0x01,io+1); /* LD1 is Parallel Port */ 1311 outb(0x30,io); 1312 cr30=inb(io+1); 1313 outb(0x60,io); 1314 cr60=inb(io+1); 1315 outb(0x61,io); 1316 cr61=inb(io+1); 1317 outb(0x70,io); 1318 cr70=inb(io+1); 1319 outb(0x74,io); 1320 cr74=inb(io+1); 1321 outb(0xf0,io); 1322 crf0=inb(io+1); 1323 outb(0xaa,io); 1324 1325 if (verbose_probing) { 1326 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x " 1327 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0); 1328 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", 1329 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f ); 1330 if ((cr74 & 0x07) > 3) 1331 printk("dma=none\n"); 1332 else 1333 printk("dma=%d\n",cr74 & 0x07); 1334 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", 1335 irqtypes[crf0>>7], (crf0>>3)&0x0f); 1336 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]); 1337 } 1338 1339 if(cr30 & 0x01) { /* the settings can be interrogated later ... */ 1340 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1341 i++; 1342 if(i==NR_SUPERIOS) 1343 printk(KERN_INFO "Super-IO: too many chips!\n"); 1344 else { 1345 superios[i].io = (cr60<<8)|cr61; 1346 superios[i].irq = cr70&0x0f; 1347 superios[i].dma = (((cr74 & 0x07) > 3) ? 1348 PARPORT_DMA_NONE : (cr74 & 0x07)); 1349 } 1350 } 1351 } 1352 1353 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid) 1354 { 1355 const char *type = "unknown"; 1356 int id,progif=2; 1357 1358 if (devid == devrev) 1359 /* simple heuristics, we happened to read some 1360 non-winbond register */ 1361 return; 1362 1363 id=(devid<<8) | devrev; 1364 1365 /* Values are from public data sheets pdf files, I can just 1366 confirm 83977TF is correct :-) */ 1367 if (id == 0x9771) type="83977F/AF"; 1368 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x"; 1369 else if (id == 0x9774) type="83977ATF"; 1370 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x"; 1371 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x"; 1372 else if ((id & ~0x0f) == 0x5210) type="83627"; 1373 else if ((id & ~0x0f) == 0x6010) type="83697HF"; 1374 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;} 1375 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;} 1376 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;} 1377 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;} 1378 else progif=0; 1379 1380 if (verbose_probing) 1381 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " 1382 "devid=%02x devrev=%02x oldid=%02x type=%s\n", 1383 efer, key, devid, devrev, oldid, type); 1384 1385 if (progif == 2) 1386 show_parconfig_winbond(efer,key); 1387 } 1388 1389 static void __devinit decode_smsc(int efer, int key, int devid, int devrev) 1390 { 1391 const char *type = "unknown"; 1392 void (*func)(int io, int key); 1393 int id; 1394 1395 if (devid == devrev) 1396 /* simple heuristics, we happened to read some 1397 non-smsc register */ 1398 return; 1399 1400 func=NULL; 1401 id=(devid<<8) | devrev; 1402 1403 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;} 1404 else if (id==0x6582) type="37c665IR"; 1405 else if (devid==0x65) type="37c665GT"; 1406 else if (devid==0x66) type="37c666GT"; 1407 1408 if (verbose_probing) 1409 printk(KERN_INFO "SMSC chip at EFER=0x%x " 1410 "key=0x%02x devid=%02x devrev=%02x type=%s\n", 1411 efer, key, devid, devrev, type); 1412 1413 if (func) 1414 func(efer,key); 1415 } 1416 1417 1418 static void __devinit winbond_check(int io, int key) 1419 { 1420 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1421 1422 if (!request_region(io, 3, __FUNCTION__)) 1423 return; 1424 1425 /* First probe without key */ 1426 outb(0x20,io); 1427 x_devid=inb(io+1); 1428 outb(0x21,io); 1429 x_devrev=inb(io+1); 1430 outb(0x09,io); 1431 x_oldid=inb(io+1); 1432 1433 outb(key,io); 1434 outb(key,io); /* Write Magic Sequence to EFER, extended 1435 funtion enable register */ 1436 outb(0x20,io); /* Write EFIR, extended function index register */ 1437 devid=inb(io+1); /* Read EFDR, extended function data register */ 1438 outb(0x21,io); 1439 devrev=inb(io+1); 1440 outb(0x09,io); 1441 oldid=inb(io+1); 1442 outb(0xaa,io); /* Magic Seal */ 1443 1444 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1445 goto out; /* protection against false positives */ 1446 1447 decode_winbond(io,key,devid,devrev,oldid); 1448 out: 1449 release_region(io, 3); 1450 } 1451 1452 static void __devinit winbond_check2(int io,int key) 1453 { 1454 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1455 1456 if (!request_region(io, 3, __FUNCTION__)) 1457 return; 1458 1459 /* First probe without the key */ 1460 outb(0x20,io+2); 1461 x_devid=inb(io+2); 1462 outb(0x21,io+1); 1463 x_devrev=inb(io+2); 1464 outb(0x09,io+1); 1465 x_oldid=inb(io+2); 1466 1467 outb(key,io); /* Write Magic Byte to EFER, extended 1468 funtion enable register */ 1469 outb(0x20,io+2); /* Write EFIR, extended function index register */ 1470 devid=inb(io+2); /* Read EFDR, extended function data register */ 1471 outb(0x21,io+1); 1472 devrev=inb(io+2); 1473 outb(0x09,io+1); 1474 oldid=inb(io+2); 1475 outb(0xaa,io); /* Magic Seal */ 1476 1477 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1478 goto out; /* protection against false positives */ 1479 1480 decode_winbond(io,key,devid,devrev,oldid); 1481 out: 1482 release_region(io, 3); 1483 } 1484 1485 static void __devinit smsc_check(int io, int key) 1486 { 1487 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; 1488 1489 if (!request_region(io, 3, __FUNCTION__)) 1490 return; 1491 1492 /* First probe without the key */ 1493 outb(0x0d,io); 1494 x_oldid=inb(io+1); 1495 outb(0x0e,io); 1496 x_oldrev=inb(io+1); 1497 outb(0x20,io); 1498 x_id=inb(io+1); 1499 outb(0x21,io); 1500 x_rev=inb(io+1); 1501 1502 outb(key,io); 1503 outb(key,io); /* Write Magic Sequence to EFER, extended 1504 funtion enable register */ 1505 outb(0x0d,io); /* Write EFIR, extended function index register */ 1506 oldid=inb(io+1); /* Read EFDR, extended function data register */ 1507 outb(0x0e,io); 1508 oldrev=inb(io+1); 1509 outb(0x20,io); 1510 id=inb(io+1); 1511 outb(0x21,io); 1512 rev=inb(io+1); 1513 outb(0xaa,io); /* Magic Seal */ 1514 1515 if ((x_id == id) && (x_oldrev == oldrev) && 1516 (x_oldid == oldid) && (x_rev == rev)) 1517 goto out; /* protection against false positives */ 1518 1519 decode_smsc(io,key,oldid,oldrev); 1520 out: 1521 release_region(io, 3); 1522 } 1523 1524 1525 static void __devinit detect_and_report_winbond (void) 1526 { 1527 if (verbose_probing) 1528 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); 1529 winbond_check(0x3f0,0x87); 1530 winbond_check(0x370,0x87); 1531 winbond_check(0x2e ,0x87); 1532 winbond_check(0x4e ,0x87); 1533 winbond_check(0x3f0,0x86); 1534 winbond_check2(0x250,0x88); 1535 winbond_check2(0x250,0x89); 1536 } 1537 1538 static void __devinit detect_and_report_smsc (void) 1539 { 1540 if (verbose_probing) 1541 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); 1542 smsc_check(0x3f0,0x55); 1543 smsc_check(0x370,0x55); 1544 smsc_check(0x3f0,0x44); 1545 smsc_check(0x370,0x44); 1546 } 1547 #endif /* CONFIG_PARPORT_PC_SUPERIO */ 1548 1549 static int __devinit get_superio_dma (struct parport *p) 1550 { 1551 int i=0; 1552 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1553 i++; 1554 if (i!=NR_SUPERIOS) 1555 return superios[i].dma; 1556 return PARPORT_DMA_NONE; 1557 } 1558 1559 static int get_superio_irq (struct parport *p) 1560 { 1561 int i=0; 1562 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1563 i++; 1564 if (i!=NR_SUPERIOS) 1565 return superios[i].irq; 1566 return PARPORT_IRQ_NONE; 1567 } 1568 1569 1570 /* --- Mode detection ------------------------------------- */ 1571 1572 /* 1573 * Checks for port existence, all ports support SPP MODE 1574 * Returns: 1575 * 0 : No parallel port at this address 1576 * PARPORT_MODE_PCSPP : SPP port detected 1577 * (if the user specified an ioport himself, 1578 * this shall always be the case!) 1579 * 1580 */ 1581 static int parport_SPP_supported(struct parport *pb) 1582 { 1583 unsigned char r, w; 1584 1585 /* 1586 * first clear an eventually pending EPP timeout 1587 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset 1588 * that does not even respond to SPP cycles if an EPP 1589 * timeout is pending 1590 */ 1591 clear_epp_timeout(pb); 1592 1593 /* Do a simple read-write test to make sure the port exists. */ 1594 w = 0xc; 1595 outb (w, CONTROL (pb)); 1596 1597 /* Is there a control register that we can read from? Some 1598 * ports don't allow reads, so read_control just returns a 1599 * software copy. Some ports _do_ allow reads, so bypass the 1600 * software copy here. In addition, some bits aren't 1601 * writable. */ 1602 r = inb (CONTROL (pb)); 1603 if ((r & 0xf) == w) { 1604 w = 0xe; 1605 outb (w, CONTROL (pb)); 1606 r = inb (CONTROL (pb)); 1607 outb (0xc, CONTROL (pb)); 1608 if ((r & 0xf) == w) 1609 return PARPORT_MODE_PCSPP; 1610 } 1611 1612 if (user_specified) 1613 /* That didn't work, but the user thinks there's a 1614 * port here. */ 1615 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: " 1616 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1617 1618 /* Try the data register. The data lines aren't tri-stated at 1619 * this stage, so we expect back what we wrote. */ 1620 w = 0xaa; 1621 parport_pc_write_data (pb, w); 1622 r = parport_pc_read_data (pb); 1623 if (r == w) { 1624 w = 0x55; 1625 parport_pc_write_data (pb, w); 1626 r = parport_pc_read_data (pb); 1627 if (r == w) 1628 return PARPORT_MODE_PCSPP; 1629 } 1630 1631 if (user_specified) { 1632 /* Didn't work, but the user is convinced this is the 1633 * place. */ 1634 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: " 1635 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1636 printk (KERN_INFO "parport 0x%lx: You gave this address, " 1637 "but there is probably no parallel port there!\n", 1638 pb->base); 1639 } 1640 1641 /* It's possible that we can't read the control register or 1642 * the data register. In that case just believe the user. */ 1643 if (user_specified) 1644 return PARPORT_MODE_PCSPP; 1645 1646 return 0; 1647 } 1648 1649 /* Check for ECR 1650 * 1651 * Old style XT ports alias io ports every 0x400, hence accessing ECR 1652 * on these cards actually accesses the CTR. 1653 * 1654 * Modern cards don't do this but reading from ECR will return 0xff 1655 * regardless of what is written here if the card does NOT support 1656 * ECP. 1657 * 1658 * We first check to see if ECR is the same as CTR. If not, the low 1659 * two bits of ECR aren't writable, so we check by writing ECR and 1660 * reading it back to see if it's what we expect. 1661 */ 1662 static int parport_ECR_present(struct parport *pb) 1663 { 1664 struct parport_pc_private *priv = pb->private_data; 1665 unsigned char r = 0xc; 1666 1667 outb (r, CONTROL (pb)); 1668 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) { 1669 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */ 1670 1671 r = inb (CONTROL (pb)); 1672 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2)) 1673 goto no_reg; /* Sure that no ECR register exists */ 1674 } 1675 1676 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1) 1677 goto no_reg; 1678 1679 ECR_WRITE (pb, 0x34); 1680 if (inb (ECONTROL (pb)) != 0x35) 1681 goto no_reg; 1682 1683 priv->ecr = 1; 1684 outb (0xc, CONTROL (pb)); 1685 1686 /* Go to mode 000 */ 1687 frob_set_mode (pb, ECR_SPP); 1688 1689 return 1; 1690 1691 no_reg: 1692 outb (0xc, CONTROL (pb)); 1693 return 0; 1694 } 1695 1696 #ifdef CONFIG_PARPORT_1284 1697 /* Detect PS/2 support. 1698 * 1699 * Bit 5 (0x20) sets the PS/2 data direction; setting this high 1700 * allows us to read data from the data lines. In theory we would get back 1701 * 0xff but any peripheral attached to the port may drag some or all of the 1702 * lines down to zero. So if we get back anything that isn't the contents 1703 * of the data register we deem PS/2 support to be present. 1704 * 1705 * Some SPP ports have "half PS/2" ability - you can't turn off the line 1706 * drivers, but an external peripheral with sufficiently beefy drivers of 1707 * its own can overpower them and assert its own levels onto the bus, from 1708 * where they can then be read back as normal. Ports with this property 1709 * and the right type of device attached are likely to fail the SPP test, 1710 * (as they will appear to have stuck bits) and so the fact that they might 1711 * be misdetected here is rather academic. 1712 */ 1713 1714 static int parport_PS2_supported(struct parport *pb) 1715 { 1716 int ok = 0; 1717 1718 clear_epp_timeout(pb); 1719 1720 /* try to tri-state the buffer */ 1721 parport_pc_data_reverse (pb); 1722 1723 parport_pc_write_data(pb, 0x55); 1724 if (parport_pc_read_data(pb) != 0x55) ok++; 1725 1726 parport_pc_write_data(pb, 0xaa); 1727 if (parport_pc_read_data(pb) != 0xaa) ok++; 1728 1729 /* cancel input mode */ 1730 parport_pc_data_forward (pb); 1731 1732 if (ok) { 1733 pb->modes |= PARPORT_MODE_TRISTATE; 1734 } else { 1735 struct parport_pc_private *priv = pb->private_data; 1736 priv->ctr_writable &= ~0x20; 1737 } 1738 1739 return ok; 1740 } 1741 1742 #ifdef CONFIG_PARPORT_PC_FIFO 1743 static int __devinit parport_ECP_supported(struct parport *pb) 1744 { 1745 int i; 1746 int config, configb; 1747 int pword; 1748 struct parport_pc_private *priv = pb->private_data; 1749 /* Translate ECP intrLine to ISA irq value */ 1750 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 }; 1751 1752 /* If there is no ECR, we have no hope of supporting ECP. */ 1753 if (!priv->ecr) 1754 return 0; 1755 1756 /* Find out FIFO depth */ 1757 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1758 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */ 1759 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++) 1760 outb (0xaa, FIFO (pb)); 1761 1762 /* 1763 * Using LGS chipset it uses ECR register, but 1764 * it doesn't support ECP or FIFO MODE 1765 */ 1766 if (i == 1024) { 1767 ECR_WRITE (pb, ECR_SPP << 5); 1768 return 0; 1769 } 1770 1771 priv->fifo_depth = i; 1772 if (verbose_probing) 1773 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); 1774 1775 /* Find out writeIntrThreshold */ 1776 frob_econtrol (pb, 1<<2, 1<<2); 1777 frob_econtrol (pb, 1<<2, 0); 1778 for (i = 1; i <= priv->fifo_depth; i++) { 1779 inb (FIFO (pb)); 1780 udelay (50); 1781 if (inb (ECONTROL (pb)) & (1<<2)) 1782 break; 1783 } 1784 1785 if (i <= priv->fifo_depth) { 1786 if (verbose_probing) 1787 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", 1788 pb->base, i); 1789 } else 1790 /* Number of bytes we know we can write if we get an 1791 interrupt. */ 1792 i = 0; 1793 1794 priv->writeIntrThreshold = i; 1795 1796 /* Find out readIntrThreshold */ 1797 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */ 1798 parport_pc_data_reverse (pb); /* Must be in PS2 mode */ 1799 frob_set_mode (pb, ECR_TST); /* Test FIFO */ 1800 frob_econtrol (pb, 1<<2, 1<<2); 1801 frob_econtrol (pb, 1<<2, 0); 1802 for (i = 1; i <= priv->fifo_depth; i++) { 1803 outb (0xaa, FIFO (pb)); 1804 if (inb (ECONTROL (pb)) & (1<<2)) 1805 break; 1806 } 1807 1808 if (i <= priv->fifo_depth) { 1809 if (verbose_probing) 1810 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n", 1811 pb->base, i); 1812 } else 1813 /* Number of bytes we can read if we get an interrupt. */ 1814 i = 0; 1815 1816 priv->readIntrThreshold = i; 1817 1818 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1819 ECR_WRITE (pb, 0xf4); /* Configuration mode */ 1820 config = inb (CONFIGA (pb)); 1821 pword = (config >> 4) & 0x7; 1822 switch (pword) { 1823 case 0: 1824 pword = 2; 1825 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1826 pb->base); 1827 break; 1828 case 2: 1829 pword = 4; 1830 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1831 pb->base); 1832 break; 1833 default: 1834 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n", 1835 pb->base); 1836 /* Assume 1 */ 1837 case 1: 1838 pword = 1; 1839 } 1840 priv->pword = pword; 1841 1842 if (verbose_probing) { 1843 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword); 1844 1845 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, 1846 config & 0x80 ? "Level" : "Pulses"); 1847 1848 configb = inb (CONFIGB (pb)); 1849 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", 1850 pb->base, config, configb); 1851 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); 1852 if ((configb >>3) & 0x07) 1853 printk("%d",intrline[(configb >>3) & 0x07]); 1854 else 1855 printk("<none or set by other means>"); 1856 printk (" dma="); 1857 if( (configb & 0x03 ) == 0x00) 1858 printk("<none or set by other means>\n"); 1859 else 1860 printk("%d\n",configb & 0x07); 1861 } 1862 1863 /* Go back to mode 000 */ 1864 frob_set_mode (pb, ECR_SPP); 1865 1866 return 1; 1867 } 1868 #endif 1869 1870 static int parport_ECPPS2_supported(struct parport *pb) 1871 { 1872 const struct parport_pc_private *priv = pb->private_data; 1873 int result; 1874 unsigned char oecr; 1875 1876 if (!priv->ecr) 1877 return 0; 1878 1879 oecr = inb (ECONTROL (pb)); 1880 ECR_WRITE (pb, ECR_PS2 << 5); 1881 result = parport_PS2_supported(pb); 1882 ECR_WRITE (pb, oecr); 1883 return result; 1884 } 1885 1886 /* EPP mode detection */ 1887 1888 static int parport_EPP_supported(struct parport *pb) 1889 { 1890 const struct parport_pc_private *priv = pb->private_data; 1891 1892 /* 1893 * Theory: 1894 * Bit 0 of STR is the EPP timeout bit, this bit is 0 1895 * when EPP is possible and is set high when an EPP timeout 1896 * occurs (EPP uses the HALT line to stop the CPU while it does 1897 * the byte transfer, an EPP timeout occurs if the attached 1898 * device fails to respond after 10 micro seconds). 1899 * 1900 * This bit is cleared by either reading it (National Semi) 1901 * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? 1902 * This bit is always high in non EPP modes. 1903 */ 1904 1905 /* If EPP timeout bit clear then EPP available */ 1906 if (!clear_epp_timeout(pb)) { 1907 return 0; /* No way to clear timeout */ 1908 } 1909 1910 /* Check for Intel bug. */ 1911 if (priv->ecr) { 1912 unsigned char i; 1913 for (i = 0x00; i < 0x80; i += 0x20) { 1914 ECR_WRITE (pb, i); 1915 if (clear_epp_timeout (pb)) { 1916 /* Phony EPP in ECP. */ 1917 return 0; 1918 } 1919 } 1920 } 1921 1922 pb->modes |= PARPORT_MODE_EPP; 1923 1924 /* Set up access functions to use EPP hardware. */ 1925 pb->ops->epp_read_data = parport_pc_epp_read_data; 1926 pb->ops->epp_write_data = parport_pc_epp_write_data; 1927 pb->ops->epp_read_addr = parport_pc_epp_read_addr; 1928 pb->ops->epp_write_addr = parport_pc_epp_write_addr; 1929 1930 return 1; 1931 } 1932 1933 static int parport_ECPEPP_supported(struct parport *pb) 1934 { 1935 struct parport_pc_private *priv = pb->private_data; 1936 int result; 1937 unsigned char oecr; 1938 1939 if (!priv->ecr) { 1940 return 0; 1941 } 1942 1943 oecr = inb (ECONTROL (pb)); 1944 /* Search for SMC style EPP+ECP mode */ 1945 ECR_WRITE (pb, 0x80); 1946 outb (0x04, CONTROL (pb)); 1947 result = parport_EPP_supported(pb); 1948 1949 ECR_WRITE (pb, oecr); 1950 1951 if (result) { 1952 /* Set up access functions to use ECP+EPP hardware. */ 1953 pb->ops->epp_read_data = parport_pc_ecpepp_read_data; 1954 pb->ops->epp_write_data = parport_pc_ecpepp_write_data; 1955 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; 1956 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; 1957 } 1958 1959 return result; 1960 } 1961 1962 #else /* No IEEE 1284 support */ 1963 1964 /* Don't bother probing for modes we know we won't use. */ 1965 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } 1966 #ifdef CONFIG_PARPORT_PC_FIFO 1967 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; } 1968 #endif 1969 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; } 1970 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;} 1971 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;} 1972 1973 #endif /* No IEEE 1284 support */ 1974 1975 /* --- IRQ detection -------------------------------------- */ 1976 1977 /* Only if supports ECP mode */ 1978 static int __devinit programmable_irq_support(struct parport *pb) 1979 { 1980 int irq, intrLine; 1981 unsigned char oecr = inb (ECONTROL (pb)); 1982 static const int lookup[8] = { 1983 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 1984 }; 1985 1986 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */ 1987 1988 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07; 1989 irq = lookup[intrLine]; 1990 1991 ECR_WRITE (pb, oecr); 1992 return irq; 1993 } 1994 1995 static int __devinit irq_probe_ECP(struct parport *pb) 1996 { 1997 int i; 1998 unsigned long irqs; 1999 2000 irqs = probe_irq_on(); 2001 2002 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 2003 ECR_WRITE (pb, (ECR_TST << 5) | 0x04); 2004 ECR_WRITE (pb, ECR_TST << 5); 2005 2006 /* If Full FIFO sure that writeIntrThreshold is generated */ 2007 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) 2008 outb (0xaa, FIFO (pb)); 2009 2010 pb->irq = probe_irq_off(irqs); 2011 ECR_WRITE (pb, ECR_SPP << 5); 2012 2013 if (pb->irq <= 0) 2014 pb->irq = PARPORT_IRQ_NONE; 2015 2016 return pb->irq; 2017 } 2018 2019 /* 2020 * This detection seems that only works in National Semiconductors 2021 * This doesn't work in SMC, LGS, and Winbond 2022 */ 2023 static int __devinit irq_probe_EPP(struct parport *pb) 2024 { 2025 #ifndef ADVANCED_DETECT 2026 return PARPORT_IRQ_NONE; 2027 #else 2028 int irqs; 2029 unsigned char oecr; 2030 2031 if (pb->modes & PARPORT_MODE_PCECR) 2032 oecr = inb (ECONTROL (pb)); 2033 2034 irqs = probe_irq_on(); 2035 2036 if (pb->modes & PARPORT_MODE_PCECR) 2037 frob_econtrol (pb, 0x10, 0x10); 2038 2039 clear_epp_timeout(pb); 2040 parport_pc_frob_control (pb, 0x20, 0x20); 2041 parport_pc_frob_control (pb, 0x10, 0x10); 2042 clear_epp_timeout(pb); 2043 2044 /* Device isn't expecting an EPP read 2045 * and generates an IRQ. 2046 */ 2047 parport_pc_read_epp(pb); 2048 udelay(20); 2049 2050 pb->irq = probe_irq_off (irqs); 2051 if (pb->modes & PARPORT_MODE_PCECR) 2052 ECR_WRITE (pb, oecr); 2053 parport_pc_write_control(pb, 0xc); 2054 2055 if (pb->irq <= 0) 2056 pb->irq = PARPORT_IRQ_NONE; 2057 2058 return pb->irq; 2059 #endif /* Advanced detection */ 2060 } 2061 2062 static int __devinit irq_probe_SPP(struct parport *pb) 2063 { 2064 /* Don't even try to do this. */ 2065 return PARPORT_IRQ_NONE; 2066 } 2067 2068 /* We will attempt to share interrupt requests since other devices 2069 * such as sound cards and network cards seem to like using the 2070 * printer IRQs. 2071 * 2072 * When ECP is available we can autoprobe for IRQs. 2073 * NOTE: If we can autoprobe it, we can register the IRQ. 2074 */ 2075 static int parport_irq_probe(struct parport *pb) 2076 { 2077 struct parport_pc_private *priv = pb->private_data; 2078 2079 if (priv->ecr) { 2080 pb->irq = programmable_irq_support(pb); 2081 2082 if (pb->irq == PARPORT_IRQ_NONE) 2083 pb->irq = irq_probe_ECP(pb); 2084 } 2085 2086 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && 2087 (pb->modes & PARPORT_MODE_EPP)) 2088 pb->irq = irq_probe_EPP(pb); 2089 2090 clear_epp_timeout(pb); 2091 2092 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) 2093 pb->irq = irq_probe_EPP(pb); 2094 2095 clear_epp_timeout(pb); 2096 2097 if (pb->irq == PARPORT_IRQ_NONE) 2098 pb->irq = irq_probe_SPP(pb); 2099 2100 if (pb->irq == PARPORT_IRQ_NONE) 2101 pb->irq = get_superio_irq(pb); 2102 2103 return pb->irq; 2104 } 2105 2106 /* --- DMA detection -------------------------------------- */ 2107 2108 /* Only if chipset conforms to ECP ISA Interface Standard */ 2109 static int __devinit programmable_dma_support (struct parport *p) 2110 { 2111 unsigned char oecr = inb (ECONTROL (p)); 2112 int dma; 2113 2114 frob_set_mode (p, ECR_CNF); 2115 2116 dma = inb (CONFIGB(p)) & 0x07; 2117 /* 000: Indicates jumpered 8-bit DMA if read-only. 2118 100: Indicates jumpered 16-bit DMA if read-only. */ 2119 if ((dma & 0x03) == 0) 2120 dma = PARPORT_DMA_NONE; 2121 2122 ECR_WRITE (p, oecr); 2123 return dma; 2124 } 2125 2126 static int __devinit parport_dma_probe (struct parport *p) 2127 { 2128 const struct parport_pc_private *priv = p->private_data; 2129 if (priv->ecr) 2130 p->dma = programmable_dma_support(p); /* ask ECP chipset first */ 2131 if (p->dma == PARPORT_DMA_NONE) { 2132 /* ask known Super-IO chips proper, although these 2133 claim ECP compatible, some don't report their DMA 2134 conforming to ECP standards */ 2135 p->dma = get_superio_dma(p); 2136 } 2137 2138 return p->dma; 2139 } 2140 2141 /* --- Initialisation code -------------------------------- */ 2142 2143 static LIST_HEAD(ports_list); 2144 static DEFINE_SPINLOCK(ports_lock); 2145 2146 struct parport *parport_pc_probe_port (unsigned long int base, 2147 unsigned long int base_hi, 2148 int irq, int dma, 2149 struct pci_dev *dev) 2150 { 2151 struct parport_pc_private *priv; 2152 struct parport_operations *ops; 2153 struct parport *p; 2154 int probedirq = PARPORT_IRQ_NONE; 2155 struct resource *base_res; 2156 struct resource *ECR_res = NULL; 2157 struct resource *EPP_res = NULL; 2158 2159 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL); 2160 if (!ops) 2161 goto out1; 2162 2163 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL); 2164 if (!priv) 2165 goto out2; 2166 2167 /* a misnomer, actually - it's allocate and reserve parport number */ 2168 p = parport_register_port(base, irq, dma, ops); 2169 if (!p) 2170 goto out3; 2171 2172 base_res = request_region(base, 3, p->name); 2173 if (!base_res) 2174 goto out4; 2175 2176 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations)); 2177 priv->ctr = 0xc; 2178 priv->ctr_writable = ~0x10; 2179 priv->ecr = 0; 2180 priv->fifo_depth = 0; 2181 priv->dma_buf = NULL; 2182 priv->dma_handle = 0; 2183 priv->dev = dev; 2184 INIT_LIST_HEAD(&priv->list); 2185 priv->port = p; 2186 p->base_hi = base_hi; 2187 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2188 p->private_data = priv; 2189 2190 if (base_hi) { 2191 ECR_res = request_region(base_hi, 3, p->name); 2192 if (ECR_res) 2193 parport_ECR_present(p); 2194 } 2195 2196 if (base != 0x3bc) { 2197 EPP_res = request_region(base+0x3, 5, p->name); 2198 if (EPP_res) 2199 if (!parport_EPP_supported(p)) 2200 parport_ECPEPP_supported(p); 2201 } 2202 if (!parport_SPP_supported (p)) 2203 /* No port. */ 2204 goto out5; 2205 if (priv->ecr) 2206 parport_ECPPS2_supported(p); 2207 else 2208 parport_PS2_supported(p); 2209 2210 p->size = (p->modes & PARPORT_MODE_EPP)?8:3; 2211 2212 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); 2213 if (p->base_hi && priv->ecr) 2214 printk(" (0x%lx)", p->base_hi); 2215 if (p->irq == PARPORT_IRQ_AUTO) { 2216 p->irq = PARPORT_IRQ_NONE; 2217 parport_irq_probe(p); 2218 } else if (p->irq == PARPORT_IRQ_PROBEONLY) { 2219 p->irq = PARPORT_IRQ_NONE; 2220 parport_irq_probe(p); 2221 probedirq = p->irq; 2222 p->irq = PARPORT_IRQ_NONE; 2223 } 2224 if (p->irq != PARPORT_IRQ_NONE) { 2225 printk(", irq %d", p->irq); 2226 priv->ctr_writable |= 0x10; 2227 2228 if (p->dma == PARPORT_DMA_AUTO) { 2229 p->dma = PARPORT_DMA_NONE; 2230 parport_dma_probe(p); 2231 } 2232 } 2233 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq 2234 is mandatory (see above) */ 2235 p->dma = PARPORT_DMA_NONE; 2236 2237 #ifdef CONFIG_PARPORT_PC_FIFO 2238 if (parport_ECP_supported(p) && 2239 p->dma != PARPORT_DMA_NOFIFO && 2240 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { 2241 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; 2242 p->ops->compat_write_data = parport_pc_compat_write_block_pio; 2243 #ifdef CONFIG_PARPORT_1284 2244 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; 2245 /* currently broken, but working on it.. (FB) */ 2246 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ 2247 #endif /* IEEE 1284 support */ 2248 if (p->dma != PARPORT_DMA_NONE) { 2249 printk(", dma %d", p->dma); 2250 p->modes |= PARPORT_MODE_DMA; 2251 } 2252 else printk(", using FIFO"); 2253 } 2254 else 2255 /* We can't use the DMA channel after all. */ 2256 p->dma = PARPORT_DMA_NONE; 2257 #endif /* Allowed to use FIFO/DMA */ 2258 2259 printk(" ["); 2260 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}} 2261 { 2262 int f = 0; 2263 printmode(PCSPP); 2264 printmode(TRISTATE); 2265 printmode(COMPAT) 2266 printmode(EPP); 2267 printmode(ECP); 2268 printmode(DMA); 2269 } 2270 #undef printmode 2271 #ifndef CONFIG_PARPORT_1284 2272 printk ("(,...)"); 2273 #endif /* CONFIG_PARPORT_1284 */ 2274 printk("]\n"); 2275 if (probedirq != PARPORT_IRQ_NONE) 2276 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); 2277 2278 /* If No ECP release the ports grabbed above. */ 2279 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { 2280 release_region(base_hi, 3); 2281 ECR_res = NULL; 2282 } 2283 /* Likewise for EEP ports */ 2284 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { 2285 release_region(base+3, 5); 2286 EPP_res = NULL; 2287 } 2288 if (p->irq != PARPORT_IRQ_NONE) { 2289 if (request_irq (p->irq, parport_pc_interrupt, 2290 0, p->name, p)) { 2291 printk (KERN_WARNING "%s: irq %d in use, " 2292 "resorting to polled operation\n", 2293 p->name, p->irq); 2294 p->irq = PARPORT_IRQ_NONE; 2295 p->dma = PARPORT_DMA_NONE; 2296 } 2297 2298 #ifdef CONFIG_PARPORT_PC_FIFO 2299 #ifdef HAS_DMA 2300 if (p->dma != PARPORT_DMA_NONE) { 2301 if (request_dma (p->dma, p->name)) { 2302 printk (KERN_WARNING "%s: dma %d in use, " 2303 "resorting to PIO operation\n", 2304 p->name, p->dma); 2305 p->dma = PARPORT_DMA_NONE; 2306 } else { 2307 priv->dma_buf = 2308 pci_alloc_consistent(priv->dev, 2309 PAGE_SIZE, 2310 &priv->dma_handle); 2311 if (! priv->dma_buf) { 2312 printk (KERN_WARNING "%s: " 2313 "cannot get buffer for DMA, " 2314 "resorting to PIO operation\n", 2315 p->name); 2316 free_dma(p->dma); 2317 p->dma = PARPORT_DMA_NONE; 2318 } 2319 } 2320 } 2321 #endif 2322 #endif 2323 } 2324 2325 /* Done probing. Now put the port into a sensible start-up state. */ 2326 if (priv->ecr) 2327 /* 2328 * Put the ECP detected port in PS2 mode. 2329 * Do this also for ports that have ECR but don't do ECP. 2330 */ 2331 ECR_WRITE (p, 0x34); 2332 2333 parport_pc_write_data(p, 0); 2334 parport_pc_data_forward (p); 2335 2336 /* Now that we've told the sharing engine about the port, and 2337 found out its characteristics, let the high-level drivers 2338 know about it. */ 2339 spin_lock(&ports_lock); 2340 list_add(&priv->list, &ports_list); 2341 spin_unlock(&ports_lock); 2342 parport_announce_port (p); 2343 2344 return p; 2345 2346 out5: 2347 if (ECR_res) 2348 release_region(base_hi, 3); 2349 if (EPP_res) 2350 release_region(base+0x3, 5); 2351 release_region(base, 3); 2352 out4: 2353 parport_put_port(p); 2354 out3: 2355 kfree (priv); 2356 out2: 2357 kfree (ops); 2358 out1: 2359 return NULL; 2360 } 2361 2362 EXPORT_SYMBOL (parport_pc_probe_port); 2363 2364 void parport_pc_unregister_port (struct parport *p) 2365 { 2366 struct parport_pc_private *priv = p->private_data; 2367 struct parport_operations *ops = p->ops; 2368 2369 parport_remove_port(p); 2370 spin_lock(&ports_lock); 2371 list_del_init(&priv->list); 2372 spin_unlock(&ports_lock); 2373 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2374 if (p->dma != PARPORT_DMA_NONE) 2375 free_dma(p->dma); 2376 #endif 2377 if (p->irq != PARPORT_IRQ_NONE) 2378 free_irq(p->irq, p); 2379 release_region(p->base, 3); 2380 if (p->size > 3) 2381 release_region(p->base + 3, p->size - 3); 2382 if (p->modes & PARPORT_MODE_ECP) 2383 release_region(p->base_hi, 3); 2384 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2385 if (priv->dma_buf) 2386 pci_free_consistent(priv->dev, PAGE_SIZE, 2387 priv->dma_buf, 2388 priv->dma_handle); 2389 #endif 2390 kfree (p->private_data); 2391 parport_put_port(p); 2392 kfree (ops); /* hope no-one cached it */ 2393 } 2394 2395 EXPORT_SYMBOL (parport_pc_unregister_port); 2396 2397 #ifdef CONFIG_PCI 2398 2399 /* ITE support maintained by Rich Liu <richliu@poorman.org> */ 2400 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq, 2401 int autodma, 2402 const struct parport_pc_via_data *via) 2403 { 2404 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; 2405 struct resource *base_res; 2406 u32 ite8872set; 2407 u32 ite8872_lpt, ite8872_lpthi; 2408 u8 ite8872_irq, type; 2409 char *fake_name = "parport probe"; 2410 int irq; 2411 int i; 2412 2413 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n"); 2414 2415 // make sure which one chip 2416 for(i = 0; i < 5; i++) { 2417 base_res = request_region(inta_addr[i], 0x8, fake_name); 2418 if (base_res) { 2419 int test; 2420 pci_write_config_dword (pdev, 0x60, 2421 0xe7000000 | inta_addr[i]); 2422 pci_write_config_dword (pdev, 0x78, 2423 0x00000000 | inta_addr[i]); 2424 test = inb (inta_addr[i]); 2425 if (test != 0xff) break; 2426 release_region(inta_addr[i], 0x8); 2427 } 2428 } 2429 if(i >= 5) { 2430 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); 2431 return 0; 2432 } 2433 2434 type = inb (inta_addr[i] + 0x18); 2435 type &= 0x0f; 2436 2437 switch (type) { 2438 case 0x2: 2439 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n"); 2440 ite8872set = 0x64200000; 2441 break; 2442 case 0xa: 2443 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n"); 2444 ite8872set = 0x64200000; 2445 break; 2446 case 0xe: 2447 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); 2448 ite8872set = 0x64e00000; 2449 break; 2450 case 0x6: 2451 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n"); 2452 return 0; 2453 case 0x8: 2454 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); 2455 return 0; 2456 default: 2457 printk (KERN_INFO "parport_pc: unknown ITE887x\n"); 2458 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' " 2459 "output to Rich.Liu@ite.com.tw\n"); 2460 return 0; 2461 } 2462 2463 pci_read_config_byte (pdev, 0x3c, &ite8872_irq); 2464 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt); 2465 ite8872_lpt &= 0x0000ff00; 2466 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi); 2467 ite8872_lpthi &= 0x0000ff00; 2468 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt); 2469 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi); 2470 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); 2471 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function 2472 // SET Parallel IRQ 2473 pci_write_config_dword (pdev, 0x9c, 2474 ite8872set | (ite8872_irq * 0x11111)); 2475 2476 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); 2477 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", 2478 ite8872_lpt); 2479 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", 2480 ite8872_lpthi); 2481 2482 /* Let the user (or defaults) steer us away from interrupts */ 2483 irq = ite8872_irq; 2484 if (autoirq != PARPORT_IRQ_AUTO) 2485 irq = PARPORT_IRQ_NONE; 2486 2487 /* 2488 * Release the resource so that parport_pc_probe_port can get it. 2489 */ 2490 release_resource(base_res); 2491 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi, 2492 irq, PARPORT_DMA_NONE, NULL)) { 2493 printk (KERN_INFO 2494 "parport_pc: ITE 8872 parallel port: io=0x%X", 2495 ite8872_lpt); 2496 if (irq != PARPORT_IRQ_NONE) 2497 printk (", irq=%d", irq); 2498 printk ("\n"); 2499 return 1; 2500 } 2501 2502 return 0; 2503 } 2504 2505 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> 2506 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ 2507 static int __devinitdata parport_init_mode = 0; 2508 2509 /* Data for two known VIA chips */ 2510 static struct parport_pc_via_data via_686a_data __devinitdata = { 2511 0x51, 2512 0x50, 2513 0x85, 2514 0x02, 2515 0xE2, 2516 0xF0, 2517 0xE6 2518 }; 2519 static struct parport_pc_via_data via_8231_data __devinitdata = { 2520 0x45, 2521 0x44, 2522 0x50, 2523 0x04, 2524 0xF2, 2525 0xFA, 2526 0xF6 2527 }; 2528 2529 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq, 2530 int autodma, 2531 const struct parport_pc_via_data *via) 2532 { 2533 u8 tmp, tmp2, siofunc; 2534 u8 ppcontrol = 0; 2535 int dma, irq; 2536 unsigned port1, port2; 2537 unsigned have_epp = 0; 2538 2539 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); 2540 2541 switch(parport_init_mode) 2542 { 2543 case 1: 2544 printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); 2545 siofunc = VIA_FUNCTION_PARPORT_SPP; 2546 break; 2547 case 2: 2548 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); 2549 siofunc = VIA_FUNCTION_PARPORT_SPP; 2550 ppcontrol = VIA_PARPORT_BIDIR; 2551 break; 2552 case 3: 2553 printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); 2554 siofunc = VIA_FUNCTION_PARPORT_EPP; 2555 ppcontrol = VIA_PARPORT_BIDIR; 2556 have_epp = 1; 2557 break; 2558 case 4: 2559 printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); 2560 siofunc = VIA_FUNCTION_PARPORT_ECP; 2561 ppcontrol = VIA_PARPORT_BIDIR; 2562 break; 2563 case 5: 2564 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); 2565 siofunc = VIA_FUNCTION_PARPORT_ECP; 2566 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; 2567 have_epp = 1; 2568 break; 2569 default: 2570 printk(KERN_DEBUG "parport_pc: probing current configuration\n"); 2571 siofunc = VIA_FUNCTION_PROBE; 2572 break; 2573 } 2574 /* 2575 * unlock super i/o configuration 2576 */ 2577 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2578 tmp |= via->via_pci_superio_config_data; 2579 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2580 2581 /* Bits 1-0: Parallel Port Mode / Enable */ 2582 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2583 tmp = inb (VIA_CONFIG_DATA); 2584 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ 2585 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2586 tmp2 = inb (VIA_CONFIG_DATA); 2587 if (siofunc == VIA_FUNCTION_PROBE) 2588 { 2589 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; 2590 ppcontrol = tmp2; 2591 } 2592 else 2593 { 2594 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; 2595 tmp |= siofunc; 2596 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2597 outb(tmp, VIA_CONFIG_DATA); 2598 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); 2599 tmp2 |= ppcontrol; 2600 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2601 outb(tmp2, VIA_CONFIG_DATA); 2602 } 2603 2604 /* Parallel Port I/O Base Address, bits 9-2 */ 2605 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2606 port1 = inb(VIA_CONFIG_DATA) << 2; 2607 2608 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1); 2609 if ((port1 == 0x3BC) && have_epp) 2610 { 2611 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2612 outb((0x378 >> 2), VIA_CONFIG_DATA); 2613 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); 2614 port1 = 0x378; 2615 } 2616 2617 /* 2618 * lock super i/o configuration 2619 */ 2620 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2621 tmp &= ~via->via_pci_superio_config_data; 2622 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2623 2624 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { 2625 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); 2626 return 0; 2627 } 2628 2629 /* Bits 7-4: PnP Routing for Parallel Port IRQ */ 2630 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); 2631 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); 2632 2633 if (siofunc == VIA_FUNCTION_PARPORT_ECP) 2634 { 2635 /* Bits 3-2: PnP Routing for Parallel Port DMA */ 2636 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); 2637 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); 2638 } 2639 else 2640 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */ 2641 dma = PARPORT_DMA_NONE; 2642 2643 /* Let the user (or defaults) steer us away from interrupts and DMA */ 2644 if (autoirq == PARPORT_IRQ_NONE) { 2645 irq = PARPORT_IRQ_NONE; 2646 dma = PARPORT_DMA_NONE; 2647 } 2648 if (autodma == PARPORT_DMA_NONE) 2649 dma = PARPORT_DMA_NONE; 2650 2651 switch (port1) { 2652 case 0x3bc: port2 = 0x7bc; break; 2653 case 0x378: port2 = 0x778; break; 2654 case 0x278: port2 = 0x678; break; 2655 default: 2656 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n", 2657 port1); 2658 return 0; 2659 } 2660 2661 /* filter bogus IRQs */ 2662 switch (irq) { 2663 case 0: 2664 case 2: 2665 case 8: 2666 case 13: 2667 irq = PARPORT_IRQ_NONE; 2668 break; 2669 2670 default: /* do nothing */ 2671 break; 2672 } 2673 2674 /* finally, do the probe with values obtained */ 2675 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) { 2676 printk (KERN_INFO 2677 "parport_pc: VIA parallel port: io=0x%X", port1); 2678 if (irq != PARPORT_IRQ_NONE) 2679 printk (", irq=%d", irq); 2680 if (dma != PARPORT_DMA_NONE) 2681 printk (", dma=%d", dma); 2682 printk ("\n"); 2683 return 1; 2684 } 2685 2686 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", 2687 port1, irq, dma); 2688 return 0; 2689 } 2690 2691 2692 enum parport_pc_sio_types { 2693 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ 2694 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ 2695 sio_ite_8872, 2696 last_sio 2697 }; 2698 2699 /* each element directly indexed from enum list, above */ 2700 static struct parport_pc_superio { 2701 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, 2702 const struct parport_pc_via_data *via); 2703 const struct parport_pc_via_data *via; 2704 } parport_pc_superio_info[] __devinitdata = { 2705 { sio_via_probe, &via_686a_data, }, 2706 { sio_via_probe, &via_8231_data, }, 2707 { sio_ite_8872_probe, NULL, }, 2708 }; 2709 2710 enum parport_pc_pci_cards { 2711 siig_1p_10x = last_sio, 2712 siig_2p_10x, 2713 siig_1p_20x, 2714 siig_2p_20x, 2715 lava_parallel, 2716 lava_parallel_dual_a, 2717 lava_parallel_dual_b, 2718 boca_ioppar, 2719 plx_9050, 2720 timedia_4078a, 2721 timedia_4079h, 2722 timedia_4085h, 2723 timedia_4088a, 2724 timedia_4089a, 2725 timedia_4095a, 2726 timedia_4096a, 2727 timedia_4078u, 2728 timedia_4079a, 2729 timedia_4085u, 2730 timedia_4079r, 2731 timedia_4079s, 2732 timedia_4079d, 2733 timedia_4079e, 2734 timedia_4079f, 2735 timedia_9079a, 2736 timedia_9079b, 2737 timedia_9079c, 2738 timedia_4006a, 2739 timedia_4014, 2740 timedia_4008a, 2741 timedia_4018, 2742 timedia_9018a, 2743 syba_2p_epp, 2744 syba_1p_ecp, 2745 titan_010l, 2746 titan_1284p1, 2747 titan_1284p2, 2748 avlab_1p, 2749 avlab_2p, 2750 oxsemi_954, 2751 oxsemi_840, 2752 aks_0100, 2753 mobility_pp, 2754 netmos_9705, 2755 netmos_9715, 2756 netmos_9755, 2757 netmos_9805, 2758 netmos_9815, 2759 }; 2760 2761 2762 /* each element directly indexed from enum list, above 2763 * (but offset by last_sio) */ 2764 static struct parport_pc_pci { 2765 int numports; 2766 struct { /* BAR (base address registers) numbers in the config 2767 space header */ 2768 int lo; 2769 int hi; /* -1 if not there, >6 for offset-method (max 2770 BAR is 6) */ 2771 } addr[4]; 2772 2773 /* If set, this is called immediately after pci_enable_device. 2774 * If it returns non-zero, no probing will take place and the 2775 * ports will not be used. */ 2776 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); 2777 2778 /* If set, this is called after probing for ports. If 'failed' 2779 * is non-zero we couldn't use any of the ports. */ 2780 void (*postinit_hook) (struct pci_dev *pdev, int failed); 2781 } cards[] = { 2782 /* siig_1p_10x */ { 1, { { 2, 3 }, } }, 2783 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2784 /* siig_1p_20x */ { 1, { { 0, 1 }, } }, 2785 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2786 /* lava_parallel */ { 1, { { 0, -1 }, } }, 2787 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, 2788 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, 2789 /* boca_ioppar */ { 1, { { 0, -1 }, } }, 2790 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, 2791 /* timedia_4078a */ { 1, { { 2, -1 }, } }, 2792 /* timedia_4079h */ { 1, { { 2, 3 }, } }, 2793 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2794 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2795 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2796 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2797 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2798 /* timedia_4078u */ { 1, { { 2, -1 }, } }, 2799 /* timedia_4079a */ { 1, { { 2, 3 }, } }, 2800 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2801 /* timedia_4079r */ { 1, { { 2, 3 }, } }, 2802 /* timedia_4079s */ { 1, { { 2, 3 }, } }, 2803 /* timedia_4079d */ { 1, { { 2, 3 }, } }, 2804 /* timedia_4079e */ { 1, { { 2, 3 }, } }, 2805 /* timedia_4079f */ { 1, { { 2, 3 }, } }, 2806 /* timedia_9079a */ { 1, { { 2, 3 }, } }, 2807 /* timedia_9079b */ { 1, { { 2, 3 }, } }, 2808 /* timedia_9079c */ { 1, { { 2, 3 }, } }, 2809 /* timedia_4006a */ { 1, { { 0, -1 }, } }, 2810 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, 2811 /* timedia_4008a */ { 1, { { 0, 1 }, } }, 2812 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2813 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2814 /* SYBA uses fixed offsets in 2815 a 1K io window */ 2816 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, 2817 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, 2818 /* titan_010l */ { 1, { { 3, -1 }, } }, 2819 /* titan_1284p1 */ { 1, { { 0, 1 }, } }, 2820 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2821 /* avlab_1p */ { 1, { { 0, 1}, } }, 2822 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, 2823 /* The Oxford Semi cards are unusual: 954 doesn't support ECP, 2824 * and 840 locks up if you write 1 to bit 2! */ 2825 /* oxsemi_954 */ { 1, { { 0, -1 }, } }, 2826 /* oxsemi_840 */ { 1, { { 0, -1 }, } }, 2827 /* aks_0100 */ { 1, { { 0, -1 }, } }, 2828 /* mobility_pp */ { 1, { { 0, 1 }, } }, 2829 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */ 2830 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2831 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2832 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */ 2833 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */ 2834 }; 2835 2836 static const struct pci_device_id parport_pc_pci_tbl[] = { 2837 /* Super-IO onboard chips */ 2838 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, 2839 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, 2840 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, 2842 2843 /* PCI cards */ 2844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, 2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, 2846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, 2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, 2848 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, 2849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, 2850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, 2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, 2852 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, 2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, 2854 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, 2855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, 2856 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, 2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, 2858 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, 2859 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, 2860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2861 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 }, 2862 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ 2863 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, 2864 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, 2865 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, 2866 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, 2867 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, 2868 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, 2869 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, 2870 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, 2871 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, 2872 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, 2873 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, 2874 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, 2875 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, 2876 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, 2877 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, 2878 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, 2879 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, 2880 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, 2881 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, 2882 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, 2883 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, 2884 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, 2885 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, 2886 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, 2887 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, 2888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, 2889 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, 2890 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, 2891 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, 2892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, 2893 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, 2894 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, 2895 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ 2896 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */ 2897 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, 2898 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, 2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, 2900 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, 2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, 2902 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, 2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, 2904 /* NetMos communication controllers */ 2905 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, 2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, 2907 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, 2908 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, 2909 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, 2910 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, 2911 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, 2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, 2913 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, 2914 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, 2915 { 0, } /* terminate list */ 2916 }; 2917 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl); 2918 2919 struct pci_parport_data { 2920 int num; 2921 struct parport *ports[2]; 2922 }; 2923 2924 static int parport_pc_pci_probe (struct pci_dev *dev, 2925 const struct pci_device_id *id) 2926 { 2927 int err, count, n, i = id->driver_data; 2928 struct pci_parport_data *data; 2929 2930 if (i < last_sio) 2931 /* This is an onboard Super-IO and has already been probed */ 2932 return 0; 2933 2934 /* This is a PCI card */ 2935 i -= last_sio; 2936 count = 0; 2937 if ((err = pci_enable_device (dev)) != 0) 2938 return err; 2939 2940 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); 2941 if (!data) 2942 return -ENOMEM; 2943 2944 if (cards[i].preinit_hook && 2945 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { 2946 kfree(data); 2947 return -ENODEV; 2948 } 2949 2950 for (n = 0; n < cards[i].numports; n++) { 2951 int lo = cards[i].addr[n].lo; 2952 int hi = cards[i].addr[n].hi; 2953 unsigned long io_lo, io_hi; 2954 io_lo = pci_resource_start (dev, lo); 2955 io_hi = 0; 2956 if ((hi >= 0) && (hi <= 6)) 2957 io_hi = pci_resource_start (dev, hi); 2958 else if (hi > 6) 2959 io_lo += hi; /* Reinterpret the meaning of 2960 "hi" as an offset (see SYBA 2961 def.) */ 2962 /* TODO: test if sharing interrupts works */ 2963 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, " 2964 "I/O at %#lx(%#lx)\n", 2965 parport_pc_pci_tbl[i + last_sio].vendor, 2966 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi); 2967 data->ports[count] = 2968 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE, 2969 PARPORT_DMA_NONE, dev); 2970 if (data->ports[count]) 2971 count++; 2972 } 2973 2974 data->num = count; 2975 2976 if (cards[i].postinit_hook) 2977 cards[i].postinit_hook (dev, count == 0); 2978 2979 if (count) { 2980 pci_set_drvdata(dev, data); 2981 return 0; 2982 } 2983 2984 kfree(data); 2985 2986 return -ENODEV; 2987 } 2988 2989 static void __devexit parport_pc_pci_remove(struct pci_dev *dev) 2990 { 2991 struct pci_parport_data *data = pci_get_drvdata(dev); 2992 int i; 2993 2994 pci_set_drvdata(dev, NULL); 2995 2996 if (data) { 2997 for (i = data->num - 1; i >= 0; i--) 2998 parport_pc_unregister_port(data->ports[i]); 2999 3000 kfree(data); 3001 } 3002 } 3003 3004 static struct pci_driver parport_pc_pci_driver = { 3005 .name = "parport_pc", 3006 .id_table = parport_pc_pci_tbl, 3007 .probe = parport_pc_pci_probe, 3008 .remove = __devexit_p(parport_pc_pci_remove), 3009 }; 3010 3011 static int __init parport_pc_init_superio (int autoirq, int autodma) 3012 { 3013 const struct pci_device_id *id; 3014 struct pci_dev *pdev = NULL; 3015 int ret = 0; 3016 3017 for_each_pci_dev(pdev) { 3018 id = pci_match_id(parport_pc_pci_tbl, pdev); 3019 if (id == NULL || id->driver_data >= last_sio) 3020 continue; 3021 3022 if (parport_pc_superio_info[id->driver_data].probe 3023 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) { 3024 ret++; 3025 } 3026 } 3027 3028 return ret; /* number of devices found */ 3029 } 3030 #else 3031 static struct pci_driver parport_pc_pci_driver; 3032 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;} 3033 #endif /* CONFIG_PCI */ 3034 3035 3036 static const struct pnp_device_id parport_pc_pnp_tbl[] = { 3037 /* Standard LPT Printer Port */ 3038 {.id = "PNP0400", .driver_data = 0}, 3039 /* ECP Printer Port */ 3040 {.id = "PNP0401", .driver_data = 0}, 3041 { } 3042 }; 3043 3044 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl); 3045 3046 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) 3047 { 3048 struct parport *pdata; 3049 unsigned long io_lo, io_hi; 3050 int dma, irq; 3051 3052 if (pnp_port_valid(dev,0) && 3053 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) { 3054 io_lo = pnp_port_start(dev,0); 3055 } else 3056 return -EINVAL; 3057 3058 if (pnp_port_valid(dev,1) && 3059 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) { 3060 io_hi = pnp_port_start(dev,1); 3061 } else 3062 io_hi = 0; 3063 3064 if (pnp_irq_valid(dev,0) && 3065 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) { 3066 irq = pnp_irq(dev,0); 3067 } else 3068 irq = PARPORT_IRQ_NONE; 3069 3070 if (pnp_dma_valid(dev,0) && 3071 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) { 3072 dma = pnp_dma(dev,0); 3073 } else 3074 dma = PARPORT_DMA_NONE; 3075 3076 printk(KERN_INFO "parport: PnPBIOS parport detected.\n"); 3077 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL))) 3078 return -ENODEV; 3079 3080 pnp_set_drvdata(dev,pdata); 3081 return 0; 3082 } 3083 3084 static void parport_pc_pnp_remove(struct pnp_dev *dev) 3085 { 3086 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); 3087 if (!pdata) 3088 return; 3089 3090 parport_pc_unregister_port(pdata); 3091 } 3092 3093 /* we only need the pnp layer to activate the device, at least for now */ 3094 static struct pnp_driver parport_pc_pnp_driver = { 3095 .name = "parport_pc", 3096 .id_table = parport_pc_pnp_tbl, 3097 .probe = parport_pc_pnp_probe, 3098 .remove = parport_pc_pnp_remove, 3099 }; 3100 3101 3102 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ 3103 static int __devinit __attribute__((unused)) 3104 parport_pc_find_isa_ports (int autoirq, int autodma) 3105 { 3106 int count = 0; 3107 3108 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL)) 3109 count++; 3110 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL)) 3111 count++; 3112 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL)) 3113 count++; 3114 3115 return count; 3116 } 3117 3118 /* This function is called by parport_pc_init if the user didn't 3119 * specify any ports to probe. Its job is to find some ports. Order 3120 * is important here -- we want ISA ports to be registered first, 3121 * followed by PCI cards (for least surprise), but before that we want 3122 * to do chipset-specific tests for some onboard ports that we know 3123 * about. 3124 * 3125 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY 3126 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO 3127 */ 3128 static void __init parport_pc_find_ports (int autoirq, int autodma) 3129 { 3130 int count = 0, err; 3131 3132 #ifdef CONFIG_PARPORT_PC_SUPERIO 3133 detect_and_report_winbond (); 3134 detect_and_report_smsc (); 3135 #endif 3136 3137 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ 3138 count += parport_pc_init_superio (autoirq, autodma); 3139 3140 /* PnP ports, skip detection if SuperIO already found them */ 3141 if (!count) { 3142 err = pnp_register_driver (&parport_pc_pnp_driver); 3143 if (!err) 3144 pnp_registered_parport = 1; 3145 } 3146 3147 /* ISA ports and whatever (see asm/parport.h). */ 3148 parport_pc_find_nonpci_ports (autoirq, autodma); 3149 3150 err = pci_register_driver (&parport_pc_pci_driver); 3151 if (!err) 3152 pci_registered_parport = 1; 3153 } 3154 3155 /* 3156 * Piles of crap below pretend to be a parser for module and kernel 3157 * parameters. Say "thank you" to whoever had come up with that 3158 * syntax and keep in mind that code below is a cleaned up version. 3159 */ 3160 3161 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 }; 3162 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = 3163 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO }; 3164 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE }; 3165 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY }; 3166 3167 static int __init parport_parse_param(const char *s, int *val, 3168 int automatic, int none, int nofifo) 3169 { 3170 if (!s) 3171 return 0; 3172 if (!strncmp(s, "auto", 4)) 3173 *val = automatic; 3174 else if (!strncmp(s, "none", 4)) 3175 *val = none; 3176 else if (nofifo && !strncmp(s, "nofifo", 4)) 3177 *val = nofifo; 3178 else { 3179 char *ep; 3180 unsigned long r = simple_strtoul(s, &ep, 0); 3181 if (ep != s) 3182 *val = r; 3183 else { 3184 printk(KERN_ERR "parport: bad specifier `%s'\n", s); 3185 return -1; 3186 } 3187 } 3188 return 0; 3189 } 3190 3191 static int __init parport_parse_irq(const char *irqstr, int *val) 3192 { 3193 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, 3194 PARPORT_IRQ_NONE, 0); 3195 } 3196 3197 static int __init parport_parse_dma(const char *dmastr, int *val) 3198 { 3199 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, 3200 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); 3201 } 3202 3203 #ifdef CONFIG_PCI 3204 static int __init parport_init_mode_setup(char *str) 3205 { 3206 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); 3207 3208 if (!strcmp (str, "spp")) 3209 parport_init_mode=1; 3210 if (!strcmp (str, "ps2")) 3211 parport_init_mode=2; 3212 if (!strcmp (str, "epp")) 3213 parport_init_mode=3; 3214 if (!strcmp (str, "ecp")) 3215 parport_init_mode=4; 3216 if (!strcmp (str, "ecpepp")) 3217 parport_init_mode=5; 3218 return 1; 3219 } 3220 #endif 3221 3222 #ifdef MODULE 3223 static const char *irq[PARPORT_PC_MAX_PORTS]; 3224 static const char *dma[PARPORT_PC_MAX_PORTS]; 3225 3226 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); 3227 module_param_array(io, int, NULL, 0); 3228 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); 3229 module_param_array(io_hi, int, NULL, 0); 3230 MODULE_PARM_DESC(irq, "IRQ line"); 3231 module_param_array(irq, charp, NULL, 0); 3232 MODULE_PARM_DESC(dma, "DMA channel"); 3233 module_param_array(dma, charp, NULL, 0); 3234 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 3235 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 3236 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); 3237 module_param(verbose_probing, int, 0644); 3238 #endif 3239 #ifdef CONFIG_PCI 3240 static char *init_mode; 3241 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); 3242 module_param(init_mode, charp, 0); 3243 #endif 3244 3245 static int __init parse_parport_params(void) 3246 { 3247 unsigned int i; 3248 int val; 3249 3250 #ifdef CONFIG_PCI 3251 if (init_mode) 3252 parport_init_mode_setup(init_mode); 3253 #endif 3254 3255 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { 3256 if (parport_parse_irq(irq[i], &val)) 3257 return 1; 3258 irqval[i] = val; 3259 if (parport_parse_dma(dma[i], &val)) 3260 return 1; 3261 dmaval[i] = val; 3262 } 3263 if (!io[0]) { 3264 /* The user can make us use any IRQs or DMAs we find. */ 3265 if (irq[0] && !parport_parse_irq(irq[0], &val)) 3266 switch (val) { 3267 case PARPORT_IRQ_NONE: 3268 case PARPORT_IRQ_AUTO: 3269 irqval[0] = val; 3270 break; 3271 default: 3272 printk (KERN_WARNING 3273 "parport_pc: irq specified " 3274 "without base address. Use 'io=' " 3275 "to specify one\n"); 3276 } 3277 3278 if (dma[0] && !parport_parse_dma(dma[0], &val)) 3279 switch (val) { 3280 case PARPORT_DMA_NONE: 3281 case PARPORT_DMA_AUTO: 3282 dmaval[0] = val; 3283 break; 3284 default: 3285 printk (KERN_WARNING 3286 "parport_pc: dma specified " 3287 "without base address. Use 'io=' " 3288 "to specify one\n"); 3289 } 3290 } 3291 return 0; 3292 } 3293 3294 #else 3295 3296 static int parport_setup_ptr __initdata = 0; 3297 3298 /* 3299 * Acceptable parameters: 3300 * 3301 * parport=0 3302 * parport=auto 3303 * parport=0xBASE[,IRQ[,DMA]] 3304 * 3305 * IRQ/DMA may be numeric or 'auto' or 'none' 3306 */ 3307 static int __init parport_setup (char *str) 3308 { 3309 char *endptr; 3310 char *sep; 3311 int val; 3312 3313 if (!str || !*str || (*str == '0' && !*(str+1))) { 3314 /* Disable parport if "parport=0" in cmdline */ 3315 io[0] = PARPORT_DISABLE; 3316 return 1; 3317 } 3318 3319 if (!strncmp (str, "auto", 4)) { 3320 irqval[0] = PARPORT_IRQ_AUTO; 3321 dmaval[0] = PARPORT_DMA_AUTO; 3322 return 1; 3323 } 3324 3325 val = simple_strtoul (str, &endptr, 0); 3326 if (endptr == str) { 3327 printk (KERN_WARNING "parport=%s not understood\n", str); 3328 return 1; 3329 } 3330 3331 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { 3332 printk(KERN_ERR "parport=%s ignored, too many ports\n", str); 3333 return 1; 3334 } 3335 3336 io[parport_setup_ptr] = val; 3337 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; 3338 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; 3339 3340 sep = strchr(str, ','); 3341 if (sep++) { 3342 if (parport_parse_irq(sep, &val)) 3343 return 1; 3344 irqval[parport_setup_ptr] = val; 3345 sep = strchr(sep, ','); 3346 if (sep++) { 3347 if (parport_parse_dma(sep, &val)) 3348 return 1; 3349 dmaval[parport_setup_ptr] = val; 3350 } 3351 } 3352 parport_setup_ptr++; 3353 return 1; 3354 } 3355 3356 static int __init parse_parport_params(void) 3357 { 3358 return io[0] == PARPORT_DISABLE; 3359 } 3360 3361 __setup ("parport=", parport_setup); 3362 3363 /* 3364 * Acceptable parameters: 3365 * 3366 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] 3367 */ 3368 #ifdef CONFIG_PCI 3369 __setup("parport_init_mode=",parport_init_mode_setup); 3370 #endif 3371 #endif 3372 3373 /* "Parser" ends here */ 3374 3375 static int __init parport_pc_init(void) 3376 { 3377 if (parse_parport_params()) 3378 return -EINVAL; 3379 3380 if (io[0]) { 3381 int i; 3382 /* Only probe the ports we were given. */ 3383 user_specified = 1; 3384 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { 3385 if (!io[i]) 3386 break; 3387 if ((io_hi[i]) == PARPORT_IOHI_AUTO) 3388 io_hi[i] = 0x400 + io[i]; 3389 parport_pc_probe_port(io[i], io_hi[i], 3390 irqval[i], dmaval[i], NULL); 3391 } 3392 } else 3393 parport_pc_find_ports (irqval[0], dmaval[0]); 3394 3395 return 0; 3396 } 3397 3398 static void __exit parport_pc_exit(void) 3399 { 3400 if (pci_registered_parport) 3401 pci_unregister_driver (&parport_pc_pci_driver); 3402 if (pnp_registered_parport) 3403 pnp_unregister_driver (&parport_pc_pnp_driver); 3404 3405 spin_lock(&ports_lock); 3406 while (!list_empty(&ports_list)) { 3407 struct parport_pc_private *priv; 3408 struct parport *port; 3409 priv = list_entry(ports_list.next, 3410 struct parport_pc_private, list); 3411 port = priv->port; 3412 spin_unlock(&ports_lock); 3413 parport_pc_unregister_port(port); 3414 spin_lock(&ports_lock); 3415 } 3416 spin_unlock(&ports_lock); 3417 } 3418 3419 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); 3420 MODULE_DESCRIPTION("PC-style parallel port driver"); 3421 MODULE_LICENSE("GPL"); 3422 module_init(parport_pc_init) 3423 module_exit(parport_pc_exit) 3424