1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 ** System Bus Adapter (SBA) I/O MMU manager 4 ** 5 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 6 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 7 ** (c) Copyright 2000-2004 Hewlett-Packard Company 8 ** 9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 10 ** 11 ** 12 ** 13 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 14 ** J5000/J7000/N-class/L-class machines and their successors. 15 ** 16 ** FIXME: add DMA hint support programming in both sba and lba modules. 17 */ 18 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/spinlock.h> 22 #include <linux/slab.h> 23 #include <linux/init.h> 24 25 #include <linux/mm.h> 26 #include <linux/string.h> 27 #include <linux/pci.h> 28 #include <linux/scatterlist.h> 29 #include <linux/iommu-helper.h> 30 31 #include <asm/byteorder.h> 32 #include <asm/io.h> 33 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 34 35 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 36 37 #include <linux/proc_fs.h> 38 #include <linux/seq_file.h> 39 #include <linux/module.h> 40 41 #include <asm/ropes.h> 42 #include <asm/mckinley.h> /* for proc_mckinley_root */ 43 #include <asm/runway.h> /* for proc_runway_root */ 44 #include <asm/page.h> /* for PAGE0 */ 45 #include <asm/pdc.h> /* for PDC_MODEL_* */ 46 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 47 #include <asm/parisc-device.h> 48 49 #include "iommu.h" 50 51 #define MODULE_NAME "SBA" 52 53 /* 54 ** The number of debug flags is a clue - this code is fragile. 55 ** Don't even think about messing with it unless you have 56 ** plenty of 710's to sacrifice to the computer gods. :^) 57 */ 58 #undef DEBUG_SBA_INIT 59 #undef DEBUG_SBA_RUN 60 #undef DEBUG_SBA_RUN_SG 61 #undef DEBUG_SBA_RESOURCE 62 #undef ASSERT_PDIR_SANITY 63 #undef DEBUG_LARGE_SG_ENTRIES 64 #undef DEBUG_DMB_TRAP 65 66 #ifdef DEBUG_SBA_INIT 67 #define DBG_INIT(x...) printk(x) 68 #else 69 #define DBG_INIT(x...) 70 #endif 71 72 #ifdef DEBUG_SBA_RUN 73 #define DBG_RUN(x...) printk(x) 74 #else 75 #define DBG_RUN(x...) 76 #endif 77 78 #ifdef DEBUG_SBA_RUN_SG 79 #define DBG_RUN_SG(x...) printk(x) 80 #else 81 #define DBG_RUN_SG(x...) 82 #endif 83 84 85 #ifdef DEBUG_SBA_RESOURCE 86 #define DBG_RES(x...) printk(x) 87 #else 88 #define DBG_RES(x...) 89 #endif 90 91 #define SBA_INLINE __inline__ 92 93 #define DEFAULT_DMA_HINT_REG 0 94 95 struct sba_device *sba_list; 96 EXPORT_SYMBOL_GPL(sba_list); 97 98 static unsigned long ioc_needs_fdc = 0; 99 100 /* global count of IOMMUs in the system */ 101 static unsigned int global_ioc_cnt = 0; 102 103 /* PA8700 (Piranha 2.2) bug workaround */ 104 static unsigned long piranha_bad_128k = 0; 105 106 /* Looks nice and keeps the compiler happy */ 107 #define SBA_DEV(d) ((struct sba_device *) (d)) 108 109 #ifdef CONFIG_AGP_PARISC 110 #define SBA_AGP_SUPPORT 111 #endif /*CONFIG_AGP_PARISC*/ 112 113 #ifdef SBA_AGP_SUPPORT 114 static int sba_reserve_agpgart = 1; 115 module_param(sba_reserve_agpgart, int, 0444); 116 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 117 #endif 118 119 120 /************************************ 121 ** SBA register read and write support 122 ** 123 ** BE WARNED: register writes are posted. 124 ** (ie follow writes which must reach HW with a read) 125 ** 126 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 127 */ 128 #define READ_REG32(addr) readl(addr) 129 #define READ_REG64(addr) readq(addr) 130 #define WRITE_REG32(val, addr) writel((val), (addr)) 131 #define WRITE_REG64(val, addr) writeq((val), (addr)) 132 133 #ifdef CONFIG_64BIT 134 #define READ_REG(addr) READ_REG64(addr) 135 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 136 #else 137 #define READ_REG(addr) READ_REG32(addr) 138 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 139 #endif 140 141 #ifdef DEBUG_SBA_INIT 142 143 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 144 145 /** 146 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 147 * @hpa: base address of the sba 148 * 149 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 150 * IO Adapter (aka Bus Converter). 151 */ 152 static void 153 sba_dump_ranges(void __iomem *hpa) 154 { 155 DBG_INIT("SBA at 0x%p\n", hpa); 156 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 157 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 158 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 159 DBG_INIT("\n"); 160 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 161 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 162 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 163 } 164 165 /** 166 * sba_dump_tlb - debugging only - print IOMMU operating parameters 167 * @hpa: base address of the IOMMU 168 * 169 * Print the size/location of the IO MMU PDIR. 170 */ 171 static void sba_dump_tlb(void __iomem *hpa) 172 { 173 DBG_INIT("IO TLB at 0x%p\n", hpa); 174 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 175 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 176 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 177 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 178 DBG_INIT("\n"); 179 } 180 #else 181 #define sba_dump_ranges(x) 182 #define sba_dump_tlb(x) 183 #endif /* DEBUG_SBA_INIT */ 184 185 186 #ifdef ASSERT_PDIR_SANITY 187 188 /** 189 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 190 * @ioc: IO MMU structure which owns the pdir we are interested in. 191 * @msg: text to print ont the output line. 192 * @pide: pdir index. 193 * 194 * Print one entry of the IO MMU PDIR in human readable form. 195 */ 196 static void 197 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 198 { 199 /* start printing from lowest pde in rval */ 200 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 201 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 202 uint rcnt; 203 204 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 205 msg, 206 rptr, pide & (BITS_PER_LONG - 1), *rptr); 207 208 rcnt = 0; 209 while (rcnt < BITS_PER_LONG) { 210 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 211 (rcnt == (pide & (BITS_PER_LONG - 1))) 212 ? " -->" : " ", 213 rcnt, ptr, *ptr ); 214 rcnt++; 215 ptr++; 216 } 217 printk(KERN_DEBUG "%s", msg); 218 } 219 220 221 /** 222 * sba_check_pdir - debugging only - consistency checker 223 * @ioc: IO MMU structure which owns the pdir we are interested in. 224 * @msg: text to print ont the output line. 225 * 226 * Verify the resource map and pdir state is consistent 227 */ 228 static int 229 sba_check_pdir(struct ioc *ioc, char *msg) 230 { 231 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 232 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 233 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 234 uint pide = 0; 235 236 while (rptr < rptr_end) { 237 u32 rval = *rptr; 238 int rcnt = 32; /* number of bits we might check */ 239 240 while (rcnt) { 241 /* Get last byte and highest bit from that */ 242 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 243 if ((rval ^ pde) & 0x80000000) 244 { 245 /* 246 ** BUMMER! -- res_map != pdir -- 247 ** Dump rval and matching pdir entries 248 */ 249 sba_dump_pdir_entry(ioc, msg, pide); 250 return(1); 251 } 252 rcnt--; 253 rval <<= 1; /* try the next bit */ 254 pptr++; 255 pide++; 256 } 257 rptr++; /* look at next word of res_map */ 258 } 259 /* It'd be nice if we always got here :^) */ 260 return 0; 261 } 262 263 264 /** 265 * sba_dump_sg - debugging only - print Scatter-Gather list 266 * @ioc: IO MMU structure which owns the pdir we are interested in. 267 * @startsg: head of the SG list 268 * @nents: number of entries in SG list 269 * 270 * print the SG list so we can verify it's correct by hand. 271 */ 272 static void 273 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 274 { 275 while (nents-- > 0) { 276 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 277 nents, 278 (unsigned long) sg_dma_address(startsg), 279 sg_dma_len(startsg), 280 sg_virt(startsg), startsg->length); 281 startsg++; 282 } 283 } 284 285 #endif /* ASSERT_PDIR_SANITY */ 286 287 288 289 290 /************************************************************** 291 * 292 * I/O Pdir Resource Management 293 * 294 * Bits set in the resource map are in use. 295 * Each bit can represent a number of pages. 296 * LSbs represent lower addresses (IOVA's). 297 * 298 ***************************************************************/ 299 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 300 301 /* Convert from IOVP to IOVA and vice versa. */ 302 303 #ifdef ZX1_SUPPORT 304 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 305 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 306 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 307 #else 308 /* only support Astro and ancestors. Saves a few cycles in key places */ 309 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 310 #define SBA_IOVP(ioc,iova) (iova) 311 #endif 312 313 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 314 315 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 316 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 317 318 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, 319 unsigned int bitshiftcnt) 320 { 321 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) 322 + bitshiftcnt; 323 } 324 325 /** 326 * sba_search_bitmap - find free space in IO PDIR resource bitmap 327 * @ioc: IO MMU structure which owns the pdir we are interested in. 328 * @bits_wanted: number of entries we need. 329 * 330 * Find consecutive free bits in resource bitmap. 331 * Each bit represents one entry in the IO Pdir. 332 * Cool perf optimization: search for log2(size) bits at a time. 333 */ 334 static SBA_INLINE unsigned long 335 sba_search_bitmap(struct ioc *ioc, struct device *dev, 336 unsigned long bits_wanted) 337 { 338 unsigned long *res_ptr = ioc->res_hint; 339 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 340 unsigned long pide = ~0UL, tpide; 341 unsigned long boundary_size; 342 unsigned long shift; 343 int ret; 344 345 boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT); 346 347 #if defined(ZX1_SUPPORT) 348 BUG_ON(ioc->ibase & ~IOVP_MASK); 349 shift = ioc->ibase >> IOVP_SHIFT; 350 #else 351 shift = 0; 352 #endif 353 354 if (bits_wanted > (BITS_PER_LONG/2)) { 355 /* Search word at a time - no mask needed */ 356 for(; res_ptr < res_end; ++res_ptr) { 357 tpide = ptr_to_pide(ioc, res_ptr, 0); 358 ret = iommu_is_span_boundary(tpide, bits_wanted, 359 shift, 360 boundary_size); 361 if ((*res_ptr == 0) && !ret) { 362 *res_ptr = RESMAP_MASK(bits_wanted); 363 pide = tpide; 364 break; 365 } 366 } 367 /* point to the next word on next pass */ 368 res_ptr++; 369 ioc->res_bitshift = 0; 370 } else { 371 /* 372 ** Search the resource bit map on well-aligned values. 373 ** "o" is the alignment. 374 ** We need the alignment to invalidate I/O TLB using 375 ** SBA HW features in the unmap path. 376 */ 377 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 378 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 379 unsigned long mask; 380 381 if (bitshiftcnt >= BITS_PER_LONG) { 382 bitshiftcnt = 0; 383 res_ptr++; 384 } 385 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 386 387 DBG_RES("%s() o %ld %p", __func__, o, res_ptr); 388 while(res_ptr < res_end) 389 { 390 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 391 WARN_ON(mask == 0); 392 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); 393 ret = iommu_is_span_boundary(tpide, bits_wanted, 394 shift, 395 boundary_size); 396 if ((((*res_ptr) & mask) == 0) && !ret) { 397 *res_ptr |= mask; /* mark resources busy! */ 398 pide = tpide; 399 break; 400 } 401 mask >>= o; 402 bitshiftcnt += o; 403 if (mask == 0) { 404 mask = RESMAP_MASK(bits_wanted); 405 bitshiftcnt=0; 406 res_ptr++; 407 } 408 } 409 /* look in the same word on the next pass */ 410 ioc->res_bitshift = bitshiftcnt + bits_wanted; 411 } 412 413 /* wrapped ? */ 414 if (res_end <= res_ptr) { 415 ioc->res_hint = (unsigned long *) ioc->res_map; 416 ioc->res_bitshift = 0; 417 } else { 418 ioc->res_hint = res_ptr; 419 } 420 return (pide); 421 } 422 423 424 /** 425 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 426 * @ioc: IO MMU structure which owns the pdir we are interested in. 427 * @size: number of bytes to create a mapping for 428 * 429 * Given a size, find consecutive unmarked and then mark those bits in the 430 * resource bit map. 431 */ 432 static int 433 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 434 { 435 unsigned int pages_needed = size >> IOVP_SHIFT; 436 #ifdef SBA_COLLECT_STATS 437 unsigned long cr_start = mfctl(16); 438 #endif 439 unsigned long pide; 440 441 pide = sba_search_bitmap(ioc, dev, pages_needed); 442 if (pide >= (ioc->res_size << 3)) { 443 pide = sba_search_bitmap(ioc, dev, pages_needed); 444 if (pide >= (ioc->res_size << 3)) 445 panic("%s: I/O MMU @ %p is out of mapping resources\n", 446 __FILE__, ioc->ioc_hpa); 447 } 448 449 #ifdef ASSERT_PDIR_SANITY 450 /* verify the first enable bit is clear */ 451 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 452 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 453 } 454 #endif 455 456 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 457 __func__, size, pages_needed, pide, 458 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 459 ioc->res_bitshift ); 460 461 #ifdef SBA_COLLECT_STATS 462 { 463 unsigned long cr_end = mfctl(16); 464 unsigned long tmp = cr_end - cr_start; 465 /* check for roll over */ 466 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 467 } 468 ioc->avg_search[ioc->avg_idx++] = cr_start; 469 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 470 471 ioc->used_pages += pages_needed; 472 #endif 473 474 return (pide); 475 } 476 477 478 /** 479 * sba_free_range - unmark bits in IO PDIR resource bitmap 480 * @ioc: IO MMU structure which owns the pdir we are interested in. 481 * @iova: IO virtual address which was previously allocated. 482 * @size: number of bytes to create a mapping for 483 * 484 * clear bits in the ioc's resource map 485 */ 486 static SBA_INLINE void 487 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 488 { 489 unsigned long iovp = SBA_IOVP(ioc, iova); 490 unsigned int pide = PDIR_INDEX(iovp); 491 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 492 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 493 494 int bits_not_wanted = size >> IOVP_SHIFT; 495 496 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 497 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 498 499 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 500 __func__, (uint) iova, size, 501 bits_not_wanted, m, pide, res_ptr, *res_ptr); 502 503 #ifdef SBA_COLLECT_STATS 504 ioc->used_pages -= bits_not_wanted; 505 #endif 506 507 *res_ptr &= ~m; 508 } 509 510 511 /************************************************************** 512 * 513 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 514 * 515 ***************************************************************/ 516 517 #ifdef SBA_HINT_SUPPORT 518 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 519 #endif 520 521 typedef unsigned long space_t; 522 #define KERNEL_SPACE 0 523 524 /** 525 * sba_io_pdir_entry - fill in one IO PDIR entry 526 * @pdir_ptr: pointer to IO PDIR entry 527 * @sid: process Space ID - currently only support KERNEL_SPACE 528 * @vba: Virtual CPU address of buffer to map 529 * @hint: DMA hint set to use for this mapping 530 * 531 * SBA Mapping Routine 532 * 533 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 534 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 535 * pdir_ptr (arg0). 536 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 537 * for Astro/Ike looks like: 538 * 539 * 540 * 0 19 51 55 63 541 * +-+---------------------+----------------------------------+----+--------+ 542 * |V| U | PPN[43:12] | U | VI | 543 * +-+---------------------+----------------------------------+----+--------+ 544 * 545 * Pluto is basically identical, supports fewer physical address bits: 546 * 547 * 0 23 51 55 63 548 * +-+------------------------+-------------------------------+----+--------+ 549 * |V| U | PPN[39:12] | U | VI | 550 * +-+------------------------+-------------------------------+----+--------+ 551 * 552 * V == Valid Bit (Most Significant Bit is bit 0) 553 * U == Unused 554 * PPN == Physical Page Number 555 * VI == Virtual Index (aka Coherent Index) 556 * 557 * LPA instruction output is put into PPN field. 558 * LCI (Load Coherence Index) instruction provides the "VI" bits. 559 * 560 * We pre-swap the bytes since PCX-W is Big Endian and the 561 * IOMMU uses little endian for the pdir. 562 */ 563 564 static void SBA_INLINE 565 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 566 unsigned long hint) 567 { 568 u64 pa; /* physical address */ 569 register unsigned ci; /* coherent index */ 570 571 pa = lpa(vba); 572 pa &= IOVP_MASK; 573 574 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba)); 575 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */ 576 577 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 578 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 579 580 /* 581 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 582 * (bit #61, big endian), we have to flush and sync every time 583 * IO-PDIR is changed in Ike/Astro. 584 */ 585 asm_io_fdc(pdir_ptr); 586 } 587 588 589 /** 590 * sba_mark_invalid - invalidate one or more IO PDIR entries 591 * @ioc: IO MMU structure which owns the pdir we are interested in. 592 * @iova: IO Virtual Address mapped earlier 593 * @byte_cnt: number of bytes this mapping covers. 594 * 595 * Marking the IO PDIR entry(ies) as Invalid and invalidate 596 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 597 * is to purge stale entries in the IO TLB when unmapping entries. 598 * 599 * The PCOM register supports purging of multiple pages, with a minium 600 * of 1 page and a maximum of 2GB. Hardware requires the address be 601 * aligned to the size of the range being purged. The size of the range 602 * must be a power of 2. The "Cool perf optimization" in the 603 * allocation routine helps keep that true. 604 */ 605 static SBA_INLINE void 606 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 607 { 608 u32 iovp = (u32) SBA_IOVP(ioc,iova); 609 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 610 611 #ifdef ASSERT_PDIR_SANITY 612 /* Assert first pdir entry is set. 613 ** 614 ** Even though this is a big-endian machine, the entries 615 ** in the iopdir are little endian. That's why we look at 616 ** the byte at +7 instead of at +0. 617 */ 618 if (0x80 != (((u8 *) pdir_ptr)[7])) { 619 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 620 } 621 #endif 622 623 if (byte_cnt > IOVP_SIZE) 624 { 625 #if 0 626 unsigned long entries_per_cacheline = ioc_needs_fdc ? 627 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 628 - (unsigned long) pdir_ptr; 629 : 262144; 630 #endif 631 632 /* set "size" field for PCOM */ 633 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 634 635 do { 636 /* clear I/O Pdir entry "valid" bit first */ 637 ((u8 *) pdir_ptr)[7] = 0; 638 asm_io_fdc(pdir_ptr); 639 if (ioc_needs_fdc) { 640 #if 0 641 entries_per_cacheline = L1_CACHE_SHIFT - 3; 642 #endif 643 } 644 pdir_ptr++; 645 byte_cnt -= IOVP_SIZE; 646 } while (byte_cnt > IOVP_SIZE); 647 } else 648 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 649 650 /* 651 ** clear I/O PDIR entry "valid" bit. 652 ** We have to R/M/W the cacheline regardless how much of the 653 ** pdir entry that we clobber. 654 ** The rest of the entry would be useful for debugging if we 655 ** could dump core on HPMC. 656 */ 657 ((u8 *) pdir_ptr)[7] = 0; 658 asm_io_fdc(pdir_ptr); 659 660 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 661 } 662 663 /** 664 * sba_dma_supported - PCI driver can query DMA support 665 * @dev: instance of PCI owned by the driver that's asking 666 * @mask: number of address bits this PCI device can handle 667 * 668 * See Documentation/core-api/dma-api-howto.rst 669 */ 670 static int sba_dma_supported( struct device *dev, u64 mask) 671 { 672 struct ioc *ioc; 673 674 if (dev == NULL) { 675 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 676 BUG(); 677 return(0); 678 } 679 680 ioc = GET_IOC(dev); 681 if (!ioc) 682 return 0; 683 684 /* 685 * check if mask is >= than the current max IO Virt Address 686 * The max IO Virt address will *always* < 30 bits. 687 */ 688 return((int)(mask >= (ioc->ibase - 1 + 689 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 690 } 691 692 693 /** 694 * sba_map_single - map one buffer and return IOVA for DMA 695 * @dev: instance of PCI owned by the driver that's asking. 696 * @addr: driver buffer to map. 697 * @size: number of bytes to map in driver buffer. 698 * @direction: R/W or both. 699 * 700 * See Documentation/core-api/dma-api-howto.rst 701 */ 702 static dma_addr_t 703 sba_map_single(struct device *dev, void *addr, size_t size, 704 enum dma_data_direction direction) 705 { 706 struct ioc *ioc; 707 unsigned long flags; 708 dma_addr_t iovp; 709 dma_addr_t offset; 710 u64 *pdir_start; 711 int pide; 712 713 ioc = GET_IOC(dev); 714 if (!ioc) 715 return DMA_MAPPING_ERROR; 716 717 /* save offset bits */ 718 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 719 720 /* round up to nearest IOVP_SIZE */ 721 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 722 723 spin_lock_irqsave(&ioc->res_lock, flags); 724 #ifdef ASSERT_PDIR_SANITY 725 sba_check_pdir(ioc,"Check before sba_map_single()"); 726 #endif 727 728 #ifdef SBA_COLLECT_STATS 729 ioc->msingle_calls++; 730 ioc->msingle_pages += size >> IOVP_SHIFT; 731 #endif 732 pide = sba_alloc_range(ioc, dev, size); 733 iovp = (dma_addr_t) pide << IOVP_SHIFT; 734 735 DBG_RUN("%s() 0x%p -> 0x%lx\n", 736 __func__, addr, (long) iovp | offset); 737 738 pdir_start = &(ioc->pdir_base[pide]); 739 740 while (size > 0) { 741 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 742 743 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 744 pdir_start, 745 (u8) (((u8 *) pdir_start)[7]), 746 (u8) (((u8 *) pdir_start)[6]), 747 (u8) (((u8 *) pdir_start)[5]), 748 (u8) (((u8 *) pdir_start)[4]), 749 (u8) (((u8 *) pdir_start)[3]), 750 (u8) (((u8 *) pdir_start)[2]), 751 (u8) (((u8 *) pdir_start)[1]), 752 (u8) (((u8 *) pdir_start)[0]) 753 ); 754 755 addr += IOVP_SIZE; 756 size -= IOVP_SIZE; 757 pdir_start++; 758 } 759 760 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 761 asm_io_sync(); 762 763 #ifdef ASSERT_PDIR_SANITY 764 sba_check_pdir(ioc,"Check after sba_map_single()"); 765 #endif 766 spin_unlock_irqrestore(&ioc->res_lock, flags); 767 768 /* form complete address */ 769 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 770 } 771 772 773 static dma_addr_t 774 sba_map_page(struct device *dev, struct page *page, unsigned long offset, 775 size_t size, enum dma_data_direction direction, 776 unsigned long attrs) 777 { 778 return sba_map_single(dev, page_address(page) + offset, size, 779 direction); 780 } 781 782 783 /** 784 * sba_unmap_page - unmap one IOVA and free resources 785 * @dev: instance of PCI owned by the driver that's asking. 786 * @iova: IOVA of driver buffer previously mapped. 787 * @size: number of bytes mapped in driver buffer. 788 * @direction: R/W or both. 789 * 790 * See Documentation/core-api/dma-api-howto.rst 791 */ 792 static void 793 sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size, 794 enum dma_data_direction direction, unsigned long attrs) 795 { 796 struct ioc *ioc; 797 #if DELAYED_RESOURCE_CNT > 0 798 struct sba_dma_pair *d; 799 #endif 800 unsigned long flags; 801 dma_addr_t offset; 802 803 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); 804 805 ioc = GET_IOC(dev); 806 if (!ioc) { 807 WARN_ON(!ioc); 808 return; 809 } 810 offset = iova & ~IOVP_MASK; 811 iova ^= offset; /* clear offset bits */ 812 size += offset; 813 size = ALIGN(size, IOVP_SIZE); 814 815 spin_lock_irqsave(&ioc->res_lock, flags); 816 817 #ifdef SBA_COLLECT_STATS 818 ioc->usingle_calls++; 819 ioc->usingle_pages += size >> IOVP_SHIFT; 820 #endif 821 822 sba_mark_invalid(ioc, iova, size); 823 824 #if DELAYED_RESOURCE_CNT > 0 825 /* Delaying when we re-use a IO Pdir entry reduces the number 826 * of MMIO reads needed to flush writes to the PCOM register. 827 */ 828 d = &(ioc->saved[ioc->saved_cnt]); 829 d->iova = iova; 830 d->size = size; 831 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 832 int cnt = ioc->saved_cnt; 833 while (cnt--) { 834 sba_free_range(ioc, d->iova, d->size); 835 d--; 836 } 837 ioc->saved_cnt = 0; 838 839 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 840 } 841 #else /* DELAYED_RESOURCE_CNT == 0 */ 842 sba_free_range(ioc, iova, size); 843 844 /* If fdc's were issued, force fdc's to be visible now */ 845 asm_io_sync(); 846 847 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 848 #endif /* DELAYED_RESOURCE_CNT == 0 */ 849 850 spin_unlock_irqrestore(&ioc->res_lock, flags); 851 852 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 853 ** For Astro based systems this isn't a big deal WRT performance. 854 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 855 ** we don't need the syncdma. The issue here is I/O MMU cachelines 856 ** are *not* coherent in all cases. May be hwrev dependent. 857 ** Need to investigate more. 858 asm volatile("syncdma"); 859 */ 860 } 861 862 863 /** 864 * sba_alloc - allocate/map shared mem for DMA 865 * @hwdev: instance of PCI owned by the driver that's asking. 866 * @size: number of bytes mapped in driver buffer. 867 * @dma_handle: IOVA of new buffer. 868 * 869 * See Documentation/core-api/dma-api-howto.rst 870 */ 871 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, 872 gfp_t gfp, unsigned long attrs) 873 { 874 void *ret; 875 876 if (!hwdev) { 877 /* only support PCI */ 878 *dma_handle = 0; 879 return NULL; 880 } 881 882 ret = (void *) __get_free_pages(gfp, get_order(size)); 883 884 if (ret) { 885 memset(ret, 0, size); 886 *dma_handle = sba_map_single(hwdev, ret, size, 0); 887 } 888 889 return ret; 890 } 891 892 893 /** 894 * sba_free - free/unmap shared mem for DMA 895 * @hwdev: instance of PCI owned by the driver that's asking. 896 * @size: number of bytes mapped in driver buffer. 897 * @vaddr: virtual address IOVA of "consistent" buffer. 898 * @dma_handler: IO virtual address of "consistent" buffer. 899 * 900 * See Documentation/core-api/dma-api-howto.rst 901 */ 902 static void 903 sba_free(struct device *hwdev, size_t size, void *vaddr, 904 dma_addr_t dma_handle, unsigned long attrs) 905 { 906 sba_unmap_page(hwdev, dma_handle, size, 0, 0); 907 free_pages((unsigned long) vaddr, get_order(size)); 908 } 909 910 911 /* 912 ** Since 0 is a valid pdir_base index value, can't use that 913 ** to determine if a value is valid or not. Use a flag to indicate 914 ** the SG list entry contains a valid pdir index. 915 */ 916 #define PIDE_FLAG 0x80000000UL 917 918 #ifdef SBA_COLLECT_STATS 919 #define IOMMU_MAP_STATS 920 #endif 921 #include "iommu-helpers.h" 922 923 #ifdef DEBUG_LARGE_SG_ENTRIES 924 int dump_run_sg = 0; 925 #endif 926 927 928 /** 929 * sba_map_sg - map Scatter/Gather list 930 * @dev: instance of PCI owned by the driver that's asking. 931 * @sglist: array of buffer/length pairs 932 * @nents: number of entries in list 933 * @direction: R/W or both. 934 * 935 * See Documentation/core-api/dma-api-howto.rst 936 */ 937 static int 938 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 939 enum dma_data_direction direction, unsigned long attrs) 940 { 941 struct ioc *ioc; 942 int coalesced, filled = 0; 943 unsigned long flags; 944 945 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 946 947 ioc = GET_IOC(dev); 948 if (!ioc) 949 return 0; 950 951 /* Fast path single entry scatterlists. */ 952 if (nents == 1) { 953 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist), 954 sglist->length, direction); 955 sg_dma_len(sglist) = sglist->length; 956 return 1; 957 } 958 959 spin_lock_irqsave(&ioc->res_lock, flags); 960 961 #ifdef ASSERT_PDIR_SANITY 962 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 963 { 964 sba_dump_sg(ioc, sglist, nents); 965 panic("Check before sba_map_sg()"); 966 } 967 #endif 968 969 #ifdef SBA_COLLECT_STATS 970 ioc->msg_calls++; 971 #endif 972 973 /* 974 ** First coalesce the chunks and allocate I/O pdir space 975 ** 976 ** If this is one DMA stream, we can properly map using the 977 ** correct virtual address associated with each DMA page. 978 ** w/o this association, we wouldn't have coherent DMA! 979 ** Access to the virtual address is what forces a two pass algorithm. 980 */ 981 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); 982 983 /* 984 ** Program the I/O Pdir 985 ** 986 ** map the virtual addresses to the I/O Pdir 987 ** o dma_address will contain the pdir index 988 ** o dma_len will contain the number of bytes to map 989 ** o address contains the virtual address. 990 */ 991 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 992 993 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 994 asm_io_sync(); 995 996 #ifdef ASSERT_PDIR_SANITY 997 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 998 { 999 sba_dump_sg(ioc, sglist, nents); 1000 panic("Check after sba_map_sg()\n"); 1001 } 1002 #endif 1003 1004 spin_unlock_irqrestore(&ioc->res_lock, flags); 1005 1006 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 1007 1008 return filled; 1009 } 1010 1011 1012 /** 1013 * sba_unmap_sg - unmap Scatter/Gather list 1014 * @dev: instance of PCI owned by the driver that's asking. 1015 * @sglist: array of buffer/length pairs 1016 * @nents: number of entries in list 1017 * @direction: R/W or both. 1018 * 1019 * See Documentation/core-api/dma-api-howto.rst 1020 */ 1021 static void 1022 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1023 enum dma_data_direction direction, unsigned long attrs) 1024 { 1025 struct ioc *ioc; 1026 #ifdef ASSERT_PDIR_SANITY 1027 unsigned long flags; 1028 #endif 1029 1030 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1031 __func__, nents, sg_virt(sglist), sglist->length); 1032 1033 ioc = GET_IOC(dev); 1034 if (!ioc) { 1035 WARN_ON(!ioc); 1036 return; 1037 } 1038 1039 #ifdef SBA_COLLECT_STATS 1040 ioc->usg_calls++; 1041 #endif 1042 1043 #ifdef ASSERT_PDIR_SANITY 1044 spin_lock_irqsave(&ioc->res_lock, flags); 1045 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1046 spin_unlock_irqrestore(&ioc->res_lock, flags); 1047 #endif 1048 1049 while (sg_dma_len(sglist) && nents--) { 1050 1051 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist), 1052 direction, 0); 1053 #ifdef SBA_COLLECT_STATS 1054 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1055 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1056 #endif 1057 ++sglist; 1058 } 1059 1060 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1061 1062 #ifdef ASSERT_PDIR_SANITY 1063 spin_lock_irqsave(&ioc->res_lock, flags); 1064 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1065 spin_unlock_irqrestore(&ioc->res_lock, flags); 1066 #endif 1067 1068 } 1069 1070 static const struct dma_map_ops sba_ops = { 1071 .dma_supported = sba_dma_supported, 1072 .alloc = sba_alloc, 1073 .free = sba_free, 1074 .map_page = sba_map_page, 1075 .unmap_page = sba_unmap_page, 1076 .map_sg = sba_map_sg, 1077 .unmap_sg = sba_unmap_sg, 1078 .get_sgtable = dma_common_get_sgtable, 1079 }; 1080 1081 1082 /************************************************************************** 1083 ** 1084 ** SBA PAT PDC support 1085 ** 1086 ** o call pdc_pat_cell_module() 1087 ** o store ranges in PCI "resource" structures 1088 ** 1089 **************************************************************************/ 1090 1091 static void 1092 sba_get_pat_resources(struct sba_device *sba_dev) 1093 { 1094 #if 0 1095 /* 1096 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1097 ** PAT PDC to program the SBA/LBA directed range registers...this 1098 ** burden may fall on the LBA code since it directly supports the 1099 ** PCI subsystem. It's not clear yet. - ggg 1100 */ 1101 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1102 FIXME : ??? 1103 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1104 Tells where the dvi bits are located in the address. 1105 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1106 FIXME : ??? 1107 #endif 1108 } 1109 1110 1111 /************************************************************** 1112 * 1113 * Initialization and claim 1114 * 1115 ***************************************************************/ 1116 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1117 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1118 static void * 1119 sba_alloc_pdir(unsigned int pdir_size) 1120 { 1121 unsigned long pdir_base; 1122 unsigned long pdir_order = get_order(pdir_size); 1123 1124 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1125 if (NULL == (void *) pdir_base) { 1126 panic("%s() could not allocate I/O Page Table\n", 1127 __func__); 1128 } 1129 1130 /* If this is not PA8700 (PCX-W2) 1131 ** OR newer than ver 2.2 1132 ** OR in a system that doesn't need VINDEX bits from SBA, 1133 ** 1134 ** then we aren't exposed to the HW bug. 1135 */ 1136 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1137 || (boot_cpu_data.pdc.versions > 0x202) 1138 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1139 return (void *) pdir_base; 1140 1141 /* 1142 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1143 * 1144 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1145 * Ike/Astro can cause silent data corruption. This is only 1146 * a problem if the I/O PDIR is located in memory such that 1147 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1148 * 1149 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1150 * right physical address, we can either avoid (IOPDIR <= 1MB) 1151 * or minimize (2MB IO Pdir) the problem if we restrict the 1152 * IO Pdir to a maximum size of 2MB-128K (1902K). 1153 * 1154 * Because we always allocate 2^N sized IO pdirs, either of the 1155 * "bad" regions will be the last 128K if at all. That's easy 1156 * to test for. 1157 * 1158 */ 1159 if (pdir_order <= (19-12)) { 1160 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1161 /* allocate a new one on 512k alignment */ 1162 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1163 /* release original */ 1164 free_pages(pdir_base, pdir_order); 1165 1166 pdir_base = new_pdir; 1167 1168 /* release excess */ 1169 while (pdir_order < (19-12)) { 1170 new_pdir += pdir_size; 1171 free_pages(new_pdir, pdir_order); 1172 pdir_order +=1; 1173 pdir_size <<=1; 1174 } 1175 } 1176 } else { 1177 /* 1178 ** 1MB or 2MB Pdir 1179 ** Needs to be aligned on an "odd" 1MB boundary. 1180 */ 1181 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1182 1183 /* release original */ 1184 free_pages( pdir_base, pdir_order); 1185 1186 /* release first 1MB */ 1187 free_pages(new_pdir, 20-12); 1188 1189 pdir_base = new_pdir + 1024*1024; 1190 1191 if (pdir_order > (20-12)) { 1192 /* 1193 ** 2MB Pdir. 1194 ** 1195 ** Flag tells init_bitmap() to mark bad 128k as used 1196 ** and to reduce the size by 128k. 1197 */ 1198 piranha_bad_128k = 1; 1199 1200 new_pdir += 3*1024*1024; 1201 /* release last 1MB */ 1202 free_pages(new_pdir, 20-12); 1203 1204 /* release unusable 128KB */ 1205 free_pages(new_pdir - 128*1024 , 17-12); 1206 1207 pdir_size -= 128*1024; 1208 } 1209 } 1210 1211 memset((void *) pdir_base, 0, pdir_size); 1212 return (void *) pdir_base; 1213 } 1214 1215 struct ibase_data_struct { 1216 struct ioc *ioc; 1217 int ioc_num; 1218 }; 1219 1220 static int setup_ibase_imask_callback(struct device *dev, void *data) 1221 { 1222 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1223 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1224 struct parisc_device *lba = to_parisc_device(dev); 1225 struct ibase_data_struct *ibd = data; 1226 int rope_num = (lba->hpa.start >> 13) & 0xf; 1227 if (rope_num >> 3 == ibd->ioc_num) 1228 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); 1229 return 0; 1230 } 1231 1232 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1233 static void 1234 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1235 { 1236 struct ibase_data_struct ibase_data = { 1237 .ioc = ioc, 1238 .ioc_num = ioc_num, 1239 }; 1240 1241 device_for_each_child(&sba->dev, &ibase_data, 1242 setup_ibase_imask_callback); 1243 } 1244 1245 #ifdef SBA_AGP_SUPPORT 1246 static int 1247 sba_ioc_find_quicksilver(struct device *dev, void *data) 1248 { 1249 int *agp_found = data; 1250 struct parisc_device *lba = to_parisc_device(dev); 1251 1252 if (IS_QUICKSILVER(lba)) 1253 *agp_found = 1; 1254 return 0; 1255 } 1256 #endif 1257 1258 static void 1259 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1260 { 1261 u32 iova_space_mask; 1262 u32 iova_space_size; 1263 int iov_order, tcnfg; 1264 #ifdef SBA_AGP_SUPPORT 1265 int agp_found = 0; 1266 #endif 1267 /* 1268 ** Firmware programs the base and size of a "safe IOVA space" 1269 ** (one that doesn't overlap memory or LMMIO space) in the 1270 ** IBASE and IMASK registers. 1271 */ 1272 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL; 1273 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1274 1275 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1276 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1277 iova_space_size /= 2; 1278 } 1279 1280 /* 1281 ** iov_order is always based on a 1GB IOVA space since we want to 1282 ** turn on the other half for AGP GART. 1283 */ 1284 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1285 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1286 1287 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1288 __func__, ioc->ioc_hpa, iova_space_size >> 20, 1289 iov_order + PAGE_SHIFT); 1290 1291 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1292 get_order(ioc->pdir_size)); 1293 if (!ioc->pdir_base) 1294 panic("Couldn't allocate I/O Page Table\n"); 1295 1296 memset(ioc->pdir_base, 0, ioc->pdir_size); 1297 1298 DBG_INIT("%s() pdir %p size %x\n", 1299 __func__, ioc->pdir_base, ioc->pdir_size); 1300 1301 #ifdef SBA_HINT_SUPPORT 1302 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1303 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1304 1305 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1306 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1307 #endif 1308 1309 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1310 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1311 1312 /* build IMASK for IOC and Elroy */ 1313 iova_space_mask = 0xffffffff; 1314 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1315 ioc->imask = iova_space_mask; 1316 #ifdef ZX1_SUPPORT 1317 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1318 #endif 1319 sba_dump_tlb(ioc->ioc_hpa); 1320 1321 setup_ibase_imask(sba, ioc, ioc_num); 1322 1323 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1324 1325 #ifdef CONFIG_64BIT 1326 /* 1327 ** Setting the upper bits makes checking for bypass addresses 1328 ** a little faster later on. 1329 */ 1330 ioc->imask |= 0xFFFFFFFF00000000UL; 1331 #endif 1332 1333 /* Set I/O PDIR Page size to system page size */ 1334 switch (PAGE_SHIFT) { 1335 case 12: tcnfg = 0; break; /* 4K */ 1336 case 13: tcnfg = 1; break; /* 8K */ 1337 case 14: tcnfg = 2; break; /* 16K */ 1338 case 16: tcnfg = 3; break; /* 64K */ 1339 default: 1340 panic(__FILE__ "Unsupported system page size %d", 1341 1 << PAGE_SHIFT); 1342 break; 1343 } 1344 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1345 1346 /* 1347 ** Program the IOC's ibase and enable IOVA translation 1348 ** Bit zero == enable bit. 1349 */ 1350 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1351 1352 /* 1353 ** Clear I/O TLB of any possible entries. 1354 ** (Yes. This is a bit paranoid...but so what) 1355 */ 1356 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1357 1358 #ifdef SBA_AGP_SUPPORT 1359 1360 /* 1361 ** If an AGP device is present, only use half of the IOV space 1362 ** for PCI DMA. Unfortunately we can't know ahead of time 1363 ** whether GART support will actually be used, for now we 1364 ** can just key on any AGP device found in the system. 1365 ** We program the next pdir index after we stop w/ a key for 1366 ** the GART code to handshake on. 1367 */ 1368 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); 1369 1370 if (agp_found && sba_reserve_agpgart) { 1371 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1372 __func__, (iova_space_size/2) >> 20); 1373 ioc->pdir_size /= 2; 1374 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1375 } 1376 #endif /*SBA_AGP_SUPPORT*/ 1377 } 1378 1379 static void 1380 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1381 { 1382 u32 iova_space_size, iova_space_mask; 1383 unsigned int pdir_size, iov_order, tcnfg; 1384 1385 /* 1386 ** Determine IOVA Space size from memory size. 1387 ** 1388 ** Ideally, PCI drivers would register the maximum number 1389 ** of DMA they can have outstanding for each device they 1390 ** own. Next best thing would be to guess how much DMA 1391 ** can be outstanding based on PCI Class/sub-class. Both 1392 ** methods still require some "extra" to support PCI 1393 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1394 ** 1395 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1396 ** for DMA hints - ergo only 30 bits max. 1397 */ 1398 1399 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt); 1400 1401 /* limit IOVA space size to 1MB-1GB */ 1402 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1403 iova_space_size = 1 << (20 - PAGE_SHIFT); 1404 } 1405 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1406 iova_space_size = 1 << (30 - PAGE_SHIFT); 1407 } 1408 1409 /* 1410 ** iova space must be log2() in size. 1411 ** thus, pdir/res_map will also be log2(). 1412 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1413 */ 1414 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1415 1416 /* iova_space_size is now bytes, not pages */ 1417 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1418 1419 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1420 1421 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1422 __func__, 1423 ioc->ioc_hpa, 1424 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), 1425 iova_space_size>>20, 1426 iov_order + PAGE_SHIFT); 1427 1428 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1429 1430 DBG_INIT("%s() pdir %p size %x\n", 1431 __func__, ioc->pdir_base, pdir_size); 1432 1433 #ifdef SBA_HINT_SUPPORT 1434 /* FIXME : DMA HINTs not used */ 1435 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1436 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1437 1438 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1439 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1440 #endif 1441 1442 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1443 1444 /* build IMASK for IOC and Elroy */ 1445 iova_space_mask = 0xffffffff; 1446 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1447 1448 /* 1449 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1450 ** ibase=0, imask=0xFE000000, size=0x2000000. 1451 */ 1452 ioc->ibase = 0; 1453 ioc->imask = iova_space_mask; /* save it */ 1454 #ifdef ZX1_SUPPORT 1455 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1456 #endif 1457 1458 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1459 __func__, ioc->ibase, ioc->imask); 1460 1461 /* 1462 ** FIXME: Hint registers are programmed with default hint 1463 ** values during boot, so hints should be sane even if we 1464 ** can't reprogram them the way drivers want. 1465 */ 1466 1467 setup_ibase_imask(sba, ioc, ioc_num); 1468 1469 /* 1470 ** Program the IOC's ibase and enable IOVA translation 1471 */ 1472 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1473 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1474 1475 /* Set I/O PDIR Page size to system page size */ 1476 switch (PAGE_SHIFT) { 1477 case 12: tcnfg = 0; break; /* 4K */ 1478 case 13: tcnfg = 1; break; /* 8K */ 1479 case 14: tcnfg = 2; break; /* 16K */ 1480 case 16: tcnfg = 3; break; /* 64K */ 1481 default: 1482 panic(__FILE__ "Unsupported system page size %d", 1483 1 << PAGE_SHIFT); 1484 break; 1485 } 1486 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */ 1487 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG); 1488 1489 /* 1490 ** Clear I/O TLB of any possible entries. 1491 ** (Yes. This is a bit paranoid...but so what) 1492 */ 1493 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1494 1495 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1496 1497 DBG_INIT("%s() DONE\n", __func__); 1498 } 1499 1500 1501 1502 /************************************************************************** 1503 ** 1504 ** SBA initialization code (HW and SW) 1505 ** 1506 ** o identify SBA chip itself 1507 ** o initialize SBA chip modes (HardFail) 1508 ** o initialize SBA chip modes (HardFail) 1509 ** o FIXME: initialize DMA hints for reasonable defaults 1510 ** 1511 **************************************************************************/ 1512 1513 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1514 { 1515 return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1516 } 1517 1518 static void sba_hw_init(struct sba_device *sba_dev) 1519 { 1520 int i; 1521 int num_ioc; 1522 u64 ioc_ctl; 1523 1524 if (!is_pdc_pat()) { 1525 /* Shutdown the USB controller on Astro-based workstations. 1526 ** Once we reprogram the IOMMU, the next DMA performed by 1527 ** USB will HPMC the box. USB is only enabled if a 1528 ** keyboard is present and found. 1529 ** 1530 ** With serial console, j6k v5.0 firmware says: 1531 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1532 ** 1533 ** FIXME: Using GFX+USB console at power up but direct 1534 ** linux to serial console is still broken. 1535 ** USB could generate DMA so we must reset USB. 1536 ** The proper sequence would be: 1537 ** o block console output 1538 ** o reset USB device 1539 ** o reprogram serial port 1540 ** o unblock console output 1541 */ 1542 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1543 pdc_io_reset_devices(); 1544 } 1545 1546 } 1547 1548 1549 #if 0 1550 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1551 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1552 1553 /* 1554 ** Need to deal with DMA from LAN. 1555 ** Maybe use page zero boot device as a handle to talk 1556 ** to PDC about which device to shutdown. 1557 ** 1558 ** Netbooting, j6k v5.0 firmware says: 1559 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1560 ** ARGH! invalid class. 1561 */ 1562 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1563 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1564 pdc_io_reset(); 1565 } 1566 #endif 1567 1568 if (!IS_PLUTO(sba_dev->dev)) { 1569 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1570 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1571 __func__, sba_dev->sba_hpa, ioc_ctl); 1572 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1573 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1574 /* j6700 v1.6 firmware sets 0x294f */ 1575 /* A500 firmware sets 0x4d */ 1576 1577 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1578 1579 #ifdef DEBUG_SBA_INIT 1580 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1581 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1582 #endif 1583 } /* if !PLUTO */ 1584 1585 if (IS_ASTRO(sba_dev->dev)) { 1586 int err; 1587 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1588 num_ioc = 1; 1589 1590 sba_dev->chip_resv.name = "Astro Intr Ack"; 1591 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1592 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1593 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1594 BUG_ON(err < 0); 1595 1596 } else if (IS_PLUTO(sba_dev->dev)) { 1597 int err; 1598 1599 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1600 num_ioc = 1; 1601 1602 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1603 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1604 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1605 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1606 WARN_ON(err < 0); 1607 1608 sba_dev->iommu_resv.name = "IOVA Space"; 1609 sba_dev->iommu_resv.start = 0x40000000UL; 1610 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1611 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1612 WARN_ON(err < 0); 1613 } else { 1614 /* IKE, REO */ 1615 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1616 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1617 num_ioc = 2; 1618 1619 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1620 } 1621 /* XXX: What about Reo Grande? */ 1622 1623 sba_dev->num_ioc = num_ioc; 1624 for (i = 0; i < num_ioc; i++) { 1625 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1626 unsigned int j; 1627 1628 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1629 1630 /* 1631 * Clear ROPE(N)_CONFIG AO bit. 1632 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1633 * Overrides bit 1 in DMA Hint Sets. 1634 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1635 */ 1636 if (IS_PLUTO(sba_dev->dev)) { 1637 void __iomem *rope_cfg; 1638 unsigned long cfg_val; 1639 1640 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1641 cfg_val = READ_REG(rope_cfg); 1642 cfg_val &= ~IOC_ROPE_AO; 1643 WRITE_REG(cfg_val, rope_cfg); 1644 } 1645 1646 /* 1647 ** Make sure the box crashes on rope errors. 1648 */ 1649 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1650 } 1651 1652 /* flush out the last writes */ 1653 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1654 1655 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1656 i, 1657 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1658 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1659 ); 1660 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1661 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1662 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1663 ); 1664 1665 if (IS_PLUTO(sba_dev->dev)) { 1666 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1667 } else { 1668 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1669 } 1670 } 1671 } 1672 1673 static void 1674 sba_common_init(struct sba_device *sba_dev) 1675 { 1676 int i; 1677 1678 /* add this one to the head of the list (order doesn't matter) 1679 ** This will be useful for debugging - especially if we get coredumps 1680 */ 1681 sba_dev->next = sba_list; 1682 sba_list = sba_dev; 1683 1684 for(i=0; i< sba_dev->num_ioc; i++) { 1685 int res_size; 1686 #ifdef DEBUG_DMB_TRAP 1687 extern void iterate_pages(unsigned long , unsigned long , 1688 void (*)(pte_t * , unsigned long), 1689 unsigned long ); 1690 void set_data_memory_break(pte_t * , unsigned long); 1691 #endif 1692 /* resource map size dictated by pdir_size */ 1693 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1694 1695 /* Second part of PIRANHA BUG */ 1696 if (piranha_bad_128k) { 1697 res_size -= (128*1024)/sizeof(u64); 1698 } 1699 1700 res_size >>= 3; /* convert bit count to byte count */ 1701 DBG_INIT("%s() res_size 0x%x\n", 1702 __func__, res_size); 1703 1704 sba_dev->ioc[i].res_size = res_size; 1705 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1706 1707 #ifdef DEBUG_DMB_TRAP 1708 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1709 set_data_memory_break, 0); 1710 #endif 1711 1712 if (NULL == sba_dev->ioc[i].res_map) 1713 { 1714 panic("%s:%s() could not allocate resource map\n", 1715 __FILE__, __func__ ); 1716 } 1717 1718 memset(sba_dev->ioc[i].res_map, 0, res_size); 1719 /* next available IOVP - circular search */ 1720 sba_dev->ioc[i].res_hint = (unsigned long *) 1721 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1722 1723 #ifdef ASSERT_PDIR_SANITY 1724 /* Mark first bit busy - ie no IOVA 0 */ 1725 sba_dev->ioc[i].res_map[0] = 0x80; 1726 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1727 #endif 1728 1729 /* Third (and last) part of PIRANHA BUG */ 1730 if (piranha_bad_128k) { 1731 /* region from +1408K to +1536 is un-usable. */ 1732 1733 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1734 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1735 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1736 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1737 1738 /* mark that part of the io pdir busy */ 1739 while (p_start < p_end) 1740 *p_start++ = -1; 1741 1742 } 1743 1744 #ifdef DEBUG_DMB_TRAP 1745 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1746 set_data_memory_break, 0); 1747 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1748 set_data_memory_break, 0); 1749 #endif 1750 1751 DBG_INIT("%s() %d res_map %x %p\n", 1752 __func__, i, res_size, sba_dev->ioc[i].res_map); 1753 } 1754 1755 spin_lock_init(&sba_dev->sba_lock); 1756 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1757 1758 #ifdef DEBUG_SBA_INIT 1759 /* 1760 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1761 * (bit #61, big endian), we have to flush and sync every time 1762 * IO-PDIR is changed in Ike/Astro. 1763 */ 1764 if (ioc_needs_fdc) { 1765 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1766 } else { 1767 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1768 } 1769 #endif 1770 } 1771 1772 #ifdef CONFIG_PROC_FS 1773 static int sba_proc_info(struct seq_file *m, void *p) 1774 { 1775 struct sba_device *sba_dev = sba_list; 1776 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1777 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1778 #ifdef SBA_COLLECT_STATS 1779 unsigned long avg = 0, min, max; 1780 #endif 1781 int i; 1782 1783 seq_printf(m, "%s rev %d.%d\n", 1784 sba_dev->name, 1785 (sba_dev->hw_rev & 0x7) + 1, 1786 (sba_dev->hw_rev & 0x18) >> 3); 1787 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1788 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1789 total_pages); 1790 1791 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1792 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1793 1794 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1795 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1796 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1797 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)); 1798 1799 for (i=0; i<4; i++) 1800 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", 1801 i, 1802 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1803 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1804 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)); 1805 1806 #ifdef SBA_COLLECT_STATS 1807 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1808 total_pages - ioc->used_pages, ioc->used_pages, 1809 (int)(ioc->used_pages * 100 / total_pages)); 1810 1811 min = max = ioc->avg_search[0]; 1812 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1813 avg += ioc->avg_search[i]; 1814 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1815 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1816 } 1817 avg /= SBA_SEARCH_SAMPLE; 1818 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1819 min, avg, max); 1820 1821 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1822 ioc->msingle_calls, ioc->msingle_pages, 1823 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1824 1825 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1826 min = ioc->usingle_calls; 1827 max = ioc->usingle_pages - ioc->usg_pages; 1828 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1829 min, max, (int)((max * 1000)/min)); 1830 1831 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1832 ioc->msg_calls, ioc->msg_pages, 1833 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1834 1835 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1836 ioc->usg_calls, ioc->usg_pages, 1837 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1838 #endif 1839 1840 return 0; 1841 } 1842 1843 static int 1844 sba_proc_bitmap_info(struct seq_file *m, void *p) 1845 { 1846 struct sba_device *sba_dev = sba_list; 1847 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1848 1849 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1850 ioc->res_size, false); 1851 seq_putc(m, '\n'); 1852 1853 return 0; 1854 } 1855 #endif /* CONFIG_PROC_FS */ 1856 1857 static const struct parisc_device_id sba_tbl[] __initconst = { 1858 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1859 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1860 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1861 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1862 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1863 { 0, } 1864 }; 1865 1866 static int sba_driver_callback(struct parisc_device *); 1867 1868 static struct parisc_driver sba_driver __refdata = { 1869 .name = MODULE_NAME, 1870 .id_table = sba_tbl, 1871 .probe = sba_driver_callback, 1872 }; 1873 1874 /* 1875 ** Determine if sba should claim this chip (return 0) or not (return 1). 1876 ** If so, initialize the chip and tell other partners in crime they 1877 ** have work to do. 1878 */ 1879 static int __init sba_driver_callback(struct parisc_device *dev) 1880 { 1881 struct sba_device *sba_dev; 1882 u32 func_class; 1883 int i; 1884 char *version; 1885 void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE); 1886 #ifdef CONFIG_PROC_FS 1887 struct proc_dir_entry *root; 1888 #endif 1889 1890 sba_dump_ranges(sba_addr); 1891 1892 /* Read HW Rev First */ 1893 func_class = READ_REG(sba_addr + SBA_FCLASS); 1894 1895 if (IS_ASTRO(dev)) { 1896 unsigned long fclass; 1897 static char astro_rev[]="Astro ?.?"; 1898 1899 /* Astro is broken...Read HW Rev First */ 1900 fclass = READ_REG(sba_addr); 1901 1902 astro_rev[6] = '1' + (char) (fclass & 0x7); 1903 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1904 version = astro_rev; 1905 1906 } else if (IS_IKE(dev)) { 1907 static char ike_rev[] = "Ike rev ?"; 1908 ike_rev[8] = '0' + (char) (func_class & 0xff); 1909 version = ike_rev; 1910 } else if (IS_PLUTO(dev)) { 1911 static char pluto_rev[]="Pluto ?.?"; 1912 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1913 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1914 version = pluto_rev; 1915 } else { 1916 static char reo_rev[] = "REO rev ?"; 1917 reo_rev[8] = '0' + (char) (func_class & 0xff); 1918 version = reo_rev; 1919 } 1920 1921 if (!global_ioc_cnt) { 1922 global_ioc_cnt = count_parisc_driver(&sba_driver); 1923 1924 /* Astro and Pluto have one IOC per SBA */ 1925 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1926 global_ioc_cnt *= 2; 1927 } 1928 1929 printk(KERN_INFO "%s found %s at 0x%llx\n", 1930 MODULE_NAME, version, (unsigned long long)dev->hpa.start); 1931 1932 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1933 if (!sba_dev) { 1934 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1935 return -ENOMEM; 1936 } 1937 1938 parisc_set_drvdata(dev, sba_dev); 1939 1940 for(i=0; i<MAX_IOC; i++) 1941 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1942 1943 sba_dev->dev = dev; 1944 sba_dev->hw_rev = func_class; 1945 sba_dev->name = dev->name; 1946 sba_dev->sba_hpa = sba_addr; 1947 1948 sba_get_pat_resources(sba_dev); 1949 sba_hw_init(sba_dev); 1950 sba_common_init(sba_dev); 1951 1952 hppa_dma_ops = &sba_ops; 1953 1954 #ifdef CONFIG_PROC_FS 1955 switch (dev->id.hversion) { 1956 case PLUTO_MCKINLEY_PORT: 1957 root = proc_mckinley_root; 1958 break; 1959 case ASTRO_RUNWAY_PORT: 1960 case IKE_MERCED_PORT: 1961 default: 1962 root = proc_runway_root; 1963 break; 1964 } 1965 1966 proc_create_single("sba_iommu", 0, root, sba_proc_info); 1967 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info); 1968 #endif 1969 return 0; 1970 } 1971 1972 /* 1973 ** One time initialization to let the world know the SBA was found. 1974 ** This is the only routine which is NOT static. 1975 ** Must be called exactly once before pci_init(). 1976 */ 1977 void __init sba_init(void) 1978 { 1979 register_parisc_driver(&sba_driver); 1980 } 1981 1982 1983 /** 1984 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 1985 * @dev: The parisc device. 1986 * 1987 * Returns the appropriate IOMMU data for the given parisc PCI controller. 1988 * This is cached and used later for PCI DMA Mapping. 1989 */ 1990 void * sba_get_iommu(struct parisc_device *pci_hba) 1991 { 1992 struct parisc_device *sba_dev = parisc_parent(pci_hba); 1993 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 1994 char t = sba_dev->id.hw_type; 1995 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 1996 1997 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 1998 1999 return &(sba->ioc[iocnum]); 2000 } 2001 2002 2003 /** 2004 * sba_directed_lmmio - return first directed LMMIO range routed to rope 2005 * @pa_dev: The parisc device. 2006 * @r: resource PCI host controller wants start/end fields assigned. 2007 * 2008 * For the given parisc PCI controller, determine if any direct ranges 2009 * are routed down the corresponding rope. 2010 */ 2011 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2012 { 2013 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2014 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2015 char t = sba_dev->id.hw_type; 2016 int i; 2017 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2018 2019 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2020 2021 r->start = r->end = 0; 2022 2023 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2024 for (i=0; i<4; i++) { 2025 int base, size; 2026 void __iomem *reg = sba->sba_hpa + i*0x18; 2027 2028 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2029 if ((base & 1) == 0) 2030 continue; /* not enabled */ 2031 2032 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2033 2034 if ((size & (ROPES_PER_IOC-1)) != rope) 2035 continue; /* directed down different rope */ 2036 2037 r->start = (base & ~1UL) | PCI_F_EXTEND; 2038 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2039 r->end = r->start + size; 2040 r->flags = IORESOURCE_MEM; 2041 } 2042 } 2043 2044 2045 /** 2046 * sba_distributed_lmmio - return portion of distributed LMMIO range 2047 * @pa_dev: The parisc device. 2048 * @r: resource PCI host controller wants start/end fields assigned. 2049 * 2050 * For the given parisc PCI controller, return portion of distributed LMMIO 2051 * range. The distributed LMMIO is always present and it's just a question 2052 * of the base address and size of the range. 2053 */ 2054 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2055 { 2056 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2057 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2058 char t = sba_dev->id.hw_type; 2059 int base, size; 2060 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2061 2062 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2063 2064 r->start = r->end = 0; 2065 2066 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2067 if ((base & 1) == 0) { 2068 BUG(); /* Gah! Distr Range wasn't enabled! */ 2069 return; 2070 } 2071 2072 r->start = (base & ~1UL) | PCI_F_EXTEND; 2073 2074 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2075 r->start += rope * (size + 1); /* adjust base for this rope */ 2076 r->end = r->start + size; 2077 r->flags = IORESOURCE_MEM; 2078 } 2079