1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 ** System Bus Adapter (SBA) I/O MMU manager 4 ** 5 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 6 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 7 ** (c) Copyright 2000-2004 Hewlett-Packard Company 8 ** 9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 10 ** 11 ** 12 ** 13 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 14 ** J5000/J7000/N-class/L-class machines and their successors. 15 ** 16 ** FIXME: add DMA hint support programming in both sba and lba modules. 17 */ 18 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/spinlock.h> 22 #include <linux/slab.h> 23 #include <linux/init.h> 24 25 #include <linux/mm.h> 26 #include <linux/string.h> 27 #include <linux/pci.h> 28 #include <linux/dma-map-ops.h> 29 #include <linux/scatterlist.h> 30 #include <linux/iommu-helper.h> 31 /* 32 * The semantics of 64 register access on 32bit systems can't be guaranteed 33 * by the C standard, we hope the _lo_hi() macros defining readq and writeq 34 * here will behave as expected. 35 */ 36 #include <linux/io-64-nonatomic-lo-hi.h> 37 38 #include <asm/byteorder.h> 39 #include <asm/io.h> 40 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 41 42 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 43 44 #include <linux/proc_fs.h> 45 #include <linux/seq_file.h> 46 #include <linux/module.h> 47 48 #include <asm/ropes.h> 49 #include <asm/page.h> /* for PAGE0 */ 50 #include <asm/pdc.h> /* for PDC_MODEL_* */ 51 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 52 #include <asm/parisc-device.h> 53 54 #include "iommu.h" 55 56 #define MODULE_NAME "SBA" 57 58 /* 59 ** The number of debug flags is a clue - this code is fragile. 60 ** Don't even think about messing with it unless you have 61 ** plenty of 710's to sacrifice to the computer gods. :^) 62 */ 63 #undef DEBUG_SBA_INIT 64 #undef DEBUG_SBA_RUN 65 #undef DEBUG_SBA_RUN_SG 66 #undef DEBUG_SBA_RESOURCE 67 #undef ASSERT_PDIR_SANITY 68 #undef DEBUG_LARGE_SG_ENTRIES 69 70 #ifdef DEBUG_SBA_INIT 71 #define DBG_INIT(x...) printk(x) 72 #else 73 #define DBG_INIT(x...) 74 #endif 75 76 #ifdef DEBUG_SBA_RUN 77 #define DBG_RUN(x...) printk(x) 78 #else 79 #define DBG_RUN(x...) 80 #endif 81 82 #ifdef DEBUG_SBA_RUN_SG 83 #define DBG_RUN_SG(x...) printk(x) 84 #else 85 #define DBG_RUN_SG(x...) 86 #endif 87 88 89 #ifdef DEBUG_SBA_RESOURCE 90 #define DBG_RES(x...) printk(x) 91 #else 92 #define DBG_RES(x...) 93 #endif 94 95 #define DEFAULT_DMA_HINT_REG 0 96 97 struct sba_device *sba_list; 98 EXPORT_SYMBOL_GPL(sba_list); 99 100 static unsigned long ioc_needs_fdc = 0; 101 102 /* global count of IOMMUs in the system */ 103 static unsigned int global_ioc_cnt = 0; 104 105 /* PA8700 (Piranha 2.2) bug workaround */ 106 static unsigned long piranha_bad_128k = 0; 107 108 /* Looks nice and keeps the compiler happy */ 109 #define SBA_DEV(d) ((struct sba_device *) (d)) 110 111 #ifdef CONFIG_AGP_PARISC 112 #define SBA_AGP_SUPPORT 113 #endif /*CONFIG_AGP_PARISC*/ 114 115 #ifdef SBA_AGP_SUPPORT 116 static int sba_reserve_agpgart = 1; 117 module_param(sba_reserve_agpgart, int, 0444); 118 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 119 #endif 120 121 static struct proc_dir_entry *proc_runway_root __ro_after_init; 122 static struct proc_dir_entry *proc_mckinley_root __ro_after_init; 123 124 /************************************ 125 ** SBA register read and write support 126 ** 127 ** BE WARNED: register writes are posted. 128 ** (ie follow writes which must reach HW with a read) 129 ** 130 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 131 */ 132 #define READ_REG32(addr) readl(addr) 133 #define READ_REG64(addr) readq(addr) 134 #define WRITE_REG32(val, addr) writel((val), (addr)) 135 #define WRITE_REG64(val, addr) writeq((val), (addr)) 136 137 #ifdef CONFIG_64BIT 138 #define READ_REG(addr) READ_REG64(addr) 139 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 140 #else 141 #define READ_REG(addr) READ_REG32(addr) 142 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 143 #endif 144 145 #ifdef DEBUG_SBA_INIT 146 147 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 148 149 /** 150 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 151 * @hpa: base address of the sba 152 * 153 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 154 * IO Adapter (aka Bus Converter). 155 */ 156 static void 157 sba_dump_ranges(void __iomem *hpa) 158 { 159 DBG_INIT("SBA at 0x%p\n", hpa); 160 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 161 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 162 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 163 DBG_INIT("\n"); 164 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 165 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 166 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 167 } 168 169 /** 170 * sba_dump_tlb - debugging only - print IOMMU operating parameters 171 * @hpa: base address of the IOMMU 172 * 173 * Print the size/location of the IO MMU PDIR. 174 */ 175 static void sba_dump_tlb(void __iomem *hpa) 176 { 177 DBG_INIT("IO TLB at 0x%p\n", hpa); 178 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 179 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 180 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 181 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 182 DBG_INIT("\n"); 183 } 184 #else 185 #define sba_dump_ranges(x) 186 #define sba_dump_tlb(x) 187 #endif /* DEBUG_SBA_INIT */ 188 189 190 #ifdef ASSERT_PDIR_SANITY 191 192 /** 193 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 194 * @ioc: IO MMU structure which owns the pdir we are interested in. 195 * @msg: text to print ont the output line. 196 * @pide: pdir index. 197 * 198 * Print one entry of the IO MMU PDIR in human readable form. 199 */ 200 static void 201 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 202 { 203 /* start printing from lowest pde in rval */ 204 __le64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 205 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 206 uint rcnt; 207 208 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 209 msg, 210 rptr, pide & (BITS_PER_LONG - 1), *rptr); 211 212 rcnt = 0; 213 while (rcnt < BITS_PER_LONG) { 214 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 215 (rcnt == (pide & (BITS_PER_LONG - 1))) 216 ? " -->" : " ", 217 rcnt, ptr, *ptr ); 218 rcnt++; 219 ptr++; 220 } 221 printk(KERN_DEBUG "%s", msg); 222 } 223 224 225 /** 226 * sba_check_pdir - debugging only - consistency checker 227 * @ioc: IO MMU structure which owns the pdir we are interested in. 228 * @msg: text to print ont the output line. 229 * 230 * Verify the resource map and pdir state is consistent 231 */ 232 static int 233 sba_check_pdir(struct ioc *ioc, char *msg) 234 { 235 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 236 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 237 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 238 uint pide = 0; 239 240 while (rptr < rptr_end) { 241 u32 rval = *rptr; 242 int rcnt = 32; /* number of bits we might check */ 243 244 while (rcnt) { 245 /* Get last byte and highest bit from that */ 246 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 247 if ((rval ^ pde) & 0x80000000) 248 { 249 /* 250 ** BUMMER! -- res_map != pdir -- 251 ** Dump rval and matching pdir entries 252 */ 253 sba_dump_pdir_entry(ioc, msg, pide); 254 return(1); 255 } 256 rcnt--; 257 rval <<= 1; /* try the next bit */ 258 pptr++; 259 pide++; 260 } 261 rptr++; /* look at next word of res_map */ 262 } 263 /* It'd be nice if we always got here :^) */ 264 return 0; 265 } 266 267 268 /** 269 * sba_dump_sg - debugging only - print Scatter-Gather list 270 * @ioc: IO MMU structure which owns the pdir we are interested in. 271 * @startsg: head of the SG list 272 * @nents: number of entries in SG list 273 * 274 * print the SG list so we can verify it's correct by hand. 275 */ 276 static void 277 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 278 { 279 while (nents-- > 0) { 280 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 281 nents, 282 (unsigned long) sg_dma_address(startsg), 283 sg_dma_len(startsg), 284 sg_virt(startsg), startsg->length); 285 startsg++; 286 } 287 } 288 289 #endif /* ASSERT_PDIR_SANITY */ 290 291 292 293 294 /************************************************************** 295 * 296 * I/O Pdir Resource Management 297 * 298 * Bits set in the resource map are in use. 299 * Each bit can represent a number of pages. 300 * LSbs represent lower addresses (IOVA's). 301 * 302 ***************************************************************/ 303 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 304 305 /* Convert from IOVP to IOVA and vice versa. */ 306 307 #ifdef ZX1_SUPPORT 308 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 309 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 310 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 311 #else 312 /* only support Astro and ancestors. Saves a few cycles in key places */ 313 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 314 #define SBA_IOVP(ioc,iova) (iova) 315 #endif 316 317 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 318 319 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 320 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 321 322 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, 323 unsigned int bitshiftcnt) 324 { 325 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) 326 + bitshiftcnt; 327 } 328 329 /** 330 * sba_search_bitmap - find free space in IO PDIR resource bitmap 331 * @ioc: IO MMU structure which owns the pdir we are interested in. 332 * @dev: device to query the bitmap for 333 * @bits_wanted: number of entries we need. 334 * 335 * Find consecutive free bits in resource bitmap. 336 * Each bit represents one entry in the IO Pdir. 337 * Cool perf optimization: search for log2(size) bits at a time. 338 */ 339 static unsigned long 340 sba_search_bitmap(struct ioc *ioc, struct device *dev, 341 unsigned long bits_wanted) 342 { 343 unsigned long *res_ptr = ioc->res_hint; 344 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 345 unsigned long pide = ~0UL, tpide; 346 unsigned long boundary_size; 347 unsigned long shift; 348 int ret; 349 350 boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT); 351 352 #if defined(ZX1_SUPPORT) 353 BUG_ON(ioc->ibase & ~IOVP_MASK); 354 shift = ioc->ibase >> IOVP_SHIFT; 355 #else 356 shift = 0; 357 #endif 358 359 if (bits_wanted > (BITS_PER_LONG/2)) { 360 /* Search word at a time - no mask needed */ 361 for(; res_ptr < res_end; ++res_ptr) { 362 tpide = ptr_to_pide(ioc, res_ptr, 0); 363 ret = iommu_is_span_boundary(tpide, bits_wanted, 364 shift, 365 boundary_size); 366 if ((*res_ptr == 0) && !ret) { 367 *res_ptr = RESMAP_MASK(bits_wanted); 368 pide = tpide; 369 break; 370 } 371 } 372 /* point to the next word on next pass */ 373 res_ptr++; 374 ioc->res_bitshift = 0; 375 } else { 376 /* 377 ** Search the resource bit map on well-aligned values. 378 ** "o" is the alignment. 379 ** We need the alignment to invalidate I/O TLB using 380 ** SBA HW features in the unmap path. 381 */ 382 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 383 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 384 unsigned long mask; 385 386 if (bitshiftcnt >= BITS_PER_LONG) { 387 bitshiftcnt = 0; 388 res_ptr++; 389 } 390 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 391 392 DBG_RES("%s() o %ld %p", __func__, o, res_ptr); 393 while(res_ptr < res_end) 394 { 395 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 396 WARN_ON(mask == 0); 397 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); 398 ret = iommu_is_span_boundary(tpide, bits_wanted, 399 shift, 400 boundary_size); 401 if ((((*res_ptr) & mask) == 0) && !ret) { 402 *res_ptr |= mask; /* mark resources busy! */ 403 pide = tpide; 404 break; 405 } 406 mask >>= o; 407 bitshiftcnt += o; 408 if (mask == 0) { 409 mask = RESMAP_MASK(bits_wanted); 410 bitshiftcnt=0; 411 res_ptr++; 412 } 413 } 414 /* look in the same word on the next pass */ 415 ioc->res_bitshift = bitshiftcnt + bits_wanted; 416 } 417 418 /* wrapped ? */ 419 if (res_end <= res_ptr) { 420 ioc->res_hint = (unsigned long *) ioc->res_map; 421 ioc->res_bitshift = 0; 422 } else { 423 ioc->res_hint = res_ptr; 424 } 425 return (pide); 426 } 427 428 429 /** 430 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 431 * @ioc: IO MMU structure which owns the pdir we are interested in. 432 * @dev: device for which pages should be alloced 433 * @size: number of bytes to create a mapping for 434 * 435 * Given a size, find consecutive unmarked and then mark those bits in the 436 * resource bit map. 437 */ 438 static int 439 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 440 { 441 unsigned int pages_needed = size >> IOVP_SHIFT; 442 #ifdef SBA_COLLECT_STATS 443 unsigned long cr_start = mfctl(16); 444 #endif 445 unsigned long pide; 446 447 pide = sba_search_bitmap(ioc, dev, pages_needed); 448 if (pide >= (ioc->res_size << 3)) { 449 pide = sba_search_bitmap(ioc, dev, pages_needed); 450 if (pide >= (ioc->res_size << 3)) 451 panic("%s: I/O MMU @ %p is out of mapping resources\n", 452 __FILE__, ioc->ioc_hpa); 453 } 454 455 #ifdef ASSERT_PDIR_SANITY 456 /* verify the first enable bit is clear */ 457 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 458 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 459 } 460 #endif 461 462 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 463 __func__, size, pages_needed, pide, 464 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 465 ioc->res_bitshift ); 466 467 #ifdef SBA_COLLECT_STATS 468 { 469 unsigned long cr_end = mfctl(16); 470 unsigned long tmp = cr_end - cr_start; 471 /* check for roll over */ 472 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 473 } 474 ioc->avg_search[ioc->avg_idx++] = cr_start; 475 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 476 477 ioc->used_pages += pages_needed; 478 #endif 479 480 return (pide); 481 } 482 483 484 /** 485 * sba_free_range - unmark bits in IO PDIR resource bitmap 486 * @ioc: IO MMU structure which owns the pdir we are interested in. 487 * @iova: IO virtual address which was previously allocated. 488 * @size: number of bytes to create a mapping for 489 * 490 * clear bits in the ioc's resource map 491 */ 492 static void 493 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 494 { 495 unsigned long iovp = SBA_IOVP(ioc, iova); 496 unsigned int pide = PDIR_INDEX(iovp); 497 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 498 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 499 500 int bits_not_wanted = size >> IOVP_SHIFT; 501 502 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 503 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 504 505 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 506 __func__, (uint) iova, size, 507 bits_not_wanted, m, pide, res_ptr, *res_ptr); 508 509 #ifdef SBA_COLLECT_STATS 510 ioc->used_pages -= bits_not_wanted; 511 #endif 512 513 *res_ptr &= ~m; 514 } 515 516 517 /************************************************************** 518 * 519 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 520 * 521 ***************************************************************/ 522 523 #ifdef SBA_HINT_SUPPORT 524 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 525 #endif 526 527 typedef unsigned long space_t; 528 #define KERNEL_SPACE 0 529 530 /** 531 * sba_io_pdir_entry - fill in one IO PDIR entry 532 * @pdir_ptr: pointer to IO PDIR entry 533 * @sid: process Space ID - currently only support KERNEL_SPACE 534 * @pba: Physical address of buffer to map 535 * @hint: DMA hint set to use for this mapping 536 * 537 * SBA Mapping Routine 538 * 539 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 540 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 541 * pdir_ptr (arg0). 542 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 543 * for Astro/Ike looks like: 544 * 545 * 546 * 0 19 51 55 63 547 * +-+---------------------+----------------------------------+----+--------+ 548 * |V| U | PPN[43:12] | U | VI | 549 * +-+---------------------+----------------------------------+----+--------+ 550 * 551 * Pluto is basically identical, supports fewer physical address bits: 552 * 553 * 0 23 51 55 63 554 * +-+------------------------+-------------------------------+----+--------+ 555 * |V| U | PPN[39:12] | U | VI | 556 * +-+------------------------+-------------------------------+----+--------+ 557 * 558 * V == Valid Bit (Most Significant Bit is bit 0) 559 * U == Unused 560 * PPN == Physical Page Number 561 * VI == Virtual Index (aka Coherent Index) 562 * 563 * LPA instruction output is put into PPN field. 564 * LCI (Load Coherence Index) instruction provides the "VI" bits. 565 * 566 * We pre-swap the bytes since PCX-W is Big Endian and the 567 * IOMMU uses little endian for the pdir. 568 */ 569 570 static void 571 sba_io_pdir_entry(__le64 *pdir_ptr, space_t sid, phys_addr_t pba, 572 unsigned long hint) 573 { 574 register unsigned ci; /* coherent index */ 575 576 asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(pba))); 577 pba &= IOVP_MASK; 578 pba |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */ 579 580 /* set "valid" bit, swap and store into I/O Pdir */ 581 *pdir_ptr = cpu_to_le64((unsigned long)pba | SBA_PDIR_VALID_BIT); 582 583 /* 584 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 585 * (bit #61, big endian), we have to flush and sync every time 586 * IO-PDIR is changed in Ike/Astro. 587 */ 588 asm_io_fdc(pdir_ptr); 589 } 590 591 592 /** 593 * sba_mark_invalid - invalidate one or more IO PDIR entries 594 * @ioc: IO MMU structure which owns the pdir we are interested in. 595 * @iova: IO Virtual Address mapped earlier 596 * @byte_cnt: number of bytes this mapping covers. 597 * 598 * Marking the IO PDIR entry(ies) as Invalid and invalidate 599 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 600 * is to purge stale entries in the IO TLB when unmapping entries. 601 * 602 * The PCOM register supports purging of multiple pages, with a minium 603 * of 1 page and a maximum of 2GB. Hardware requires the address be 604 * aligned to the size of the range being purged. The size of the range 605 * must be a power of 2. The "Cool perf optimization" in the 606 * allocation routine helps keep that true. 607 */ 608 static void 609 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 610 { 611 u32 iovp = (u32) SBA_IOVP(ioc,iova); 612 __le64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 613 614 #ifdef ASSERT_PDIR_SANITY 615 /* Assert first pdir entry is set. 616 ** 617 ** Even though this is a big-endian machine, the entries 618 ** in the iopdir are little endian. That's why we look at 619 ** the byte at +7 instead of at +0. 620 */ 621 if (0x80 != (((u8 *) pdir_ptr)[7])) { 622 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 623 } 624 #endif 625 626 if (byte_cnt > IOVP_SIZE) 627 { 628 #if 0 629 unsigned long entries_per_cacheline = ioc_needs_fdc ? 630 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 631 - (unsigned long) pdir_ptr; 632 : 262144; 633 #endif 634 635 /* set "size" field for PCOM */ 636 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 637 638 do { 639 /* clear I/O Pdir entry "valid" bit first */ 640 ((u8 *) pdir_ptr)[7] = 0; 641 asm_io_fdc(pdir_ptr); 642 if (ioc_needs_fdc) { 643 #if 0 644 entries_per_cacheline = L1_CACHE_SHIFT - 3; 645 #endif 646 } 647 pdir_ptr++; 648 byte_cnt -= IOVP_SIZE; 649 } while (byte_cnt > IOVP_SIZE); 650 } else 651 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 652 653 /* 654 ** clear I/O PDIR entry "valid" bit. 655 ** We have to R/M/W the cacheline regardless how much of the 656 ** pdir entry that we clobber. 657 ** The rest of the entry would be useful for debugging if we 658 ** could dump core on HPMC. 659 */ 660 ((u8 *) pdir_ptr)[7] = 0; 661 asm_io_fdc(pdir_ptr); 662 663 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 664 } 665 666 /** 667 * sba_dma_supported - PCI driver can query DMA support 668 * @dev: instance of PCI owned by the driver that's asking 669 * @mask: number of address bits this PCI device can handle 670 * 671 * See Documentation/core-api/dma-api-howto.rst 672 */ 673 static int sba_dma_supported( struct device *dev, u64 mask) 674 { 675 struct ioc *ioc; 676 677 if (dev == NULL) { 678 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 679 BUG(); 680 return(0); 681 } 682 683 ioc = GET_IOC(dev); 684 if (!ioc) 685 return 0; 686 687 /* 688 * check if mask is >= than the current max IO Virt Address 689 * The max IO Virt address will *always* < 30 bits. 690 */ 691 return((int)(mask >= (ioc->ibase - 1 + 692 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 693 } 694 695 696 /** 697 * sba_map_single - map one buffer and return IOVA for DMA 698 * @dev: instance of PCI owned by the driver that's asking. 699 * @addr: driver buffer to map. 700 * @size: number of bytes to map in driver buffer. 701 * @direction: R/W or both. 702 * 703 * See Documentation/core-api/dma-api-howto.rst 704 */ 705 static dma_addr_t 706 sba_map_single(struct device *dev, phys_addr_t addr, size_t size, 707 enum dma_data_direction direction) 708 { 709 struct ioc *ioc; 710 unsigned long flags; 711 dma_addr_t iovp; 712 dma_addr_t offset; 713 __le64 *pdir_start; 714 int pide; 715 716 ioc = GET_IOC(dev); 717 if (!ioc) 718 return DMA_MAPPING_ERROR; 719 720 /* save offset bits */ 721 offset = offset_in_page(addr); 722 723 /* round up to nearest IOVP_SIZE */ 724 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 725 726 spin_lock_irqsave(&ioc->res_lock, flags); 727 #ifdef ASSERT_PDIR_SANITY 728 sba_check_pdir(ioc,"Check before sba_map_single()"); 729 #endif 730 731 #ifdef SBA_COLLECT_STATS 732 ioc->msingle_calls++; 733 ioc->msingle_pages += size >> IOVP_SHIFT; 734 #endif 735 pide = sba_alloc_range(ioc, dev, size); 736 iovp = (dma_addr_t) pide << IOVP_SHIFT; 737 738 DBG_RUN("%s() 0x%pa -> 0x%lx\n", 739 __func__, &addr, (long) iovp | offset); 740 741 pdir_start = &(ioc->pdir_base[pide]); 742 743 while (size > 0) { 744 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, addr, 0); 745 746 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 747 pdir_start, 748 (u8) (((u8 *) pdir_start)[7]), 749 (u8) (((u8 *) pdir_start)[6]), 750 (u8) (((u8 *) pdir_start)[5]), 751 (u8) (((u8 *) pdir_start)[4]), 752 (u8) (((u8 *) pdir_start)[3]), 753 (u8) (((u8 *) pdir_start)[2]), 754 (u8) (((u8 *) pdir_start)[1]), 755 (u8) (((u8 *) pdir_start)[0]) 756 ); 757 758 addr += IOVP_SIZE; 759 size -= IOVP_SIZE; 760 pdir_start++; 761 } 762 763 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 764 asm_io_sync(); 765 766 #ifdef ASSERT_PDIR_SANITY 767 sba_check_pdir(ioc,"Check after sba_map_single()"); 768 #endif 769 spin_unlock_irqrestore(&ioc->res_lock, flags); 770 771 /* form complete address */ 772 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 773 } 774 775 776 static dma_addr_t 777 sba_map_phys(struct device *dev, phys_addr_t phys, size_t size, 778 enum dma_data_direction direction, unsigned long attrs) 779 { 780 if (unlikely(attrs & DMA_ATTR_MMIO)) 781 return DMA_MAPPING_ERROR; 782 783 return sba_map_single(dev, phys, size, direction); 784 } 785 786 787 /** 788 * sba_unmap_phys - unmap one IOVA and free resources 789 * @dev: instance of PCI owned by the driver that's asking. 790 * @iova: IOVA of driver buffer previously mapped. 791 * @size: number of bytes mapped in driver buffer. 792 * @direction: R/W or both. 793 * @attrs: attributes 794 * 795 * See Documentation/core-api/dma-api-howto.rst 796 */ 797 static void 798 sba_unmap_phys(struct device *dev, dma_addr_t iova, size_t size, 799 enum dma_data_direction direction, unsigned long attrs) 800 { 801 struct ioc *ioc; 802 #if DELAYED_RESOURCE_CNT > 0 803 struct sba_dma_pair *d; 804 #endif 805 unsigned long flags; 806 dma_addr_t offset; 807 808 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); 809 810 ioc = GET_IOC(dev); 811 if (!ioc) { 812 WARN_ON(!ioc); 813 return; 814 } 815 offset = iova & ~IOVP_MASK; 816 iova ^= offset; /* clear offset bits */ 817 size += offset; 818 size = ALIGN(size, IOVP_SIZE); 819 820 spin_lock_irqsave(&ioc->res_lock, flags); 821 822 #ifdef SBA_COLLECT_STATS 823 ioc->usingle_calls++; 824 ioc->usingle_pages += size >> IOVP_SHIFT; 825 #endif 826 827 sba_mark_invalid(ioc, iova, size); 828 829 #if DELAYED_RESOURCE_CNT > 0 830 /* Delaying when we re-use a IO Pdir entry reduces the number 831 * of MMIO reads needed to flush writes to the PCOM register. 832 */ 833 d = &(ioc->saved[ioc->saved_cnt]); 834 d->iova = iova; 835 d->size = size; 836 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 837 int cnt = ioc->saved_cnt; 838 while (cnt--) { 839 sba_free_range(ioc, d->iova, d->size); 840 d--; 841 } 842 ioc->saved_cnt = 0; 843 844 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 845 } 846 #else /* DELAYED_RESOURCE_CNT == 0 */ 847 sba_free_range(ioc, iova, size); 848 849 /* If fdc's were issued, force fdc's to be visible now */ 850 asm_io_sync(); 851 852 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 853 #endif /* DELAYED_RESOURCE_CNT == 0 */ 854 855 spin_unlock_irqrestore(&ioc->res_lock, flags); 856 857 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 858 ** For Astro based systems this isn't a big deal WRT performance. 859 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 860 ** we don't need the syncdma. The issue here is I/O MMU cachelines 861 ** are *not* coherent in all cases. May be hwrev dependent. 862 ** Need to investigate more. 863 asm volatile("syncdma"); 864 */ 865 } 866 867 868 /** 869 * sba_alloc - allocate/map shared mem for DMA 870 * @hwdev: instance of PCI owned by the driver that's asking. 871 * @size: number of bytes mapped in driver buffer. 872 * @dma_handle: IOVA of new buffer. 873 * @gfp: allocation flags 874 * @attrs: attributes 875 * 876 * See Documentation/core-api/dma-api-howto.rst 877 */ 878 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, 879 gfp_t gfp, unsigned long attrs) 880 { 881 void *ret; 882 883 if (!hwdev) { 884 /* only support PCI */ 885 *dma_handle = 0; 886 return NULL; 887 } 888 889 ret = (void *) __get_free_pages(gfp, get_order(size)); 890 891 if (ret) { 892 memset(ret, 0, size); 893 *dma_handle = sba_map_single(hwdev, virt_to_phys(ret), size, 0); 894 } 895 896 return ret; 897 } 898 899 900 /** 901 * sba_free - free/unmap shared mem for DMA 902 * @hwdev: instance of PCI owned by the driver that's asking. 903 * @size: number of bytes mapped in driver buffer. 904 * @vaddr: virtual address IOVA of "consistent" buffer. 905 * @dma_handle: IO virtual address of "consistent" buffer. 906 * @attrs: attributes 907 * 908 * See Documentation/core-api/dma-api-howto.rst 909 */ 910 static void 911 sba_free(struct device *hwdev, size_t size, void *vaddr, 912 dma_addr_t dma_handle, unsigned long attrs) 913 { 914 sba_unmap_phys(hwdev, dma_handle, size, 0, 0); 915 free_pages((unsigned long) vaddr, get_order(size)); 916 } 917 918 919 /* 920 ** Since 0 is a valid pdir_base index value, can't use that 921 ** to determine if a value is valid or not. Use a flag to indicate 922 ** the SG list entry contains a valid pdir index. 923 */ 924 #define PIDE_FLAG 0x80000000UL 925 926 #ifdef SBA_COLLECT_STATS 927 #define IOMMU_MAP_STATS 928 #endif 929 #include "iommu-helpers.h" 930 931 #ifdef DEBUG_LARGE_SG_ENTRIES 932 int dump_run_sg = 0; 933 #endif 934 935 936 /** 937 * sba_map_sg - map Scatter/Gather list 938 * @dev: instance of PCI owned by the driver that's asking. 939 * @sglist: array of buffer/length pairs 940 * @nents: number of entries in list 941 * @direction: R/W or both. 942 * @attrs: attributes 943 * 944 * See Documentation/core-api/dma-api-howto.rst 945 */ 946 static int 947 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 948 enum dma_data_direction direction, unsigned long attrs) 949 { 950 struct ioc *ioc; 951 int filled = 0; 952 unsigned long flags; 953 954 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 955 956 ioc = GET_IOC(dev); 957 if (!ioc) 958 return -EINVAL; 959 960 /* Fast path single entry scatterlists. */ 961 if (nents == 1) { 962 sg_dma_address(sglist) = sba_map_single(dev, sg_phys(sglist), 963 sglist->length, direction); 964 sg_dma_len(sglist) = sglist->length; 965 return 1; 966 } 967 968 spin_lock_irqsave(&ioc->res_lock, flags); 969 970 #ifdef ASSERT_PDIR_SANITY 971 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 972 { 973 sba_dump_sg(ioc, sglist, nents); 974 panic("Check before sba_map_sg()"); 975 } 976 #endif 977 978 #ifdef SBA_COLLECT_STATS 979 ioc->msg_calls++; 980 #endif 981 982 /* 983 ** First coalesce the chunks and allocate I/O pdir space 984 ** 985 ** If this is one DMA stream, we can properly map using the 986 ** correct virtual address associated with each DMA page. 987 ** w/o this association, we wouldn't have coherent DMA! 988 ** Access to the virtual address is what forces a two pass algorithm. 989 */ 990 iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); 991 992 /* 993 ** Program the I/O Pdir 994 ** 995 ** map the virtual addresses to the I/O Pdir 996 ** o dma_address will contain the pdir index 997 ** o dma_len will contain the number of bytes to map 998 ** o address contains the virtual address. 999 */ 1000 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 1001 1002 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 1003 asm_io_sync(); 1004 1005 #ifdef ASSERT_PDIR_SANITY 1006 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 1007 { 1008 sba_dump_sg(ioc, sglist, nents); 1009 panic("Check after sba_map_sg()\n"); 1010 } 1011 #endif 1012 1013 spin_unlock_irqrestore(&ioc->res_lock, flags); 1014 1015 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 1016 1017 return filled; 1018 } 1019 1020 1021 /** 1022 * sba_unmap_sg - unmap Scatter/Gather list 1023 * @dev: instance of PCI owned by the driver that's asking. 1024 * @sglist: array of buffer/length pairs 1025 * @nents: number of entries in list 1026 * @direction: R/W or both. 1027 * @attrs: attributes 1028 * 1029 * See Documentation/core-api/dma-api-howto.rst 1030 */ 1031 static void 1032 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1033 enum dma_data_direction direction, unsigned long attrs) 1034 { 1035 struct ioc *ioc; 1036 #ifdef ASSERT_PDIR_SANITY 1037 unsigned long flags; 1038 #endif 1039 1040 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1041 __func__, nents, sg_virt(sglist), sglist->length); 1042 1043 ioc = GET_IOC(dev); 1044 if (!ioc) { 1045 WARN_ON(!ioc); 1046 return; 1047 } 1048 1049 #ifdef SBA_COLLECT_STATS 1050 ioc->usg_calls++; 1051 #endif 1052 1053 #ifdef ASSERT_PDIR_SANITY 1054 spin_lock_irqsave(&ioc->res_lock, flags); 1055 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1056 spin_unlock_irqrestore(&ioc->res_lock, flags); 1057 #endif 1058 1059 while (nents && sg_dma_len(sglist)) { 1060 1061 sba_unmap_phys(dev, sg_dma_address(sglist), sg_dma_len(sglist), 1062 direction, 0); 1063 #ifdef SBA_COLLECT_STATS 1064 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1065 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1066 #endif 1067 ++sglist; 1068 nents--; 1069 } 1070 1071 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1072 1073 #ifdef ASSERT_PDIR_SANITY 1074 spin_lock_irqsave(&ioc->res_lock, flags); 1075 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1076 spin_unlock_irqrestore(&ioc->res_lock, flags); 1077 #endif 1078 1079 } 1080 1081 static const struct dma_map_ops sba_ops = { 1082 .dma_supported = sba_dma_supported, 1083 .alloc = sba_alloc, 1084 .free = sba_free, 1085 .map_phys = sba_map_phys, 1086 .unmap_phys = sba_unmap_phys, 1087 .map_sg = sba_map_sg, 1088 .unmap_sg = sba_unmap_sg, 1089 .get_sgtable = dma_common_get_sgtable, 1090 .alloc_pages_op = dma_common_alloc_pages, 1091 .free_pages = dma_common_free_pages, 1092 }; 1093 1094 1095 /************************************************************************** 1096 ** 1097 ** SBA PAT PDC support 1098 ** 1099 ** o call pdc_pat_cell_module() 1100 ** o store ranges in PCI "resource" structures 1101 ** 1102 **************************************************************************/ 1103 1104 static void 1105 sba_get_pat_resources(struct sba_device *sba_dev) 1106 { 1107 #if 0 1108 /* 1109 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1110 ** PAT PDC to program the SBA/LBA directed range registers...this 1111 ** burden may fall on the LBA code since it directly supports the 1112 ** PCI subsystem. It's not clear yet. - ggg 1113 */ 1114 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1115 FIXME : ??? 1116 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1117 Tells where the dvi bits are located in the address. 1118 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1119 FIXME : ??? 1120 #endif 1121 } 1122 1123 1124 /************************************************************** 1125 * 1126 * Initialization and claim 1127 * 1128 ***************************************************************/ 1129 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1130 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1131 static void * 1132 sba_alloc_pdir(unsigned int pdir_size) 1133 { 1134 unsigned long pdir_base; 1135 unsigned long pdir_order = get_order(pdir_size); 1136 1137 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1138 if (NULL == (void *) pdir_base) { 1139 panic("%s() could not allocate I/O Page Table\n", 1140 __func__); 1141 } 1142 1143 /* If this is not PA8700 (PCX-W2) 1144 ** OR newer than ver 2.2 1145 ** OR in a system that doesn't need VINDEX bits from SBA, 1146 ** 1147 ** then we aren't exposed to the HW bug. 1148 */ 1149 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1150 || (boot_cpu_data.pdc.versions > 0x202) 1151 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1152 return (void *) pdir_base; 1153 1154 /* 1155 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1156 * 1157 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1158 * Ike/Astro can cause silent data corruption. This is only 1159 * a problem if the I/O PDIR is located in memory such that 1160 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1161 * 1162 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1163 * right physical address, we can either avoid (IOPDIR <= 1MB) 1164 * or minimize (2MB IO Pdir) the problem if we restrict the 1165 * IO Pdir to a maximum size of 2MB-128K (1902K). 1166 * 1167 * Because we always allocate 2^N sized IO pdirs, either of the 1168 * "bad" regions will be the last 128K if at all. That's easy 1169 * to test for. 1170 * 1171 */ 1172 if (pdir_order <= (19-12)) { 1173 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1174 /* allocate a new one on 512k alignment */ 1175 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1176 /* release original */ 1177 free_pages(pdir_base, pdir_order); 1178 1179 pdir_base = new_pdir; 1180 1181 /* release excess */ 1182 while (pdir_order < (19-12)) { 1183 new_pdir += pdir_size; 1184 free_pages(new_pdir, pdir_order); 1185 pdir_order +=1; 1186 pdir_size <<=1; 1187 } 1188 } 1189 } else { 1190 /* 1191 ** 1MB or 2MB Pdir 1192 ** Needs to be aligned on an "odd" 1MB boundary. 1193 */ 1194 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1195 1196 /* release original */ 1197 free_pages( pdir_base, pdir_order); 1198 1199 /* release first 1MB */ 1200 free_pages(new_pdir, 20-12); 1201 1202 pdir_base = new_pdir + 1024*1024; 1203 1204 if (pdir_order > (20-12)) { 1205 /* 1206 ** 2MB Pdir. 1207 ** 1208 ** Flag tells init_bitmap() to mark bad 128k as used 1209 ** and to reduce the size by 128k. 1210 */ 1211 piranha_bad_128k = 1; 1212 1213 new_pdir += 3*1024*1024; 1214 /* release last 1MB */ 1215 free_pages(new_pdir, 20-12); 1216 1217 /* release unusable 128KB */ 1218 free_pages(new_pdir - 128*1024 , 17-12); 1219 1220 pdir_size -= 128*1024; 1221 } 1222 } 1223 1224 memset((void *) pdir_base, 0, pdir_size); 1225 return (void *) pdir_base; 1226 } 1227 1228 struct ibase_data_struct { 1229 struct ioc *ioc; 1230 int ioc_num; 1231 }; 1232 1233 static int setup_ibase_imask_callback(struct device *dev, void *data) 1234 { 1235 struct parisc_device *lba = to_parisc_device(dev); 1236 struct ibase_data_struct *ibd = data; 1237 int rope_num = (lba->hpa.start >> 13) & 0xf; 1238 if (rope_num >> 3 == ibd->ioc_num) 1239 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); 1240 return 0; 1241 } 1242 1243 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1244 static void 1245 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1246 { 1247 struct ibase_data_struct ibase_data = { 1248 .ioc = ioc, 1249 .ioc_num = ioc_num, 1250 }; 1251 1252 device_for_each_child(&sba->dev, &ibase_data, 1253 setup_ibase_imask_callback); 1254 } 1255 1256 #ifdef SBA_AGP_SUPPORT 1257 static int 1258 sba_ioc_find_quicksilver(struct device *dev, void *data) 1259 { 1260 int *agp_found = data; 1261 struct parisc_device *lba = to_parisc_device(dev); 1262 1263 if (IS_QUICKSILVER(lba)) 1264 *agp_found = 1; 1265 return 0; 1266 } 1267 #endif 1268 1269 static void 1270 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1271 { 1272 u32 iova_space_mask; 1273 u32 iova_space_size; 1274 int iov_order, tcnfg; 1275 #ifdef SBA_AGP_SUPPORT 1276 int agp_found = 0; 1277 #endif 1278 /* 1279 ** Firmware programs the base and size of a "safe IOVA space" 1280 ** (one that doesn't overlap memory or LMMIO space) in the 1281 ** IBASE and IMASK registers. 1282 */ 1283 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL; 1284 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1285 1286 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1287 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1288 iova_space_size /= 2; 1289 } 1290 1291 /* 1292 ** iov_order is always based on a 1GB IOVA space since we want to 1293 ** turn on the other half for AGP GART. 1294 */ 1295 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1296 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1297 1298 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1299 __func__, ioc->ioc_hpa, iova_space_size >> 20, 1300 iov_order + PAGE_SHIFT); 1301 1302 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1303 get_order(ioc->pdir_size)); 1304 if (!ioc->pdir_base) 1305 panic("Couldn't allocate I/O Page Table\n"); 1306 1307 memset(ioc->pdir_base, 0, ioc->pdir_size); 1308 1309 DBG_INIT("%s() pdir %p size %x\n", 1310 __func__, ioc->pdir_base, ioc->pdir_size); 1311 1312 #ifdef SBA_HINT_SUPPORT 1313 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1314 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1315 1316 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1317 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1318 #endif 1319 1320 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1321 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1322 1323 /* build IMASK for IOC and Elroy */ 1324 iova_space_mask = 0xffffffff; 1325 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1326 ioc->imask = iova_space_mask; 1327 #ifdef ZX1_SUPPORT 1328 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1329 #endif 1330 sba_dump_tlb(ioc->ioc_hpa); 1331 1332 setup_ibase_imask(sba, ioc, ioc_num); 1333 1334 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1335 1336 #ifdef CONFIG_64BIT 1337 /* 1338 ** Setting the upper bits makes checking for bypass addresses 1339 ** a little faster later on. 1340 */ 1341 ioc->imask |= 0xFFFFFFFF00000000UL; 1342 #endif 1343 1344 /* Set I/O PDIR Page size to system page size */ 1345 switch (PAGE_SHIFT) { 1346 case 12: tcnfg = 0; break; /* 4K */ 1347 case 13: tcnfg = 1; break; /* 8K */ 1348 case 14: tcnfg = 2; break; /* 16K */ 1349 case 16: tcnfg = 3; break; /* 64K */ 1350 default: 1351 panic(__FILE__ "Unsupported system page size %d", 1352 1 << PAGE_SHIFT); 1353 break; 1354 } 1355 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1356 1357 /* 1358 ** Program the IOC's ibase and enable IOVA translation 1359 ** Bit zero == enable bit. 1360 */ 1361 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1362 1363 /* 1364 ** Clear I/O TLB of any possible entries. 1365 ** (Yes. This is a bit paranoid...but so what) 1366 */ 1367 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1368 1369 #ifdef SBA_AGP_SUPPORT 1370 1371 /* 1372 ** If an AGP device is present, only use half of the IOV space 1373 ** for PCI DMA. Unfortunately we can't know ahead of time 1374 ** whether GART support will actually be used, for now we 1375 ** can just key on any AGP device found in the system. 1376 ** We program the next pdir index after we stop w/ a key for 1377 ** the GART code to handshake on. 1378 */ 1379 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); 1380 1381 if (agp_found && sba_reserve_agpgart) { 1382 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1383 __func__, (iova_space_size/2) >> 20); 1384 ioc->pdir_size /= 2; 1385 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1386 } 1387 #endif /*SBA_AGP_SUPPORT*/ 1388 } 1389 1390 static void 1391 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1392 { 1393 u32 iova_space_size, iova_space_mask; 1394 unsigned int pdir_size, iov_order, tcnfg; 1395 1396 /* 1397 ** Determine IOVA Space size from memory size. 1398 ** 1399 ** Ideally, PCI drivers would register the maximum number 1400 ** of DMA they can have outstanding for each device they 1401 ** own. Next best thing would be to guess how much DMA 1402 ** can be outstanding based on PCI Class/sub-class. Both 1403 ** methods still require some "extra" to support PCI 1404 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1405 ** 1406 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1407 ** for DMA hints - ergo only 30 bits max. 1408 */ 1409 1410 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt); 1411 1412 /* limit IOVA space size to 1MB-1GB */ 1413 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1414 iova_space_size = 1 << (20 - PAGE_SHIFT); 1415 } 1416 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1417 iova_space_size = 1 << (30 - PAGE_SHIFT); 1418 } 1419 1420 /* 1421 ** iova space must be log2() in size. 1422 ** thus, pdir/res_map will also be log2(). 1423 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1424 */ 1425 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1426 1427 /* iova_space_size is now bytes, not pages */ 1428 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1429 1430 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1431 1432 DBG_INIT("%s() hpa %px mem %ldMB IOV %dMB (%d bits)\n", 1433 __func__, 1434 ioc->ioc_hpa, 1435 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), 1436 iova_space_size>>20, 1437 iov_order + PAGE_SHIFT); 1438 1439 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1440 1441 DBG_INIT("%s() pdir %p size %x\n", 1442 __func__, ioc->pdir_base, pdir_size); 1443 1444 #ifdef SBA_HINT_SUPPORT 1445 /* FIXME : DMA HINTs not used */ 1446 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1447 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1448 1449 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1450 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1451 #endif 1452 1453 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1454 1455 /* build IMASK for IOC and Elroy */ 1456 iova_space_mask = 0xffffffff; 1457 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1458 1459 /* 1460 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1461 ** ibase=0, imask=0xFE000000, size=0x2000000. 1462 */ 1463 ioc->ibase = 0; 1464 ioc->imask = iova_space_mask; /* save it */ 1465 #ifdef ZX1_SUPPORT 1466 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1467 #endif 1468 1469 DBG_INIT("%s() IOV base %#lx mask %#0lx\n", 1470 __func__, ioc->ibase, ioc->imask); 1471 1472 /* 1473 ** FIXME: Hint registers are programmed with default hint 1474 ** values during boot, so hints should be sane even if we 1475 ** can't reprogram them the way drivers want. 1476 */ 1477 1478 setup_ibase_imask(sba, ioc, ioc_num); 1479 1480 /* 1481 ** Program the IOC's ibase and enable IOVA translation 1482 */ 1483 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1484 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1485 1486 /* Set I/O PDIR Page size to system page size */ 1487 switch (PAGE_SHIFT) { 1488 case 12: tcnfg = 0; break; /* 4K */ 1489 case 13: tcnfg = 1; break; /* 8K */ 1490 case 14: tcnfg = 2; break; /* 16K */ 1491 case 16: tcnfg = 3; break; /* 64K */ 1492 default: 1493 panic(__FILE__ "Unsupported system page size %d", 1494 1 << PAGE_SHIFT); 1495 break; 1496 } 1497 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */ 1498 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG); 1499 1500 /* 1501 ** Clear I/O TLB of any possible entries. 1502 ** (Yes. This is a bit paranoid...but so what) 1503 */ 1504 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1505 1506 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1507 1508 DBG_INIT("%s() DONE\n", __func__); 1509 } 1510 1511 1512 1513 /************************************************************************** 1514 ** 1515 ** SBA initialization code (HW and SW) 1516 ** 1517 ** o identify SBA chip itself 1518 ** o initialize SBA chip modes (HardFail) 1519 ** o initialize SBA chip modes (HardFail) 1520 ** o FIXME: initialize DMA hints for reasonable defaults 1521 ** 1522 **************************************************************************/ 1523 1524 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1525 { 1526 return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1527 } 1528 1529 static void sba_hw_init(struct sba_device *sba_dev) 1530 { 1531 int i; 1532 int num_ioc; 1533 u64 ioc_ctl; 1534 1535 if (!is_pdc_pat()) { 1536 /* Shutdown the USB controller on Astro-based workstations. 1537 ** Once we reprogram the IOMMU, the next DMA performed by 1538 ** USB will HPMC the box. USB is only enabled if a 1539 ** keyboard is present and found. 1540 ** 1541 ** With serial console, j6k v5.0 firmware says: 1542 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1543 ** 1544 ** FIXME: Using GFX+USB console at power up but direct 1545 ** linux to serial console is still broken. 1546 ** USB could generate DMA so we must reset USB. 1547 ** The proper sequence would be: 1548 ** o block console output 1549 ** o reset USB device 1550 ** o reprogram serial port 1551 ** o unblock console output 1552 */ 1553 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1554 pdc_io_reset_devices(); 1555 } 1556 1557 } 1558 1559 1560 #if 0 1561 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1562 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1563 1564 /* 1565 ** Need to deal with DMA from LAN. 1566 ** Maybe use page zero boot device as a handle to talk 1567 ** to PDC about which device to shutdown. 1568 ** 1569 ** Netbooting, j6k v5.0 firmware says: 1570 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1571 ** ARGH! invalid class. 1572 */ 1573 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1574 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1575 pdc_io_reset(); 1576 } 1577 #endif 1578 1579 if (!IS_PLUTO(sba_dev->dev)) { 1580 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1581 DBG_INIT("%s() hpa %px ioc_ctl 0x%Lx ->", 1582 __func__, sba_dev->sba_hpa, ioc_ctl); 1583 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1584 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1585 /* j6700 v1.6 firmware sets 0x294f */ 1586 /* A500 firmware sets 0x4d */ 1587 1588 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1589 1590 #ifdef DEBUG_SBA_INIT 1591 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1592 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1593 #endif 1594 } /* if !PLUTO */ 1595 1596 if (IS_ASTRO(sba_dev->dev)) { 1597 int err; 1598 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1599 num_ioc = 1; 1600 1601 sba_dev->chip_resv.name = "Astro Intr Ack"; 1602 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1603 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1604 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1605 BUG_ON(err < 0); 1606 1607 } else if (IS_PLUTO(sba_dev->dev)) { 1608 int err; 1609 1610 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1611 num_ioc = 1; 1612 1613 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1614 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1615 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1616 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1617 WARN_ON(err < 0); 1618 1619 sba_dev->iommu_resv.name = "IOVA Space"; 1620 sba_dev->iommu_resv.start = 0x40000000UL; 1621 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1622 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1623 WARN_ON(err < 0); 1624 } else { 1625 /* IKE, REO */ 1626 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1627 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1628 num_ioc = 2; 1629 1630 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1631 } 1632 /* XXX: What about Reo Grande? */ 1633 1634 sba_dev->num_ioc = num_ioc; 1635 for (i = 0; i < num_ioc; i++) { 1636 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1637 unsigned int j; 1638 1639 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1640 1641 /* 1642 * Clear ROPE(N)_CONFIG AO bit. 1643 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1644 * Overrides bit 1 in DMA Hint Sets. 1645 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1646 */ 1647 if (IS_PLUTO(sba_dev->dev)) { 1648 void __iomem *rope_cfg; 1649 unsigned long cfg_val; 1650 1651 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1652 cfg_val = READ_REG(rope_cfg); 1653 cfg_val &= ~IOC_ROPE_AO; 1654 WRITE_REG(cfg_val, rope_cfg); 1655 } 1656 1657 /* 1658 ** Make sure the box crashes on rope errors. 1659 */ 1660 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1661 } 1662 1663 /* flush out the last writes */ 1664 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1665 1666 DBG_INIT(" ioc[%d] ROPE_CFG %#lx ROPE_DBG %lx\n", 1667 i, 1668 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1669 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1670 ); 1671 DBG_INIT(" STATUS_CONTROL %#lx FLUSH_CTRL %#lx\n", 1672 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1673 (unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1674 ); 1675 1676 if (IS_PLUTO(sba_dev->dev)) { 1677 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1678 } else { 1679 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1680 } 1681 } 1682 } 1683 1684 static void 1685 sba_common_init(struct sba_device *sba_dev) 1686 { 1687 int i; 1688 1689 /* add this one to the head of the list (order doesn't matter) 1690 ** This will be useful for debugging - especially if we get coredumps 1691 */ 1692 sba_dev->next = sba_list; 1693 sba_list = sba_dev; 1694 1695 for(i=0; i< sba_dev->num_ioc; i++) { 1696 int res_size; 1697 /* resource map size dictated by pdir_size */ 1698 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1699 1700 /* Second part of PIRANHA BUG */ 1701 if (piranha_bad_128k) { 1702 res_size -= (128*1024)/sizeof(u64); 1703 } 1704 1705 res_size >>= 3; /* convert bit count to byte count */ 1706 DBG_INIT("%s() res_size 0x%x\n", 1707 __func__, res_size); 1708 1709 sba_dev->ioc[i].res_size = res_size; 1710 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1711 if (NULL == sba_dev->ioc[i].res_map) 1712 { 1713 panic("%s:%s() could not allocate resource map\n", 1714 __FILE__, __func__ ); 1715 } 1716 1717 memset(sba_dev->ioc[i].res_map, 0, res_size); 1718 /* next available IOVP - circular search */ 1719 sba_dev->ioc[i].res_hint = (unsigned long *) 1720 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1721 1722 #ifdef ASSERT_PDIR_SANITY 1723 /* Mark first bit busy - ie no IOVA 0 */ 1724 sba_dev->ioc[i].res_map[0] = 0x80; 1725 sba_dev->ioc[i].pdir_base[0] = (__force __le64) 0xeeffc0addbba0080ULL; 1726 #endif 1727 1728 /* Third (and last) part of PIRANHA BUG */ 1729 if (piranha_bad_128k) { 1730 /* region from +1408K to +1536 is un-usable. */ 1731 1732 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1733 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1734 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1735 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1736 1737 /* mark that part of the io pdir busy */ 1738 while (p_start < p_end) 1739 *p_start++ = -1; 1740 1741 } 1742 DBG_INIT("%s() %d res_map %x %p\n", 1743 __func__, i, res_size, sba_dev->ioc[i].res_map); 1744 } 1745 1746 spin_lock_init(&sba_dev->sba_lock); 1747 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1748 1749 #ifdef DEBUG_SBA_INIT 1750 /* 1751 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1752 * (bit #61, big endian), we have to flush and sync every time 1753 * IO-PDIR is changed in Ike/Astro. 1754 */ 1755 if (ioc_needs_fdc) { 1756 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1757 } else { 1758 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1759 } 1760 #endif 1761 } 1762 1763 #ifdef CONFIG_PROC_FS 1764 static int sba_proc_info(struct seq_file *m, void *p) 1765 { 1766 struct sba_device *sba_dev = sba_list; 1767 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1768 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1769 #ifdef SBA_COLLECT_STATS 1770 unsigned long avg = 0, min, max; 1771 #endif 1772 int i; 1773 1774 seq_printf(m, "%s rev %d.%d\n", 1775 sba_dev->name, 1776 (sba_dev->hw_rev & 0x7) + 1, 1777 (sba_dev->hw_rev & 0x18) >> 3); 1778 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1779 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1780 total_pages); 1781 1782 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1783 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1784 1785 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1786 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1787 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1788 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)); 1789 1790 for (i=0; i<4; i++) 1791 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", 1792 i, 1793 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1794 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1795 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)); 1796 1797 #ifdef SBA_COLLECT_STATS 1798 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1799 total_pages - ioc->used_pages, ioc->used_pages, 1800 (int)(ioc->used_pages * 100 / total_pages)); 1801 1802 min = max = ioc->avg_search[0]; 1803 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1804 avg += ioc->avg_search[i]; 1805 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1806 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1807 } 1808 avg /= SBA_SEARCH_SAMPLE; 1809 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1810 min, avg, max); 1811 1812 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1813 ioc->msingle_calls, ioc->msingle_pages, 1814 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1815 1816 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1817 min = ioc->usingle_calls; 1818 max = ioc->usingle_pages - ioc->usg_pages; 1819 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1820 min, max, (int)((max * 1000)/min)); 1821 1822 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1823 ioc->msg_calls, ioc->msg_pages, 1824 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1825 1826 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1827 ioc->usg_calls, ioc->usg_pages, 1828 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1829 #endif 1830 1831 return 0; 1832 } 1833 1834 static int 1835 sba_proc_bitmap_info(struct seq_file *m, void *p) 1836 { 1837 struct sba_device *sba_dev = sba_list; 1838 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1839 1840 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1841 ioc->res_size, false); 1842 seq_putc(m, '\n'); 1843 1844 return 0; 1845 } 1846 #endif /* CONFIG_PROC_FS */ 1847 1848 static const struct parisc_device_id sba_tbl[] __initconst = { 1849 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1850 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1851 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1852 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1853 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1854 { 0, } 1855 }; 1856 1857 static int sba_driver_callback(struct parisc_device *); 1858 1859 static struct parisc_driver sba_driver __refdata = { 1860 .name = MODULE_NAME, 1861 .id_table = sba_tbl, 1862 .probe = sba_driver_callback, 1863 }; 1864 1865 /* 1866 ** Determine if sba should claim this chip (return 0) or not (return 1). 1867 ** If so, initialize the chip and tell other partners in crime they 1868 ** have work to do. 1869 */ 1870 static int __init sba_driver_callback(struct parisc_device *dev) 1871 { 1872 struct sba_device *sba_dev; 1873 u32 func_class; 1874 int i; 1875 char *version; 1876 void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE); 1877 struct proc_dir_entry *root __maybe_unused; 1878 1879 sba_dump_ranges(sba_addr); 1880 1881 /* Read HW Rev First */ 1882 func_class = READ_REG(sba_addr + SBA_FCLASS); 1883 1884 if (IS_ASTRO(dev)) { 1885 unsigned long fclass; 1886 static char astro_rev[]="Astro ?.?"; 1887 1888 /* Astro is broken...Read HW Rev First */ 1889 fclass = READ_REG(sba_addr); 1890 1891 astro_rev[6] = '1' + (char) (fclass & 0x7); 1892 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1893 version = astro_rev; 1894 1895 } else if (IS_IKE(dev)) { 1896 static char ike_rev[] = "Ike rev ?"; 1897 ike_rev[8] = '0' + (char) (func_class & 0xff); 1898 version = ike_rev; 1899 } else if (IS_PLUTO(dev)) { 1900 static char pluto_rev[]="Pluto ?.?"; 1901 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1902 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1903 version = pluto_rev; 1904 } else { 1905 static char reo_rev[] = "REO rev ?"; 1906 reo_rev[8] = '0' + (char) (func_class & 0xff); 1907 version = reo_rev; 1908 } 1909 1910 if (!global_ioc_cnt) { 1911 global_ioc_cnt = count_parisc_driver(&sba_driver); 1912 1913 /* Astro and Pluto have one IOC per SBA */ 1914 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1915 global_ioc_cnt *= 2; 1916 } 1917 1918 printk(KERN_INFO "%s found %s at 0x%llx\n", 1919 MODULE_NAME, version, (unsigned long long)dev->hpa.start); 1920 1921 sba_dev = kzalloc_obj(struct sba_device); 1922 if (!sba_dev) { 1923 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1924 return -ENOMEM; 1925 } 1926 1927 parisc_set_drvdata(dev, sba_dev); 1928 1929 for(i=0; i<MAX_IOC; i++) 1930 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1931 1932 sba_dev->dev = dev; 1933 sba_dev->hw_rev = func_class; 1934 sba_dev->name = dev->name; 1935 sba_dev->sba_hpa = sba_addr; 1936 1937 sba_get_pat_resources(sba_dev); 1938 sba_hw_init(sba_dev); 1939 sba_common_init(sba_dev); 1940 1941 hppa_dma_ops = &sba_ops; 1942 1943 switch (dev->id.hversion) { 1944 case PLUTO_MCKINLEY_PORT: 1945 if (!proc_mckinley_root) 1946 proc_mckinley_root = proc_mkdir("bus/mckinley", NULL); 1947 root = proc_mckinley_root; 1948 break; 1949 case ASTRO_RUNWAY_PORT: 1950 case IKE_MERCED_PORT: 1951 default: 1952 if (!proc_runway_root) 1953 proc_runway_root = proc_mkdir("bus/runway", NULL); 1954 root = proc_runway_root; 1955 break; 1956 } 1957 1958 proc_create_single("sba_iommu", 0, root, sba_proc_info); 1959 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info); 1960 return 0; 1961 } 1962 1963 /* 1964 ** One time initialization to let the world know the SBA was found. 1965 ** This is the only routine which is NOT static. 1966 ** Must be called exactly once before pci_init(). 1967 */ 1968 static int __init sba_init(void) 1969 { 1970 return register_parisc_driver(&sba_driver); 1971 } 1972 arch_initcall(sba_init); 1973 1974 1975 /** 1976 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 1977 * @pci_hba: The parisc device. 1978 * 1979 * Returns the appropriate IOMMU data for the given parisc PCI controller. 1980 * This is cached and used later for PCI DMA Mapping. 1981 */ 1982 void * sba_get_iommu(struct parisc_device *pci_hba) 1983 { 1984 struct parisc_device *sba_dev = parisc_parent(pci_hba); 1985 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 1986 char t = sba_dev->id.hw_type; 1987 int iocnum = (pci_hba->hw_path >> 3); /* IOC # */ 1988 1989 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 1990 1991 return &(sba->ioc[iocnum]); 1992 } 1993 1994 1995 /** 1996 * sba_directed_lmmio - return first directed LMMIO range routed to rope 1997 * @pci_hba: The parisc device. 1998 * @r: resource PCI host controller wants start/end fields assigned. 1999 * 2000 * For the given parisc PCI controller, determine if any direct ranges 2001 * are routed down the corresponding rope. 2002 */ 2003 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2004 { 2005 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2006 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2007 char t = sba_dev->id.hw_type; 2008 int i; 2009 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2010 2011 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2012 2013 r->start = r->end = 0; 2014 2015 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2016 for (i=0; i<4; i++) { 2017 int base, size; 2018 void __iomem *reg = sba->sba_hpa + i*0x18; 2019 2020 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2021 if ((base & 1) == 0) 2022 continue; /* not enabled */ 2023 2024 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2025 2026 if ((size & (ROPES_PER_IOC-1)) != rope) 2027 continue; /* directed down different rope */ 2028 2029 r->start = (base & ~1UL) | PCI_F_EXTEND; 2030 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2031 r->end = r->start + size; 2032 r->flags = IORESOURCE_MEM; 2033 } 2034 } 2035 2036 2037 /** 2038 * sba_distributed_lmmio - return portion of distributed LMMIO range 2039 * @pci_hba: The parisc device. 2040 * @r: resource PCI host controller wants start/end fields assigned. 2041 * 2042 * For the given parisc PCI controller, return portion of distributed LMMIO 2043 * range. The distributed LMMIO is always present and it's just a question 2044 * of the base address and size of the range. 2045 */ 2046 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2047 { 2048 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2049 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2050 char t = sba_dev->id.hw_type; 2051 int base, size; 2052 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2053 2054 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2055 2056 r->start = r->end = 0; 2057 2058 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2059 if ((base & 1) == 0) { 2060 BUG(); /* Gah! Distr Range wasn't enabled! */ 2061 return; 2062 } 2063 2064 r->start = (base & ~1UL) | PCI_F_EXTEND; 2065 2066 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2067 r->start += rope * (size + 1); /* adjust base for this rope */ 2068 r->end = r->start + size; 2069 r->flags = IORESOURCE_MEM; 2070 } 2071