1 /* 2 ** 3 ** PCI Lower Bus Adapter (LBA) manager 4 ** 5 ** (c) Copyright 1999,2000 Grant Grundler 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** 8 ** This program is free software; you can redistribute it and/or modify 9 ** it under the terms of the GNU General Public License as published by 10 ** the Free Software Foundation; either version 2 of the License, or 11 ** (at your option) any later version. 12 ** 13 ** 14 ** This module primarily provides access to PCI bus (config/IOport 15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class 16 ** with 4 digit model numbers - eg C3000 (and A400...sigh). 17 ** 18 ** LBA driver isn't as simple as the Dino driver because: 19 ** (a) this chip has substantial bug fixes between revisions 20 ** (Only one Dino bug has a software workaround :^( ) 21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD) 22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver) 23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC). 24 ** (dino only deals with "Legacy" PDC) 25 ** 26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver. 27 ** (I/O SAPIC is integratd in the LBA chip). 28 ** 29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets 30 ** FIXME: Add support for PCI card hot-plug (OLARD). 31 */ 32 33 #include <linux/delay.h> 34 #include <linux/types.h> 35 #include <linux/kernel.h> 36 #include <linux/spinlock.h> 37 #include <linux/init.h> /* for __init and __devinit */ 38 #include <linux/pci.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/smp_lock.h> 42 43 #include <asm/byteorder.h> 44 #include <asm/pdc.h> 45 #include <asm/pdcpat.h> 46 #include <asm/page.h> 47 #include <asm/system.h> 48 49 #include <asm/ropes.h> 50 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 51 #include <asm/parisc-device.h> 52 #include <asm/io.h> /* read/write stuff */ 53 54 #undef DEBUG_LBA /* general stuff */ 55 #undef DEBUG_LBA_PORT /* debug I/O Port access */ 56 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */ 57 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */ 58 59 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */ 60 61 62 #ifdef DEBUG_LBA 63 #define DBG(x...) printk(x) 64 #else 65 #define DBG(x...) 66 #endif 67 68 #ifdef DEBUG_LBA_PORT 69 #define DBG_PORT(x...) printk(x) 70 #else 71 #define DBG_PORT(x...) 72 #endif 73 74 #ifdef DEBUG_LBA_CFG 75 #define DBG_CFG(x...) printk(x) 76 #else 77 #define DBG_CFG(x...) 78 #endif 79 80 #ifdef DEBUG_LBA_PAT 81 #define DBG_PAT(x...) printk(x) 82 #else 83 #define DBG_PAT(x...) 84 #endif 85 86 87 /* 88 ** Config accessor functions only pass in the 8-bit bus number and not 89 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus 90 ** number based on what firmware wrote into the scratch register. 91 ** 92 ** The "secondary" bus number is set to this before calling 93 ** pci_register_ops(). If any PPB's are present, the scan will 94 ** discover them and update the "secondary" and "subordinate" 95 ** fields in the pci_bus structure. 96 ** 97 ** Changes in the configuration *may* result in a different 98 ** bus number for each LBA depending on what firmware does. 99 */ 100 101 #define MODULE_NAME "LBA" 102 103 /* non-postable I/O port space, densely packed */ 104 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 105 static void __iomem *astro_iop_base __read_mostly; 106 107 static u32 lba_t32; 108 109 /* lba flags */ 110 #define LBA_FLAG_SKIP_PROBE 0x10 111 112 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE) 113 114 115 /* Looks nice and keeps the compiler happy */ 116 #define LBA_DEV(d) ((struct lba_device *) (d)) 117 118 119 /* 120 ** Only allow 8 subsidiary busses per LBA 121 ** Problem is the PCI bus numbering is globally shared. 122 */ 123 #define LBA_MAX_NUM_BUSES 8 124 125 /************************************ 126 * LBA register read and write support 127 * 128 * BE WARNED: register writes are posted. 129 * (ie follow writes which must reach HW with a read) 130 */ 131 #define READ_U8(addr) __raw_readb(addr) 132 #define READ_U16(addr) __raw_readw(addr) 133 #define READ_U32(addr) __raw_readl(addr) 134 #define WRITE_U8(value, addr) __raw_writeb(value, addr) 135 #define WRITE_U16(value, addr) __raw_writew(value, addr) 136 #define WRITE_U32(value, addr) __raw_writel(value, addr) 137 138 #define READ_REG8(addr) readb(addr) 139 #define READ_REG16(addr) readw(addr) 140 #define READ_REG32(addr) readl(addr) 141 #define READ_REG64(addr) readq(addr) 142 #define WRITE_REG8(value, addr) writeb(value, addr) 143 #define WRITE_REG16(value, addr) writew(value, addr) 144 #define WRITE_REG32(value, addr) writel(value, addr) 145 146 147 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) 148 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16)) 149 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f) 150 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7) 151 152 153 /* 154 ** Extract LBA (Rope) number from HPA 155 ** REVISIT: 16 ropes for Stretch/Ike? 156 */ 157 #define ROPES_PER_IOC 8 158 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1)) 159 160 161 static void 162 lba_dump_res(struct resource *r, int d) 163 { 164 int i; 165 166 if (NULL == r) 167 return; 168 169 printk(KERN_DEBUG "(%p)", r->parent); 170 for (i = d; i ; --i) printk(" "); 171 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, 172 (long)r->start, (long)r->end, r->flags); 173 lba_dump_res(r->child, d+2); 174 lba_dump_res(r->sibling, d); 175 } 176 177 178 /* 179 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex 180 ** workaround for cfg cycles: 181 ** -- preserve LBA state 182 ** -- prevent any DMA from occurring 183 ** -- turn on smart mode 184 ** -- probe with config writes before doing config reads 185 ** -- check ERROR_STATUS 186 ** -- clear ERROR_STATUS 187 ** -- restore LBA state 188 ** 189 ** The workaround is only used for device discovery. 190 */ 191 192 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 193 { 194 u8 first_bus = d->hba.hba_bus->secondary; 195 u8 last_sub_bus = d->hba.hba_bus->subordinate; 196 197 if ((bus < first_bus) || 198 (bus > last_sub_bus) || 199 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { 200 return 0; 201 } 202 203 return 1; 204 } 205 206 207 208 #define LBA_CFG_SETUP(d, tok) { \ 209 /* Save contents of error config register. */ \ 210 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \ 211 \ 212 /* Save contents of status control register. */ \ 213 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \ 214 \ 215 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \ 216 ** arbitration for full bus walks. \ 217 */ \ 218 /* Save contents of arb mask register. */ \ 219 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \ 220 \ 221 /* \ 222 * Turn off all device arbitration bits (i.e. everything \ 223 * except arbitration enable bit). \ 224 */ \ 225 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \ 226 \ 227 /* \ 228 * Set the smart mode bit so that master aborts don't cause \ 229 * LBA to go into PCI fatal mode (required). \ 230 */ \ 231 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \ 232 } 233 234 235 #define LBA_CFG_PROBE(d, tok) { \ 236 /* \ 237 * Setup Vendor ID write and read back the address register \ 238 * to make sure that LBA is the bus master. \ 239 */ \ 240 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\ 241 /* \ 242 * Read address register to ensure that LBA is the bus master, \ 243 * which implies that DMA traffic has stopped when DMA arb is off. \ 244 */ \ 245 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 246 /* \ 247 * Generate a cfg write cycle (will have no affect on \ 248 * Vendor ID register since read-only). \ 249 */ \ 250 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \ 251 /* \ 252 * Make sure write has completed before proceeding further, \ 253 * i.e. before setting clear enable. \ 254 */ \ 255 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 256 } 257 258 259 /* 260 * HPREVISIT: 261 * -- Can't tell if config cycle got the error. 262 * 263 * OV bit is broken until rev 4.0, so can't use OV bit and 264 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle. 265 * 266 * As of rev 4.0, no longer need the error check. 267 * 268 * -- Even if we could tell, we still want to return -1 269 * for **ANY** error (not just master abort). 270 * 271 * -- Only clear non-fatal errors (we don't want to bring 272 * LBA out of pci-fatal mode). 273 * 274 * Actually, there is still a race in which 275 * we could be clearing a fatal error. We will 276 * live with this during our initial bus walk 277 * until rev 4.0 (no driver activity during 278 * initial bus walk). The initial bus walk 279 * has race conditions concerning the use of 280 * smart mode as well. 281 */ 282 283 #define LBA_MASTER_ABORT_ERROR 0xc 284 #define LBA_FATAL_ERROR 0x10 285 286 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ 287 u32 error_status = 0; \ 288 /* \ 289 * Set clear enable (CE) bit. Unset by HW when new \ 290 * errors are logged -- LBA HW ERS section 14.3.3). \ 291 */ \ 292 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ 293 error_status = READ_REG32(base + LBA_ERROR_STATUS); \ 294 if ((error_status & 0x1f) != 0) { \ 295 /* \ 296 * Fail the config read request. \ 297 */ \ 298 error = 1; \ 299 if ((error_status & LBA_FATAL_ERROR) == 0) { \ 300 /* \ 301 * Clear error status (if fatal bit not set) by setting \ 302 * clear error log bit (CL). \ 303 */ \ 304 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ 305 } \ 306 } \ 307 } 308 309 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ 310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); 311 312 #define LBA_CFG_ADDR_SETUP(d, addr) { \ 313 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 314 /* \ 315 * Read address register to ensure that LBA is the bus master, \ 316 * which implies that DMA traffic has stopped when DMA arb is off. \ 317 */ \ 318 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 319 } 320 321 322 #define LBA_CFG_RESTORE(d, base) { \ 323 /* \ 324 * Restore status control register (turn off clear enable). \ 325 */ \ 326 WRITE_REG32(status_control, base + LBA_STAT_CTL); \ 327 /* \ 328 * Restore error config register (turn off smart mode). \ 329 */ \ 330 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ 331 /* \ 332 * Restore arb mask register (reenables DMA arbitration). \ 333 */ \ 334 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ 335 } 336 337 338 339 static unsigned int 340 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) 341 { 342 u32 data = ~0U; 343 int error = 0; 344 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */ 345 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ 346 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ 347 348 LBA_CFG_SETUP(d, tok); 349 LBA_CFG_PROBE(d, tok); 350 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 351 if (!error) { 352 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 353 354 LBA_CFG_ADDR_SETUP(d, tok | reg); 355 switch (size) { 356 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; 357 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; 358 case 4: data = READ_REG32(data_reg); break; 359 } 360 } 361 LBA_CFG_RESTORE(d, d->hba.base_addr); 362 return(data); 363 } 364 365 366 static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 367 { 368 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 369 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 370 u32 tok = LBA_CFG_TOK(local_bus, devfn); 371 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 372 373 if ((pos > 255) || (devfn > 255)) 374 return -EINVAL; 375 376 /* FIXME: B2K/C3600 workaround is always use old method... */ 377 /* if (!LBA_SKIP_PROBE(d)) */ { 378 /* original - Generate config cycle on broken elroy 379 with risk we will miss PCI bus errors. */ 380 *data = lba_rd_cfg(d, tok, pos, size); 381 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data); 382 return 0; 383 } 384 385 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) { 386 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos); 387 /* either don't want to look or know device isn't present. */ 388 *data = ~0U; 389 return(0); 390 } 391 392 /* Basic Algorithm 393 ** Should only get here on fully working LBA rev. 394 ** This is how simple the code should have been. 395 */ 396 LBA_CFG_ADDR_SETUP(d, tok | pos); 397 switch(size) { 398 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; 399 case 2: *data = READ_REG16(data_reg + (pos & 2)); break; 400 case 4: *data = READ_REG32(data_reg); break; 401 } 402 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data); 403 return 0; 404 } 405 406 407 static void 408 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) 409 { 410 int error = 0; 411 u32 arb_mask = 0; 412 u32 error_config = 0; 413 u32 status_control = 0; 414 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 415 416 LBA_CFG_SETUP(d, tok); 417 LBA_CFG_ADDR_SETUP(d, tok | reg); 418 switch (size) { 419 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; 420 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; 421 case 4: WRITE_REG32(data, data_reg); break; 422 } 423 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 424 LBA_CFG_RESTORE(d, d->hba.base_addr); 425 } 426 427 428 /* 429 * LBA 4.0 config write code implements non-postable semantics 430 * by doing a read of CONFIG ADDR after the write. 431 */ 432 433 static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 434 { 435 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 436 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 437 u32 tok = LBA_CFG_TOK(local_bus,devfn); 438 439 if ((pos > 255) || (devfn > 255)) 440 return -EINVAL; 441 442 if (!LBA_SKIP_PROBE(d)) { 443 /* Original Workaround */ 444 lba_wr_cfg(d, tok, pos, (u32) data, size); 445 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data); 446 return 0; 447 } 448 449 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { 450 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data); 451 return 1; /* New Workaround */ 452 } 453 454 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data); 455 456 /* Basic Algorithm */ 457 LBA_CFG_ADDR_SETUP(d, tok | pos); 458 switch(size) { 459 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); 460 break; 461 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); 462 break; 463 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); 464 break; 465 } 466 /* flush posted write */ 467 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 468 return 0; 469 } 470 471 472 static struct pci_ops elroy_cfg_ops = { 473 .read = elroy_cfg_read, 474 .write = elroy_cfg_write, 475 }; 476 477 /* 478 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy 479 * TR4.0 as no additional bugs were found in this areea between Elroy and 480 * Mercury 481 */ 482 483 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 484 { 485 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 486 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 487 u32 tok = LBA_CFG_TOK(local_bus, devfn); 488 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 489 490 if ((pos > 255) || (devfn > 255)) 491 return -EINVAL; 492 493 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 494 switch(size) { 495 case 1: 496 *data = READ_REG8(data_reg + (pos & 3)); 497 break; 498 case 2: 499 *data = READ_REG16(data_reg + (pos & 2)); 500 break; 501 case 4: 502 *data = READ_REG32(data_reg); break; 503 break; 504 } 505 506 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); 507 return 0; 508 } 509 510 /* 511 * LBA 4.0 config write code implements non-postable semantics 512 * by doing a read of CONFIG ADDR after the write. 513 */ 514 515 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 516 { 517 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 518 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 519 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 520 u32 tok = LBA_CFG_TOK(local_bus,devfn); 521 522 if ((pos > 255) || (devfn > 255)) 523 return -EINVAL; 524 525 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data); 526 527 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 528 switch(size) { 529 case 1: 530 WRITE_REG8 (data, data_reg + (pos & 3)); 531 break; 532 case 2: 533 WRITE_REG16(data, data_reg + (pos & 2)); 534 break; 535 case 4: 536 WRITE_REG32(data, data_reg); 537 break; 538 } 539 540 /* flush posted write */ 541 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 542 return 0; 543 } 544 545 static struct pci_ops mercury_cfg_ops = { 546 .read = mercury_cfg_read, 547 .write = mercury_cfg_write, 548 }; 549 550 551 static void 552 lba_bios_init(void) 553 { 554 DBG(MODULE_NAME ": lba_bios_init\n"); 555 } 556 557 558 #ifdef CONFIG_64BIT 559 560 /* 561 ** Determine if a device is already configured. 562 ** If so, reserve it resources. 563 ** 564 ** Read PCI cfg command register and see if I/O or MMIO is enabled. 565 ** PAT has to enable the devices it's using. 566 ** 567 ** Note: resources are fixed up before we try to claim them. 568 */ 569 static void 570 lba_claim_dev_resources(struct pci_dev *dev) 571 { 572 u16 cmd; 573 int i, srch_flags; 574 575 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd); 576 577 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0; 578 if (cmd & PCI_COMMAND_MEMORY) 579 srch_flags |= IORESOURCE_MEM; 580 581 if (!srch_flags) 582 return; 583 584 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 585 if (dev->resource[i].flags & srch_flags) { 586 pci_claim_resource(dev, i); 587 DBG(" claimed %s %d [%lx,%lx]/%lx\n", 588 pci_name(dev), i, 589 dev->resource[i].start, 590 dev->resource[i].end, 591 dev->resource[i].flags 592 ); 593 } 594 } 595 } 596 597 598 /* 599 * truncate_pat_collision: Deal with overlaps or outright collisions 600 * between PAT PDC reported ranges. 601 * 602 * Broken PA8800 firmware will report lmmio range that 603 * overlaps with CPU HPA. Just truncate the lmmio range. 604 * 605 * BEWARE: conflicts with this lmmio range may be an 606 * elmmio range which is pointing down another rope. 607 * 608 * FIXME: only deals with one collision per range...theoretically we 609 * could have several. Supporting more than one collision will get messy. 610 */ 611 static unsigned long 612 truncate_pat_collision(struct resource *root, struct resource *new) 613 { 614 unsigned long start = new->start; 615 unsigned long end = new->end; 616 struct resource *tmp = root->child; 617 618 if (end <= start || start < root->start || !tmp) 619 return 0; 620 621 /* find first overlap */ 622 while (tmp && tmp->end < start) 623 tmp = tmp->sibling; 624 625 /* no entries overlap */ 626 if (!tmp) return 0; 627 628 /* found one that starts behind the new one 629 ** Don't need to do anything. 630 */ 631 if (tmp->start >= end) return 0; 632 633 if (tmp->start <= start) { 634 /* "front" of new one overlaps */ 635 new->start = tmp->end + 1; 636 637 if (tmp->end >= end) { 638 /* AACCKK! totally overlaps! drop this range. */ 639 return 1; 640 } 641 } 642 643 if (tmp->end < end ) { 644 /* "end" of new one overlaps */ 645 new->end = tmp->start - 1; 646 } 647 648 printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] " 649 "to [%lx,%lx]\n", 650 start, end, 651 (long)new->start, (long)new->end ); 652 653 return 0; /* truncation successful */ 654 } 655 656 #else 657 #define lba_claim_dev_resources(dev) do { } while (0) 658 #define truncate_pat_collision(r,n) (0) 659 #endif 660 661 /* 662 ** The algorithm is generic code. 663 ** But it needs to access local data structures to get the IRQ base. 664 ** Could make this a "pci_fixup_irq(bus, region)" but not sure 665 ** it's worth it. 666 ** 667 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked. 668 ** Resources aren't allocated until recursive buswalk below HBA is completed. 669 */ 670 static void 671 lba_fixup_bus(struct pci_bus *bus) 672 { 673 struct list_head *ln; 674 #ifdef FBB_SUPPORT 675 u16 status; 676 #endif 677 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 678 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num); 679 680 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 681 bus, bus->secondary, bus->bridge->platform_data); 682 683 /* 684 ** Properly Setup MMIO resources for this bus. 685 ** pci_alloc_primary_bus() mangles this. 686 */ 687 if (bus->self) { 688 /* PCI-PCI Bridge */ 689 pci_read_bridge_bases(bus); 690 } else { 691 /* Host-PCI Bridge */ 692 int err, i; 693 694 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 695 ldev->hba.io_space.name, 696 ldev->hba.io_space.start, ldev->hba.io_space.end, 697 ldev->hba.io_space.flags); 698 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 699 ldev->hba.lmmio_space.name, 700 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, 701 ldev->hba.lmmio_space.flags); 702 703 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); 704 if (err < 0) { 705 lba_dump_res(&ioport_resource, 2); 706 BUG(); 707 } 708 /* advertize Host bridge resources to PCI bus */ 709 bus->resource[0] = &(ldev->hba.io_space); 710 i = 1; 711 712 if (ldev->hba.elmmio_space.start) { 713 err = request_resource(&iomem_resource, 714 &(ldev->hba.elmmio_space)); 715 if (err < 0) { 716 717 printk("FAILED: lba_fixup_bus() request for " 718 "elmmio_space [%lx/%lx]\n", 719 (long)ldev->hba.elmmio_space.start, 720 (long)ldev->hba.elmmio_space.end); 721 722 /* lba_dump_res(&iomem_resource, 2); */ 723 /* BUG(); */ 724 } else 725 bus->resource[i++] = &(ldev->hba.elmmio_space); 726 } 727 728 729 /* Overlaps with elmmio can (and should) fail here. 730 * We will prune (or ignore) the distributed range. 731 * 732 * FIXME: SBA code should register all elmmio ranges first. 733 * that would take care of elmmio ranges routed 734 * to a different rope (already discovered) from 735 * getting registered *after* LBA code has already 736 * registered it's distributed lmmio range. 737 */ 738 if (truncate_pat_collision(&iomem_resource, 739 &(ldev->hba.lmmio_space))) { 740 741 printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", 742 (long)ldev->hba.lmmio_space.start, 743 (long)ldev->hba.lmmio_space.end); 744 } else { 745 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); 746 if (err < 0) { 747 printk(KERN_ERR "FAILED: lba_fixup_bus() request for " 748 "lmmio_space [%lx/%lx]\n", 749 (long)ldev->hba.lmmio_space.start, 750 (long)ldev->hba.lmmio_space.end); 751 } else 752 bus->resource[i++] = &(ldev->hba.lmmio_space); 753 } 754 755 #ifdef CONFIG_64BIT 756 /* GMMIO is distributed range. Every LBA/Rope gets part it. */ 757 if (ldev->hba.gmmio_space.flags) { 758 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); 759 if (err < 0) { 760 printk("FAILED: lba_fixup_bus() request for " 761 "gmmio_space [%lx/%lx]\n", 762 (long)ldev->hba.gmmio_space.start, 763 (long)ldev->hba.gmmio_space.end); 764 lba_dump_res(&iomem_resource, 2); 765 BUG(); 766 } 767 bus->resource[i++] = &(ldev->hba.gmmio_space); 768 } 769 #endif 770 771 } 772 773 list_for_each(ln, &bus->devices) { 774 int i; 775 struct pci_dev *dev = pci_dev_b(ln); 776 777 DBG("lba_fixup_bus() %s\n", pci_name(dev)); 778 779 /* Virtualize Device/Bridge Resources. */ 780 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 781 struct resource *res = &dev->resource[i]; 782 783 /* If resource not allocated - skip it */ 784 if (!res->start) 785 continue; 786 787 if (res->flags & IORESOURCE_IO) { 788 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ", 789 res->start, res->end); 790 res->start |= lba_portbase; 791 res->end |= lba_portbase; 792 DBG("[%lx/%lx]\n", res->start, res->end); 793 } else if (res->flags & IORESOURCE_MEM) { 794 /* 795 ** Convert PCI (IO_VIEW) addresses to 796 ** processor (PA_VIEW) addresses 797 */ 798 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ", 799 res->start, res->end); 800 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start); 801 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end); 802 DBG("[%lx/%lx]\n", res->start, res->end); 803 } else { 804 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX", 805 res->flags, res->start, res->end); 806 } 807 } 808 809 #ifdef FBB_SUPPORT 810 /* 811 ** If one device does not support FBB transfers, 812 ** No one on the bus can be allowed to use them. 813 */ 814 (void) pci_read_config_word(dev, PCI_STATUS, &status); 815 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); 816 #endif 817 818 if (is_pdc_pat()) { 819 /* Claim resources for PDC's devices */ 820 lba_claim_dev_resources(dev); 821 } 822 823 /* 824 ** P2PB's have no IRQs. ignore them. 825 */ 826 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 827 continue; 828 829 /* Adjust INTERRUPT_LINE for this dev */ 830 iosapic_fixup_irq(ldev->iosapic_obj, dev); 831 } 832 833 #ifdef FBB_SUPPORT 834 /* FIXME/REVISIT - finish figuring out to set FBB on both 835 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL. 836 ** Can't fixup here anyway....garr... 837 */ 838 if (fbb_enable) { 839 if (bus->self) { 840 u8 control; 841 /* enable on PPB */ 842 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); 843 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); 844 845 } else { 846 /* enable on LBA */ 847 } 848 fbb_enable = PCI_COMMAND_FAST_BACK; 849 } 850 851 /* Lastly enable FBB/PERR/SERR on all devices too */ 852 list_for_each(ln, &bus->devices) { 853 (void) pci_read_config_word(dev, PCI_COMMAND, &status); 854 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable; 855 (void) pci_write_config_word(dev, PCI_COMMAND, status); 856 } 857 #endif 858 } 859 860 861 struct pci_bios_ops lba_bios_ops = { 862 .init = lba_bios_init, 863 .fixup_bus = lba_fixup_bus, 864 }; 865 866 867 868 869 /******************************************************* 870 ** 871 ** LBA Sprockets "I/O Port" Space Accessor Functions 872 ** 873 ** This set of accessor functions is intended for use with 874 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes). 875 ** 876 ** Many PCI devices don't require use of I/O port space (eg Tulip, 877 ** NCR720) since they export the same registers to both MMIO and 878 ** I/O port space. In general I/O port space is slower than 879 ** MMIO since drivers are designed so PIO writes can be posted. 880 ** 881 ********************************************************/ 882 883 #define LBA_PORT_IN(size, mask) \ 884 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \ 885 { \ 886 u##size t; \ 887 t = READ_REG##size(astro_iop_base + addr); \ 888 DBG_PORT(" 0x%x\n", t); \ 889 return (t); \ 890 } 891 892 LBA_PORT_IN( 8, 3) 893 LBA_PORT_IN(16, 2) 894 LBA_PORT_IN(32, 0) 895 896 897 898 /* 899 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR 900 ** 901 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is 902 ** guarantee non-postable completion semantics - not avoid X4107. 903 ** The READ_U32 only guarantees the write data gets to elroy but 904 ** out to the PCI bus. We can't read stuff from I/O port space 905 ** since we don't know what has side-effects. Attempting to read 906 ** from configuration space would be suicidal given the number of 907 ** bugs in that elroy functionality. 908 ** 909 ** Description: 910 ** DMA read results can improperly pass PIO writes (X4107). The 911 ** result of this bug is that if a processor modifies a location in 912 ** memory after having issued PIO writes, the PIO writes are not 913 ** guaranteed to be completed before a PCI device is allowed to see 914 ** the modified data in a DMA read. 915 ** 916 ** Note that IKE bug X3719 in TR1 IKEs will result in the same 917 ** symptom. 918 ** 919 ** Workaround: 920 ** The workaround for this bug is to always follow a PIO write with 921 ** a PIO read to the same bus before starting DMA on that PCI bus. 922 ** 923 */ 924 #define LBA_PORT_OUT(size, mask) \ 925 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 926 { \ 927 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \ 928 WRITE_REG##size(val, astro_iop_base + addr); \ 929 if (LBA_DEV(d)->hw_rev < 3) \ 930 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \ 931 } 932 933 LBA_PORT_OUT( 8, 3) 934 LBA_PORT_OUT(16, 2) 935 LBA_PORT_OUT(32, 0) 936 937 938 static struct pci_port_ops lba_astro_port_ops = { 939 .inb = lba_astro_in8, 940 .inw = lba_astro_in16, 941 .inl = lba_astro_in32, 942 .outb = lba_astro_out8, 943 .outw = lba_astro_out16, 944 .outl = lba_astro_out32 945 }; 946 947 948 #ifdef CONFIG_64BIT 949 #define PIOP_TO_GMMIO(lba, addr) \ 950 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3)) 951 952 /******************************************************* 953 ** 954 ** LBA PAT "I/O Port" Space Accessor Functions 955 ** 956 ** This set of accessor functions is intended for use with 957 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes). 958 ** 959 ** This uses the PIOP space located in the first 64MB of GMMIO. 960 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way. 961 ** bits 1:0 stay the same. bits 15:2 become 25:12. 962 ** Then add the base and we can generate an I/O Port cycle. 963 ********************************************************/ 964 #undef LBA_PORT_IN 965 #define LBA_PORT_IN(size, mask) \ 966 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \ 967 { \ 968 u##size t; \ 969 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \ 970 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \ 971 DBG_PORT(" 0x%x\n", t); \ 972 return (t); \ 973 } 974 975 LBA_PORT_IN( 8, 3) 976 LBA_PORT_IN(16, 2) 977 LBA_PORT_IN(32, 0) 978 979 980 #undef LBA_PORT_OUT 981 #define LBA_PORT_OUT(size, mask) \ 982 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ 983 { \ 984 void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \ 985 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \ 986 WRITE_REG##size(val, where); \ 987 /* flush the I/O down to the elroy at least */ \ 988 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \ 989 } 990 991 LBA_PORT_OUT( 8, 3) 992 LBA_PORT_OUT(16, 2) 993 LBA_PORT_OUT(32, 0) 994 995 996 static struct pci_port_ops lba_pat_port_ops = { 997 .inb = lba_pat_in8, 998 .inw = lba_pat_in16, 999 .inl = lba_pat_in32, 1000 .outb = lba_pat_out8, 1001 .outw = lba_pat_out16, 1002 .outl = lba_pat_out32 1003 }; 1004 1005 1006 1007 /* 1008 ** make range information from PDC available to PCI subsystem. 1009 ** We make the PDC call here in order to get the PCI bus range 1010 ** numbers. The rest will get forwarded in pcibios_fixup_bus(). 1011 ** We don't have a struct pci_bus assigned to us yet. 1012 */ 1013 static void 1014 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1015 { 1016 unsigned long bytecnt; 1017 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */ 1018 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */ 1019 long io_count; 1020 long status; /* PDC return status */ 1021 long pa_count; 1022 int i; 1023 1024 /* return cell module (IO view) */ 1025 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1026 PA_VIEW, & pa_pdc_cell); 1027 pa_count = pa_pdc_cell.mod[1]; 1028 1029 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1030 IO_VIEW, &io_pdc_cell); 1031 io_count = io_pdc_cell.mod[1]; 1032 1033 /* We've already done this once for device discovery...*/ 1034 if (status != PDC_OK) { 1035 panic("pdc_pat_cell_module() call failed for LBA!\n"); 1036 } 1037 1038 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) { 1039 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n"); 1040 } 1041 1042 /* 1043 ** Inspect the resources PAT tells us about 1044 */ 1045 for (i = 0; i < pa_count; i++) { 1046 struct { 1047 unsigned long type; 1048 unsigned long start; 1049 unsigned long end; /* aka finish */ 1050 } *p, *io; 1051 struct resource *r; 1052 1053 p = (void *) &(pa_pdc_cell.mod[2+i*3]); 1054 io = (void *) &(io_pdc_cell.mod[2+i*3]); 1055 1056 /* Convert the PAT range data to PCI "struct resource" */ 1057 switch(p->type & 0xff) { 1058 case PAT_PBNUM: 1059 lba_dev->hba.bus_num.start = p->start; 1060 lba_dev->hba.bus_num.end = p->end; 1061 break; 1062 1063 case PAT_LMMIO: 1064 /* used to fix up pre-initialized MEM BARs */ 1065 if (!lba_dev->hba.lmmio_space.start) { 1066 sprintf(lba_dev->hba.lmmio_name, 1067 "PCI%02x LMMIO", 1068 (int)lba_dev->hba.bus_num.start); 1069 lba_dev->hba.lmmio_space_offset = p->start - 1070 io->start; 1071 r = &lba_dev->hba.lmmio_space; 1072 r->name = lba_dev->hba.lmmio_name; 1073 } else if (!lba_dev->hba.elmmio_space.start) { 1074 sprintf(lba_dev->hba.elmmio_name, 1075 "PCI%02x ELMMIO", 1076 (int)lba_dev->hba.bus_num.start); 1077 r = &lba_dev->hba.elmmio_space; 1078 r->name = lba_dev->hba.elmmio_name; 1079 } else { 1080 printk(KERN_WARNING MODULE_NAME 1081 " only supports 2 LMMIO resources!\n"); 1082 break; 1083 } 1084 1085 r->start = p->start; 1086 r->end = p->end; 1087 r->flags = IORESOURCE_MEM; 1088 r->parent = r->sibling = r->child = NULL; 1089 break; 1090 1091 case PAT_GMMIO: 1092 /* MMIO space > 4GB phys addr; for 64-bit BAR */ 1093 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", 1094 (int)lba_dev->hba.bus_num.start); 1095 r = &lba_dev->hba.gmmio_space; 1096 r->name = lba_dev->hba.gmmio_name; 1097 r->start = p->start; 1098 r->end = p->end; 1099 r->flags = IORESOURCE_MEM; 1100 r->parent = r->sibling = r->child = NULL; 1101 break; 1102 1103 case PAT_NPIOP: 1104 printk(KERN_WARNING MODULE_NAME 1105 " range[%d] : ignoring NPIOP (0x%lx)\n", 1106 i, p->start); 1107 break; 1108 1109 case PAT_PIOP: 1110 /* 1111 ** Postable I/O port space is per PCI host adapter. 1112 ** base of 64MB PIOP region 1113 */ 1114 lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024); 1115 1116 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1117 (int)lba_dev->hba.bus_num.start); 1118 r = &lba_dev->hba.io_space; 1119 r->name = lba_dev->hba.io_name; 1120 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); 1121 r->end = r->start + HBA_PORT_SPACE_SIZE - 1; 1122 r->flags = IORESOURCE_IO; 1123 r->parent = r->sibling = r->child = NULL; 1124 break; 1125 1126 default: 1127 printk(KERN_WARNING MODULE_NAME 1128 " range[%d] : unknown pat range type (0x%lx)\n", 1129 i, p->type & 0xff); 1130 break; 1131 } 1132 } 1133 } 1134 #else 1135 /* keep compiler from complaining about missing declarations */ 1136 #define lba_pat_port_ops lba_astro_port_ops 1137 #define lba_pat_resources(pa_dev, lba_dev) 1138 #endif /* CONFIG_64BIT */ 1139 1140 1141 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *); 1142 extern void sba_directed_lmmio(struct parisc_device *, struct resource *); 1143 1144 1145 static void 1146 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1147 { 1148 struct resource *r; 1149 int lba_num; 1150 1151 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 1152 1153 /* 1154 ** With "legacy" firmware, the lowest byte of FW_SCRATCH 1155 ** represents bus->secondary and the second byte represents 1156 ** bus->subsidiary (i.e. highest PPB programmed by firmware). 1157 ** PCI bus walk *should* end up with the same result. 1158 ** FIXME: But we don't have sanity checks in PCI or LBA. 1159 */ 1160 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); 1161 r = &(lba_dev->hba.bus_num); 1162 r->name = "LBA PCI Busses"; 1163 r->start = lba_num & 0xff; 1164 r->end = (lba_num>>8) & 0xff; 1165 1166 /* Set up local PCI Bus resources - we don't need them for 1167 ** Legacy boxes but it's nice to see in /proc/iomem. 1168 */ 1169 r = &(lba_dev->hba.lmmio_space); 1170 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", 1171 (int)lba_dev->hba.bus_num.start); 1172 r->name = lba_dev->hba.lmmio_name; 1173 1174 #if 1 1175 /* We want the CPU -> IO routing of addresses. 1176 * The SBA BASE/MASK registers control CPU -> IO routing. 1177 * Ask SBA what is routed to this rope/LBA. 1178 */ 1179 sba_distributed_lmmio(pa_dev, r); 1180 #else 1181 /* 1182 * The LBA BASE/MASK registers control IO -> System routing. 1183 * 1184 * The following code works but doesn't get us what we want. 1185 * Well, only because firmware (v5.0) on C3000 doesn't program 1186 * the LBA BASE/MASE registers to be the exact inverse of 1187 * the corresponding SBA registers. Other Astro/Pluto 1188 * based platform firmware may do it right. 1189 * 1190 * Should someone want to mess with MSI, they may need to 1191 * reprogram LBA BASE/MASK registers. Thus preserve the code 1192 * below until MSI is known to work on C3000/A500/N4000/RP3440. 1193 * 1194 * Using the code below, /proc/iomem shows: 1195 * ... 1196 * f0000000-f0ffffff : PCI00 LMMIO 1197 * f05d0000-f05d0000 : lcd_data 1198 * f05d0008-f05d0008 : lcd_cmd 1199 * f1000000-f1ffffff : PCI01 LMMIO 1200 * f4000000-f4ffffff : PCI02 LMMIO 1201 * f4000000-f4001fff : sym53c8xx 1202 * f4002000-f4003fff : sym53c8xx 1203 * f4004000-f40043ff : sym53c8xx 1204 * f4005000-f40053ff : sym53c8xx 1205 * f4007000-f4007fff : ohci_hcd 1206 * f4008000-f40083ff : tulip 1207 * f6000000-f6ffffff : PCI03 LMMIO 1208 * f8000000-fbffffff : PCI00 ELMMIO 1209 * fa100000-fa4fffff : stifb mmio 1210 * fb000000-fb1fffff : stifb fb 1211 * 1212 * But everything listed under PCI02 actually lives under PCI00. 1213 * This is clearly wrong. 1214 * 1215 * Asking SBA how things are routed tells the correct story: 1216 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000 1217 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006 1218 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004 1219 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000 1220 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000 1221 * 1222 * Which looks like this in /proc/iomem: 1223 * f4000000-f47fffff : PCI00 LMMIO 1224 * f4000000-f4001fff : sym53c8xx 1225 * ...[deteled core devices - same as above]... 1226 * f4008000-f40083ff : tulip 1227 * f4800000-f4ffffff : PCI01 LMMIO 1228 * f6000000-f67fffff : PCI02 LMMIO 1229 * f7000000-f77fffff : PCI03 LMMIO 1230 * f9000000-f9ffffff : PCI02 ELMMIO 1231 * fa000000-fbffffff : PCI03 ELMMIO 1232 * fa100000-fa4fffff : stifb mmio 1233 * fb000000-fb1fffff : stifb fb 1234 * 1235 * ie all Built-in core are under now correctly under PCI00. 1236 * The "PCI02 ELMMIO" directed range is for: 1237 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2 1238 * 1239 * All is well now. 1240 */ 1241 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); 1242 if (r->start & 1) { 1243 unsigned long rsize; 1244 1245 r->flags = IORESOURCE_MEM; 1246 /* mmio_mask also clears Enable bit */ 1247 r->start &= mmio_mask; 1248 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 1249 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); 1250 1251 /* 1252 ** Each rope only gets part of the distributed range. 1253 ** Adjust "window" for this rope. 1254 */ 1255 rsize /= ROPES_PER_IOC; 1256 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start); 1257 r->end = r->start + rsize; 1258 } else { 1259 r->end = r->start = 0; /* Not enabled. */ 1260 } 1261 #endif 1262 1263 /* 1264 ** "Directed" ranges are used when the "distributed range" isn't 1265 ** sufficient for all devices below a given LBA. Typically devices 1266 ** like graphics cards or X25 may need a directed range when the 1267 ** bus has multiple slots (ie multiple devices) or the device 1268 ** needs more than the typical 4 or 8MB a distributed range offers. 1269 ** 1270 ** The main reason for ignoring it now frigging complications. 1271 ** Directed ranges may overlap (and have precedence) over 1272 ** distributed ranges. Or a distributed range assigned to a unused 1273 ** rope may be used by a directed range on a different rope. 1274 ** Support for graphics devices may require fixing this 1275 ** since they may be assigned a directed range which overlaps 1276 ** an existing (but unused portion of) distributed range. 1277 */ 1278 r = &(lba_dev->hba.elmmio_space); 1279 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", 1280 (int)lba_dev->hba.bus_num.start); 1281 r->name = lba_dev->hba.elmmio_name; 1282 1283 #if 1 1284 /* See comment which precedes call to sba_directed_lmmio() */ 1285 sba_directed_lmmio(pa_dev, r); 1286 #else 1287 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); 1288 1289 if (r->start & 1) { 1290 unsigned long rsize; 1291 r->flags = IORESOURCE_MEM; 1292 /* mmio_mask also clears Enable bit */ 1293 r->start &= mmio_mask; 1294 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 1295 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); 1296 r->end = r->start + ~rsize; 1297 } 1298 #endif 1299 1300 r = &(lba_dev->hba.io_space); 1301 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1302 (int)lba_dev->hba.bus_num.start); 1303 r->name = lba_dev->hba.io_name; 1304 r->flags = IORESOURCE_IO; 1305 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; 1306 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); 1307 1308 /* Virtualize the I/O Port space ranges */ 1309 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); 1310 r->start |= lba_num; 1311 r->end |= lba_num; 1312 } 1313 1314 1315 /************************************************************************** 1316 ** 1317 ** LBA initialization code (HW and SW) 1318 ** 1319 ** o identify LBA chip itself 1320 ** o initialize LBA chip modes (HardFail) 1321 ** o FIXME: initialize DMA hints for reasonable defaults 1322 ** o enable configuration functions 1323 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked) 1324 ** 1325 **************************************************************************/ 1326 1327 static int __init 1328 lba_hw_init(struct lba_device *d) 1329 { 1330 u32 stat; 1331 u32 bus_reset; /* PDC_PAT_BUG */ 1332 1333 #if 0 1334 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n", 1335 d->hba.base_addr, 1336 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), 1337 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), 1338 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), 1339 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); 1340 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n", 1341 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), 1342 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), 1343 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), 1344 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); 1345 printk(KERN_DEBUG " HINT cfg 0x%Lx\n", 1346 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); 1347 printk(KERN_DEBUG " HINT reg "); 1348 { int i; 1349 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8) 1350 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); 1351 } 1352 printk("\n"); 1353 #endif /* DEBUG_LBA_PAT */ 1354 1355 #ifdef CONFIG_64BIT 1356 /* 1357 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support 1358 * Only N-Class and up can really make use of Get slot status. 1359 * maybe L-class too but I've never played with it there. 1360 */ 1361 #endif 1362 1363 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */ 1364 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; 1365 if (bus_reset) { 1366 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n"); 1367 } 1368 1369 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); 1370 if (stat & LBA_SMART_MODE) { 1371 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n"); 1372 stat &= ~LBA_SMART_MODE; 1373 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); 1374 } 1375 1376 /* Set HF mode as the default (vs. -1 mode). */ 1377 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); 1378 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 1379 1380 /* 1381 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal 1382 ** if it's not already set. If we just cleared the PCI Bus Reset 1383 ** signal, wait a bit for the PCI devices to recover and setup. 1384 */ 1385 if (bus_reset) 1386 mdelay(pci_post_reset_delay); 1387 1388 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { 1389 /* 1390 ** PDC_PAT_BUG: PDC rev 40.48 on L2000. 1391 ** B2000/C3600/J6000 also have this problem? 1392 ** 1393 ** Elroys with hot pluggable slots don't get configured 1394 ** correctly if the slot is empty. ARB_MASK is set to 0 1395 ** and we can't master transactions on the bus if it's 1396 ** not at least one. 0x3 enables elroy and first slot. 1397 */ 1398 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n"); 1399 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); 1400 } 1401 1402 /* 1403 ** FIXME: Hint registers are programmed with default hint 1404 ** values by firmware. Hints should be sane even if we 1405 ** can't reprogram them the way drivers want. 1406 */ 1407 return 0; 1408 } 1409 1410 /* 1411 * Unfortunately, when firmware numbers busses, it doesn't take into account 1412 * Cardbus bridges. So we have to renumber the busses to suit ourselves. 1413 * Elroy/Mercury don't actually know what bus number they're attached to; 1414 * we use bus 0 to indicate the directly attached bus and any other bus 1415 * number will be taken care of by the PCI-PCI bridge. 1416 */ 1417 static unsigned int lba_next_bus = 0; 1418 1419 /* 1420 * Determine if lba should claim this chip (return 0) or not (return 1). 1421 * If so, initialize the chip and tell other partners in crime they 1422 * have work to do. 1423 */ 1424 static int __init 1425 lba_driver_probe(struct parisc_device *dev) 1426 { 1427 struct lba_device *lba_dev; 1428 struct pci_bus *lba_bus; 1429 struct pci_ops *cfg_ops; 1430 u32 func_class; 1431 void *tmp_obj; 1432 char *version; 1433 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096); 1434 1435 /* Read HW Rev First */ 1436 func_class = READ_REG32(addr + LBA_FCLASS); 1437 1438 if (IS_ELROY(dev)) { 1439 func_class &= 0xf; 1440 switch (func_class) { 1441 case 0: version = "TR1.0"; break; 1442 case 1: version = "TR2.0"; break; 1443 case 2: version = "TR2.1"; break; 1444 case 3: version = "TR2.2"; break; 1445 case 4: version = "TR3.0"; break; 1446 case 5: version = "TR4.0"; break; 1447 default: version = "TR4+"; 1448 } 1449 1450 printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n", 1451 version, func_class & 0xf, (long)dev->hpa.start); 1452 1453 if (func_class < 2) { 1454 printk(KERN_WARNING "Can't support LBA older than " 1455 "TR2.1 - continuing under adversity.\n"); 1456 } 1457 1458 #if 0 1459 /* Elroy TR4.0 should work with simple algorithm. 1460 But it doesn't. Still missing something. *sigh* 1461 */ 1462 if (func_class > 4) { 1463 cfg_ops = &mercury_cfg_ops; 1464 } else 1465 #endif 1466 { 1467 cfg_ops = &elroy_cfg_ops; 1468 } 1469 1470 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) { 1471 int major, minor; 1472 1473 func_class &= 0xff; 1474 major = func_class >> 4, minor = func_class & 0xf; 1475 1476 /* We could use one printk for both Elroy and Mercury, 1477 * but for the mask for func_class. 1478 */ 1479 printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n", 1480 IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major, 1481 minor, func_class, (long)dev->hpa.start); 1482 1483 cfg_ops = &mercury_cfg_ops; 1484 } else { 1485 printk(KERN_ERR "Unknown LBA found at 0x%lx\n", 1486 (long)dev->hpa.start); 1487 return -ENODEV; 1488 } 1489 1490 /* Tell I/O SAPIC driver we have a IRQ handler/region. */ 1491 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE); 1492 1493 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't 1494 ** have an IRT entry will get NULL back from iosapic code. 1495 */ 1496 1497 lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL); 1498 if (!lba_dev) { 1499 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); 1500 return(1); 1501 } 1502 1503 1504 /* ---------- First : initialize data we already have --------- */ 1505 1506 lba_dev->hw_rev = func_class; 1507 lba_dev->hba.base_addr = addr; 1508 lba_dev->hba.dev = dev; 1509 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ 1510 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ 1511 parisc_set_drvdata(dev, lba_dev); 1512 1513 /* ------------ Second : initialize common stuff ---------- */ 1514 pci_bios = &lba_bios_ops; 1515 pcibios_register_hba(HBA_DATA(lba_dev)); 1516 spin_lock_init(&lba_dev->lba_lock); 1517 1518 if (lba_hw_init(lba_dev)) 1519 return(1); 1520 1521 /* ---------- Third : setup I/O Port and MMIO resources --------- */ 1522 1523 if (is_pdc_pat()) { 1524 /* PDC PAT firmware uses PIOP region of GMMIO space. */ 1525 pci_port = &lba_pat_port_ops; 1526 /* Go ask PDC PAT what resources this LBA has */ 1527 lba_pat_resources(dev, lba_dev); 1528 } else { 1529 if (!astro_iop_base) { 1530 /* Sprockets PDC uses NPIOP region */ 1531 astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024); 1532 pci_port = &lba_astro_port_ops; 1533 } 1534 1535 /* Poke the chip a bit for /proc output */ 1536 lba_legacy_resources(dev, lba_dev); 1537 } 1538 1539 if (lba_dev->hba.bus_num.start < lba_next_bus) 1540 lba_dev->hba.bus_num.start = lba_next_bus; 1541 1542 dev->dev.platform_data = lba_dev; 1543 lba_bus = lba_dev->hba.hba_bus = 1544 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start, 1545 cfg_ops, NULL); 1546 if (lba_bus) { 1547 lba_next_bus = lba_bus->subordinate + 1; 1548 pci_bus_add_devices(lba_bus); 1549 } 1550 1551 /* This is in lieu of calling pci_assign_unassigned_resources() */ 1552 if (is_pdc_pat()) { 1553 /* assign resources to un-initialized devices */ 1554 1555 DBG_PAT("LBA pci_bus_size_bridges()\n"); 1556 pci_bus_size_bridges(lba_bus); 1557 1558 DBG_PAT("LBA pci_bus_assign_resources()\n"); 1559 pci_bus_assign_resources(lba_bus); 1560 1561 #ifdef DEBUG_LBA_PAT 1562 DBG_PAT("\nLBA PIOP resource tree\n"); 1563 lba_dump_res(&lba_dev->hba.io_space, 2); 1564 DBG_PAT("\nLBA LMMIO resource tree\n"); 1565 lba_dump_res(&lba_dev->hba.lmmio_space, 2); 1566 #endif 1567 } 1568 pci_enable_bridges(lba_bus); 1569 1570 1571 /* 1572 ** Once PCI register ops has walked the bus, access to config 1573 ** space is restricted. Avoids master aborts on config cycles. 1574 ** Early LBA revs go fatal on *any* master abort. 1575 */ 1576 if (cfg_ops == &elroy_cfg_ops) { 1577 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 1578 } 1579 1580 /* Whew! Finally done! Tell services we got this one covered. */ 1581 return 0; 1582 } 1583 1584 static struct parisc_device_id lba_tbl[] = { 1585 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa }, 1586 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa }, 1587 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa }, 1588 { 0, } 1589 }; 1590 1591 static struct parisc_driver lba_driver = { 1592 .name = MODULE_NAME, 1593 .id_table = lba_tbl, 1594 .probe = lba_driver_probe, 1595 }; 1596 1597 /* 1598 ** One time initialization to let the world know the LBA was found. 1599 ** Must be called exactly once before pci_init(). 1600 */ 1601 void __init lba_init(void) 1602 { 1603 register_parisc_driver(&lba_driver); 1604 } 1605 1606 /* 1607 ** Initialize the IBASE/IMASK registers for LBA (Elroy). 1608 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA). 1609 ** sba_iommu is responsible for locking (none needed at init time). 1610 */ 1611 void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) 1612 { 1613 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); 1614 1615 imask <<= 2; /* adjust for hints - 2 more bits */ 1616 1617 /* Make sure we aren't trying to set bits that aren't writeable. */ 1618 WARN_ON((ibase & 0x001fffff) != 0); 1619 WARN_ON((imask & 0x001fffff) != 0); 1620 1621 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask); 1622 WRITE_REG32( imask, base_addr + LBA_IMASK); 1623 WRITE_REG32( ibase, base_addr + LBA_IBASE); 1624 iounmap(base_addr); 1625 } 1626 1627