1 /* 2 * eisa.c - provide support for EISA adapters in PA-RISC machines 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard 10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com> 11 * 12 * There are two distinct EISA adapters. Mongoose is found in machines 13 * before the 712; then the Wax ASIC is used. To complicate matters, the 14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are 15 * dealt with elsewhere; this file is concerned only with the EISA portions 16 * of Wax. 17 * 18 * 19 * HINT: 20 * ----- 21 * To allow an ISA card to work properly in the EISA slot you need to 22 * set an edge trigger level. This may be done on the palo command line 23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with 24 * n and n2 as the irq levels you want to use. 25 * 26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at 27 * irq levels 10 and 11. 28 */ 29 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/interrupt.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/spinlock.h> 37 #include <linux/eisa.h> 38 39 #include <asm/byteorder.h> 40 #include <asm/io.h> 41 #include <asm/hardware.h> 42 #include <asm/processor.h> 43 #include <asm/parisc-device.h> 44 #include <asm/delay.h> 45 #include <asm/eisa_bus.h> 46 #include <asm/eisa_eeprom.h> 47 48 #if 0 49 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg ) 50 #else 51 #define EISA_DBG(msg, arg... ) 52 #endif 53 54 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400 55 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400 56 57 static DEFINE_SPINLOCK(eisa_irq_lock); 58 59 void __iomem *eisa_eeprom_addr __read_mostly; 60 61 /* We can only have one EISA adapter in the system because neither 62 * implementation can be flexed. 63 */ 64 static struct eisa_ba { 65 struct pci_hba_data hba; 66 unsigned long eeprom_addr; 67 struct eisa_root_device root; 68 } eisa_dev; 69 70 /* Port ops */ 71 72 static inline unsigned long eisa_permute(unsigned short port) 73 { 74 if (port & 0x300) { 75 return 0xfc000000 | ((port & 0xfc00) >> 6) 76 | ((port & 0x3f8) << 9) | (port & 7); 77 } else { 78 return 0xfc000000 | port; 79 } 80 } 81 82 unsigned char eisa_in8(unsigned short port) 83 { 84 if (EISA_bus) 85 return gsc_readb(eisa_permute(port)); 86 return 0xff; 87 } 88 89 unsigned short eisa_in16(unsigned short port) 90 { 91 if (EISA_bus) 92 return le16_to_cpu(gsc_readw(eisa_permute(port))); 93 return 0xffff; 94 } 95 96 unsigned int eisa_in32(unsigned short port) 97 { 98 if (EISA_bus) 99 return le32_to_cpu(gsc_readl(eisa_permute(port))); 100 return 0xffffffff; 101 } 102 103 void eisa_out8(unsigned char data, unsigned short port) 104 { 105 if (EISA_bus) 106 gsc_writeb(data, eisa_permute(port)); 107 } 108 109 void eisa_out16(unsigned short data, unsigned short port) 110 { 111 if (EISA_bus) 112 gsc_writew(cpu_to_le16(data), eisa_permute(port)); 113 } 114 115 void eisa_out32(unsigned int data, unsigned short port) 116 { 117 if (EISA_bus) 118 gsc_writel(cpu_to_le32(data), eisa_permute(port)); 119 } 120 121 #ifndef CONFIG_PCI 122 /* We call these directly without PCI. See asm/io.h. */ 123 EXPORT_SYMBOL(eisa_in8); 124 EXPORT_SYMBOL(eisa_in16); 125 EXPORT_SYMBOL(eisa_in32); 126 EXPORT_SYMBOL(eisa_out8); 127 EXPORT_SYMBOL(eisa_out16); 128 EXPORT_SYMBOL(eisa_out32); 129 #endif 130 131 /* Interrupt handling */ 132 133 /* cached interrupt mask registers */ 134 static int master_mask; 135 static int slave_mask; 136 137 /* the trig level can be set with the 138 * eisa_irq_edge=n,n,n commandline parameter 139 * We should really read this from the EEPROM 140 * in the furure. 141 */ 142 /* irq 13,8,2,1,0 must be edge */ 143 static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */ 144 145 146 /* called by free irq */ 147 static void eisa_mask_irq(unsigned int irq) 148 { 149 unsigned long flags; 150 151 EISA_DBG("disable irq %d\n", irq); 152 /* just mask for now */ 153 spin_lock_irqsave(&eisa_irq_lock, flags); 154 if (irq & 8) { 155 slave_mask |= (1 << (irq&7)); 156 eisa_out8(slave_mask, 0xa1); 157 } else { 158 master_mask |= (1 << (irq&7)); 159 eisa_out8(master_mask, 0x21); 160 } 161 spin_unlock_irqrestore(&eisa_irq_lock, flags); 162 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 163 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 164 } 165 166 /* called by request irq */ 167 static void eisa_unmask_irq(unsigned int irq) 168 { 169 unsigned long flags; 170 EISA_DBG("enable irq %d\n", irq); 171 172 spin_lock_irqsave(&eisa_irq_lock, flags); 173 if (irq & 8) { 174 slave_mask &= ~(1 << (irq&7)); 175 eisa_out8(slave_mask, 0xa1); 176 } else { 177 master_mask &= ~(1 << (irq&7)); 178 eisa_out8(master_mask, 0x21); 179 } 180 spin_unlock_irqrestore(&eisa_irq_lock, flags); 181 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 182 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 183 } 184 185 static struct irq_chip eisa_interrupt_type = { 186 .name = "EISA", 187 .unmask = eisa_unmask_irq, 188 .mask = eisa_mask_irq, 189 .ack = no_ack_irq, 190 }; 191 192 static irqreturn_t eisa_irq(int wax_irq, void *intr_dev) 193 { 194 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */ 195 unsigned long flags; 196 197 spin_lock_irqsave(&eisa_irq_lock, flags); 198 /* read IRR command */ 199 eisa_out8(0x0a, 0x20); 200 eisa_out8(0x0a, 0xa0); 201 202 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n", 203 irq, eisa_in8(0x20), eisa_in8(0xa0)); 204 205 /* read ISR command */ 206 eisa_out8(0x0a, 0x20); 207 eisa_out8(0x0a, 0xa0); 208 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n", 209 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1)); 210 211 irq &= 0xf; 212 213 /* mask irq and write eoi */ 214 if (irq & 8) { 215 slave_mask |= (1 << (irq&7)); 216 eisa_out8(slave_mask, 0xa1); 217 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */ 218 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 219 220 } else { 221 master_mask |= (1 << (irq&7)); 222 eisa_out8(master_mask, 0x21); 223 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */ 224 } 225 spin_unlock_irqrestore(&eisa_irq_lock, flags); 226 227 generic_handle_irq(irq); 228 229 spin_lock_irqsave(&eisa_irq_lock, flags); 230 /* unmask */ 231 if (irq & 8) { 232 slave_mask &= ~(1 << (irq&7)); 233 eisa_out8(slave_mask, 0xa1); 234 } else { 235 master_mask &= ~(1 << (irq&7)); 236 eisa_out8(master_mask, 0x21); 237 } 238 spin_unlock_irqrestore(&eisa_irq_lock, flags); 239 return IRQ_HANDLED; 240 } 241 242 static irqreturn_t dummy_irq2_handler(int _, void *dev) 243 { 244 printk(KERN_ALERT "eisa: uhh, irq2?\n"); 245 return IRQ_HANDLED; 246 } 247 248 static struct irqaction irq2_action = { 249 .handler = dummy_irq2_handler, 250 .name = "cascade", 251 }; 252 253 static void init_eisa_pic(void) 254 { 255 unsigned long flags; 256 257 spin_lock_irqsave(&eisa_irq_lock, flags); 258 259 eisa_out8(0xff, 0x21); /* mask during init */ 260 eisa_out8(0xff, 0xa1); /* mask during init */ 261 262 /* master pic */ 263 eisa_out8(0x11,0x20); /* ICW1 */ 264 eisa_out8(0x00,0x21); /* ICW2 */ 265 eisa_out8(0x04,0x21); /* ICW3 */ 266 eisa_out8(0x01,0x21); /* ICW4 */ 267 eisa_out8(0x40,0x20); /* OCW2 */ 268 269 /* slave pic */ 270 eisa_out8(0x11,0xa0); /* ICW1 */ 271 eisa_out8(0x08,0xa1); /* ICW2 */ 272 eisa_out8(0x02,0xa1); /* ICW3 */ 273 eisa_out8(0x01,0xa1); /* ICW4 */ 274 eisa_out8(0x40,0xa0); /* OCW2 */ 275 276 udelay(100); 277 278 slave_mask = 0xff; 279 master_mask = 0xfb; 280 eisa_out8(slave_mask, 0xa1); /* OCW1 */ 281 eisa_out8(master_mask, 0x21); /* OCW1 */ 282 283 /* setup trig level */ 284 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level); 285 286 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */ 287 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1); 288 289 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 290 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 291 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0)); 292 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1)); 293 294 spin_unlock_irqrestore(&eisa_irq_lock, flags); 295 } 296 297 /* Device initialisation */ 298 299 #define is_mongoose(dev) (dev->id.sversion == 0x00076) 300 301 static int __init eisa_probe(struct parisc_device *dev) 302 { 303 int i, result; 304 305 char *name = is_mongoose(dev) ? "Mongoose" : "Wax"; 306 307 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n", 308 name, (unsigned long)dev->hpa.start); 309 310 eisa_dev.hba.dev = dev; 311 eisa_dev.hba.iommu = ccio_get_iommu(dev); 312 313 eisa_dev.hba.lmmio_space.name = "EISA"; 314 eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000); 315 eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff); 316 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM; 317 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space); 318 if (result < 0) { 319 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n"); 320 return result; 321 } 322 eisa_dev.hba.io_space.name = "EISA"; 323 eisa_dev.hba.io_space.start = 0; 324 eisa_dev.hba.io_space.end = 0xffff; 325 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO; 326 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space); 327 if (result < 0) { 328 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n"); 329 return result; 330 } 331 pcibios_register_hba(&eisa_dev.hba); 332 333 result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev); 334 if (result) { 335 printk(KERN_ERR "EISA: request_irq failed!\n"); 336 return result; 337 } 338 339 /* Reserve IRQ2 */ 340 setup_irq(2, &irq2_action); 341 for (i = 0; i < 16; i++) { 342 set_irq_chip_and_handler(i, &eisa_interrupt_type, 343 handle_level_irq); 344 } 345 346 EISA_bus = 1; 347 348 if (dev->num_addrs) { 349 /* newer firmware hand out the eeprom address */ 350 eisa_dev.eeprom_addr = dev->addr[0]; 351 } else { 352 /* old firmware, need to figure out the box */ 353 if (is_mongoose(dev)) { 354 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR; 355 } else { 356 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR; 357 } 358 } 359 eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH); 360 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, 361 &eisa_dev.hba.lmmio_space); 362 init_eisa_pic(); 363 364 if (result >= 0) { 365 /* FIXME : Don't enumerate the bus twice. */ 366 eisa_dev.root.dev = &dev->dev; 367 dev_set_drvdata(&dev->dev, &eisa_dev.root); 368 eisa_dev.root.bus_base_addr = 0; 369 eisa_dev.root.res = &eisa_dev.hba.io_space; 370 eisa_dev.root.slots = result; 371 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */ 372 if (eisa_root_register (&eisa_dev.root)) { 373 printk(KERN_ERR "EISA: Failed to register EISA root\n"); 374 return -1; 375 } 376 } 377 378 return 0; 379 } 380 381 static const struct parisc_device_id eisa_tbl[] = { 382 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */ 383 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */ 384 { 0, } 385 }; 386 387 MODULE_DEVICE_TABLE(parisc, eisa_tbl); 388 389 static struct parisc_driver eisa_driver = { 390 .name = "eisa_ba", 391 .id_table = eisa_tbl, 392 .probe = eisa_probe, 393 }; 394 395 void __init eisa_init(void) 396 { 397 register_parisc_driver(&eisa_driver); 398 } 399 400 401 static unsigned int eisa_irq_configured; 402 void eisa_make_irq_level(int num) 403 { 404 if (eisa_irq_configured& (1<<num)) { 405 printk(KERN_WARNING 406 "IRQ %d polarity configured twice (last to level)\n", 407 num); 408 } 409 eisa_irq_level |= (1<<num); /* set the corresponding bit */ 410 eisa_irq_configured |= (1<<num); /* set the corresponding bit */ 411 } 412 413 void eisa_make_irq_edge(int num) 414 { 415 if (eisa_irq_configured& (1<<num)) { 416 printk(KERN_WARNING 417 "IRQ %d polarity configured twice (last to edge)\n", 418 num); 419 } 420 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */ 421 eisa_irq_configured |= (1<<num); /* set the corresponding bit */ 422 } 423 424 static int __init eisa_irq_setup(char *str) 425 { 426 char *cur = str; 427 int val; 428 429 EISA_DBG("IRQ setup\n"); 430 while (cur != NULL) { 431 char *pe; 432 433 val = (int) simple_strtoul(cur, &pe, 0); 434 if (val > 15 || val < 0) { 435 printk(KERN_ERR "eisa: EISA irq value are 0-15\n"); 436 continue; 437 } 438 if (val == 2) { 439 val = 9; 440 } 441 eisa_make_irq_edge(val); /* clear the corresponding bit */ 442 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val); 443 444 if ((cur = strchr(cur, ','))) { 445 cur++; 446 } else { 447 break; 448 } 449 } 450 return 1; 451 } 452 453 __setup("eisa_irq_edge=", eisa_irq_setup); 454 455