1 /* 2 ** DINO manager 3 ** 4 ** (c) Copyright 1999 Red Hat Software 5 ** (c) Copyright 1999 SuSE GmbH 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** (c) Copyright 2000 Grant Grundler 8 ** (c) Copyright 2006 Helge Deller 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** This module provides access to Dino PCI bus (config/IOport spaces) 16 ** and helps manage Dino IRQ lines. 17 ** 18 ** Dino interrupt handling is a bit complicated. 19 ** Dino always writes to the broadcast EIR via irr0 for now. 20 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 21 ** Only one processor interrupt is used for the 11 IRQ line 22 ** inputs to dino. 23 ** 24 ** The different between Built-in Dino and Card-Mode 25 ** dino is in chip initialization and pci device initialization. 26 ** 27 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port 28 ** BARs are configured and used by the driver. Programming MMIO address 29 ** requires substantial knowledge of available Host I/O address ranges 30 ** is currently not supported. Port/Config accessor functions are the 31 ** same. "BIOS" differences are handled within the existing routines. 32 */ 33 34 /* Changes : 35 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 36 ** - added support for the integrated RS232. 37 */ 38 39 /* 40 ** TODO: create a virtual address for each Dino HPA. 41 ** GSC code might be able to do this since IODC data tells us 42 ** how many pages are used. PCI subsystem could (must?) do this 43 ** for PCI drivers devices which implement/use MMIO registers. 44 */ 45 46 #include <linux/config.h> 47 #include <linux/delay.h> 48 #include <linux/types.h> 49 #include <linux/kernel.h> 50 #include <linux/pci.h> 51 #include <linux/init.h> 52 #include <linux/ioport.h> 53 #include <linux/slab.h> 54 #include <linux/interrupt.h> /* for struct irqaction */ 55 #include <linux/spinlock.h> /* for spinlock_t and prototypes */ 56 57 #include <asm/pdc.h> 58 #include <asm/page.h> 59 #include <asm/system.h> 60 #include <asm/io.h> 61 #include <asm/hardware.h> 62 63 #include "gsc.h" 64 65 #undef DINO_DEBUG 66 67 #ifdef DINO_DEBUG 68 #define DBG(x...) printk(x) 69 #else 70 #define DBG(x...) 71 #endif 72 73 /* 74 ** Config accessor functions only pass in the 8-bit bus number 75 ** and not the 8-bit "PCI Segment" number. Each Dino will be 76 ** assigned a PCI bus number based on "when" it's discovered. 77 ** 78 ** The "secondary" bus number is set to this before calling 79 ** pci_scan_bus(). If any PPB's are present, the scan will 80 ** discover them and update the "secondary" and "subordinate" 81 ** fields in Dino's pci_bus structure. 82 ** 83 ** Changes in the configuration *will* result in a different 84 ** bus number for each dino. 85 */ 86 87 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 88 #define is_cujo(id) ((id)->hversion == 0x682) 89 90 #define DINO_IAR0 0x004 91 #define DINO_IODC_ADDR 0x008 92 #define DINO_IODC_DATA_0 0x008 93 #define DINO_IODC_DATA_1 0x008 94 #define DINO_IRR0 0x00C 95 #define DINO_IAR1 0x010 96 #define DINO_IRR1 0x014 97 #define DINO_IMR 0x018 98 #define DINO_IPR 0x01C 99 #define DINO_TOC_ADDR 0x020 100 #define DINO_ICR 0x024 101 #define DINO_ILR 0x028 102 #define DINO_IO_COMMAND 0x030 103 #define DINO_IO_STATUS 0x034 104 #define DINO_IO_CONTROL 0x038 105 #define DINO_IO_GSC_ERR_RESP 0x040 106 #define DINO_IO_ERR_INFO 0x044 107 #define DINO_IO_PCI_ERR_RESP 0x048 108 #define DINO_IO_FBB_EN 0x05c 109 #define DINO_IO_ADDR_EN 0x060 110 #define DINO_PCI_ADDR 0x064 111 #define DINO_CONFIG_DATA 0x068 112 #define DINO_IO_DATA 0x06c 113 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 114 #define DINO_GSC2X_CONFIG 0x7b4 115 #define DINO_GMASK 0x800 116 #define DINO_PAMR 0x804 117 #define DINO_PAPR 0x808 118 #define DINO_DAMODE 0x80c 119 #define DINO_PCICMD 0x810 120 #define DINO_PCISTS 0x814 121 #define DINO_MLTIM 0x81c 122 #define DINO_BRDG_FEAT 0x820 123 #define DINO_PCIROR 0x824 124 #define DINO_PCIWOR 0x828 125 #define DINO_TLTIM 0x830 126 127 #define DINO_IRQS 11 /* bits 0-10 are architected */ 128 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 129 #define DINO_LOCAL_IRQS (DINO_IRQS+1) 130 131 #define DINO_MASK_IRQ(x) (1<<(x)) 132 133 #define PCIINTA 0x001 134 #define PCIINTB 0x002 135 #define PCIINTC 0x004 136 #define PCIINTD 0x008 137 #define PCIINTE 0x010 138 #define PCIINTF 0x020 139 #define GSCEXTINT 0x040 140 /* #define xxx 0x080 - bit 7 is "default" */ 141 /* #define xxx 0x100 - bit 8 not used */ 142 /* #define xxx 0x200 - bit 9 not used */ 143 #define RS232INT 0x400 144 145 struct dino_device 146 { 147 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 148 spinlock_t dinosaur_pen; 149 unsigned long txn_addr; /* EIR addr to generate interrupt */ 150 u32 txn_data; /* EIR data assign to each dino */ 151 u32 imr; /* IRQ's which are enabled */ 152 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ 153 #ifdef DINO_DEBUG 154 unsigned int dino_irr0; /* save most recent IRQ line stat */ 155 #endif 156 }; 157 158 /* Looks nice and keeps the compiler happy */ 159 #define DINO_DEV(d) ((struct dino_device *) d) 160 161 162 /* 163 * Dino Configuration Space Accessor Functions 164 */ 165 166 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 167 168 /* 169 * keep the current highest bus count to assist in allocating busses. This 170 * tries to keep a global bus count total so that when we discover an 171 * entirely new bus, it can be given a unique bus number. 172 */ 173 static int dino_current_bus = 0; 174 175 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 176 int size, u32 *val) 177 { 178 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 179 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 180 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 181 void __iomem *base_addr = d->hba.base_addr; 182 unsigned long flags; 183 184 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 185 size); 186 spin_lock_irqsave(&d->dinosaur_pen, flags); 187 188 /* tell HW which CFG address */ 189 __raw_writel(v, base_addr + DINO_PCI_ADDR); 190 191 /* generate cfg read cycle */ 192 if (size == 1) { 193 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 194 } else if (size == 2) { 195 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 196 } else if (size == 4) { 197 *val = readl(base_addr + DINO_CONFIG_DATA); 198 } 199 200 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 201 return 0; 202 } 203 204 /* 205 * Dino address stepping "feature": 206 * When address stepping, Dino attempts to drive the bus one cycle too soon 207 * even though the type of cycle (config vs. MMIO) might be different. 208 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 209 */ 210 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 211 int size, u32 val) 212 { 213 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 214 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 215 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 216 void __iomem *base_addr = d->hba.base_addr; 217 unsigned long flags; 218 219 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 220 size); 221 spin_lock_irqsave(&d->dinosaur_pen, flags); 222 223 /* avoid address stepping feature */ 224 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 225 __raw_readl(base_addr + DINO_CONFIG_DATA); 226 227 /* tell HW which CFG address */ 228 __raw_writel(v, base_addr + DINO_PCI_ADDR); 229 /* generate cfg read cycle */ 230 if (size == 1) { 231 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 232 } else if (size == 2) { 233 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 234 } else if (size == 4) { 235 writel(val, base_addr + DINO_CONFIG_DATA); 236 } 237 238 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 239 return 0; 240 } 241 242 static struct pci_ops dino_cfg_ops = { 243 .read = dino_cfg_read, 244 .write = dino_cfg_write, 245 }; 246 247 248 /* 249 * Dino "I/O Port" Space Accessor Functions 250 * 251 * Many PCI devices don't require use of I/O port space (eg Tulip, 252 * NCR720) since they export the same registers to both MMIO and 253 * I/O port space. Performance is going to stink if drivers use 254 * I/O port instead of MMIO. 255 */ 256 257 #define DINO_PORT_IN(type, size, mask) \ 258 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 259 { \ 260 u##size v; \ 261 unsigned long flags; \ 262 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 263 /* tell HW which IO Port address */ \ 264 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 265 /* generate I/O PORT read cycle */ \ 266 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 267 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 268 return v; \ 269 } 270 271 DINO_PORT_IN(b, 8, 3) 272 DINO_PORT_IN(w, 16, 2) 273 DINO_PORT_IN(l, 32, 0) 274 275 #define DINO_PORT_OUT(type, size, mask) \ 276 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 277 { \ 278 unsigned long flags; \ 279 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 280 /* tell HW which IO port address */ \ 281 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 282 /* generate cfg write cycle */ \ 283 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 284 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 285 } 286 287 DINO_PORT_OUT(b, 8, 3) 288 DINO_PORT_OUT(w, 16, 2) 289 DINO_PORT_OUT(l, 32, 0) 290 291 struct pci_port_ops dino_port_ops = { 292 .inb = dino_in8, 293 .inw = dino_in16, 294 .inl = dino_in32, 295 .outb = dino_out8, 296 .outw = dino_out16, 297 .outl = dino_out32 298 }; 299 300 static void dino_disable_irq(unsigned int irq) 301 { 302 struct dino_device *dino_dev = irq_desc[irq].handler_data; 303 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 304 305 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 306 307 /* Clear the matching bit in the IMR register */ 308 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 309 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 310 } 311 312 static void dino_enable_irq(unsigned int irq) 313 { 314 struct dino_device *dino_dev = irq_desc[irq].handler_data; 315 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 316 u32 tmp; 317 318 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 319 320 /* 321 ** clear pending IRQ bits 322 ** 323 ** This does NOT change ILR state! 324 ** See comment below for ILR usage. 325 */ 326 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 327 328 /* set the matching bit in the IMR register */ 329 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 330 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 331 332 /* Emulate "Level Triggered" Interrupt 333 ** Basically, a driver is blowing it if the IRQ line is asserted 334 ** while the IRQ is disabled. But tulip.c seems to do that.... 335 ** Give 'em a kluge award and a nice round of applause! 336 ** 337 ** The gsc_write will generate an interrupt which invokes dino_isr(). 338 ** dino_isr() will read IPR and find nothing. But then catch this 339 ** when it also checks ILR. 340 */ 341 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 342 if (tmp & DINO_MASK_IRQ(local_irq)) { 343 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 344 __FUNCTION__, tmp); 345 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 346 } 347 } 348 349 static unsigned int dino_startup_irq(unsigned int irq) 350 { 351 dino_enable_irq(irq); 352 return 0; 353 } 354 355 static struct hw_interrupt_type dino_interrupt_type = { 356 .typename = "GSC-PCI", 357 .startup = dino_startup_irq, 358 .shutdown = dino_disable_irq, 359 .enable = dino_enable_irq, 360 .disable = dino_disable_irq, 361 .ack = no_ack_irq, 362 .end = no_end_irq, 363 }; 364 365 366 /* 367 * Handle a Processor interrupt generated by Dino. 368 * 369 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 370 * wedging the CPU. Could be removed or made optional at some point. 371 */ 372 static irqreturn_t 373 dino_isr(int irq, void *intr_dev, struct pt_regs *regs) 374 { 375 struct dino_device *dino_dev = intr_dev; 376 u32 mask; 377 int ilr_loop = 100; 378 379 /* read and acknowledge pending interrupts */ 380 #ifdef DINO_DEBUG 381 dino_dev->dino_irr0 = 382 #endif 383 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 384 385 if (mask == 0) 386 return IRQ_NONE; 387 388 ilr_again: 389 do { 390 int local_irq = __ffs(mask); 391 int irq = dino_dev->global_irq[local_irq]; 392 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 393 __FUNCTION__, irq, intr_dev, mask); 394 __do_IRQ(irq, regs); 395 mask &= ~(1 << local_irq); 396 } while (mask); 397 398 /* Support for level triggered IRQ lines. 399 ** 400 ** Dropping this support would make this routine *much* faster. 401 ** But since PCI requires level triggered IRQ line to share lines... 402 ** device drivers may assume lines are level triggered (and not 403 ** edge triggered like EISA/ISA can be). 404 */ 405 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 406 if (mask) { 407 if (--ilr_loop > 0) 408 goto ilr_again; 409 printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 410 dino_dev->hba.base_addr, mask); 411 return IRQ_NONE; 412 } 413 return IRQ_HANDLED; 414 } 415 416 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 417 { 418 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 419 if (irq == NO_IRQ) 420 return; 421 422 *irqp = irq; 423 dino->global_irq[local_irq] = irq; 424 } 425 426 static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 427 { 428 int irq; 429 struct dino_device *dino = ctrl; 430 431 switch (dev->id.sversion) { 432 case 0x00084: irq = 8; break; /* PS/2 */ 433 case 0x0008c: irq = 10; break; /* RS232 */ 434 case 0x00096: irq = 8; break; /* PS/2 */ 435 default: return; /* Unknown */ 436 } 437 438 dino_assign_irq(dino, irq, &dev->irq); 439 } 440 441 442 /* 443 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) 444 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) 445 */ 446 static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev) 447 { 448 u8 new_irq = dev->irq - 1; 449 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", 450 pci_name(dev), dev->irq, new_irq); 451 dev->irq = new_irq; 452 } 453 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); 454 455 456 static void __init 457 dino_bios_init(void) 458 { 459 DBG("dino_bios_init\n"); 460 } 461 462 /* 463 * dino_card_setup - Set up the memory space for a Dino in card mode. 464 * @bus: the bus under this dino 465 * 466 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 467 * to set up the addresses of the devices on this bus. 468 */ 469 #define _8MB 0x00800000UL 470 static void __init 471 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 472 { 473 int i; 474 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 475 struct resource *res; 476 char name[128]; 477 int size; 478 479 res = &dino_dev->hba.lmmio_space; 480 res->flags = IORESOURCE_MEM; 481 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 482 bus->bridge->bus_id); 483 res->name = kmalloc(size+1, GFP_KERNEL); 484 if(res->name) 485 strcpy((char *)res->name, name); 486 else 487 res->name = dino_dev->hba.lmmio_space.name; 488 489 490 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 491 F_EXTEND(0xf0000000UL) | _8MB, 492 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 493 struct list_head *ln, *tmp_ln; 494 495 printk(KERN_ERR "Dino: cannot attach bus %s\n", 496 bus->bridge->bus_id); 497 /* kill the bus, we can't do anything with it */ 498 list_for_each_safe(ln, tmp_ln, &bus->devices) { 499 struct pci_dev *dev = pci_dev_b(ln); 500 501 list_del(&dev->global_list); 502 list_del(&dev->bus_list); 503 } 504 505 return; 506 } 507 bus->resource[1] = res; 508 bus->resource[0] = &(dino_dev->hba.io_space); 509 510 /* Now tell dino what range it has */ 511 for (i = 1; i < 31; i++) { 512 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 513 break; 514 } 515 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", 516 i, res->start, base_addr + DINO_IO_ADDR_EN); 517 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 518 } 519 520 static void __init 521 dino_card_fixup(struct pci_dev *dev) 522 { 523 u32 irq_pin; 524 525 /* 526 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 527 ** Not sure they were ever productized. 528 ** Die here since we'll die later in dino_inb() anyway. 529 */ 530 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 531 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 532 } 533 534 /* 535 ** Set Latency Timer to 0xff (not a shared bus) 536 ** Set CACHELINE_SIZE. 537 */ 538 dino_cfg_write(dev->bus, dev->devfn, 539 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 540 541 /* 542 ** Program INT_LINE for card-mode devices. 543 ** The cards are hardwired according to this algorithm. 544 ** And it doesn't matter if PPB's are present or not since 545 ** the IRQ lines bypass the PPB. 546 ** 547 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 548 ** The additional "-1" adjusts for skewing the IRQ<->slot. 549 */ 550 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 551 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 552 553 /* Shouldn't really need to do this but it's in case someone tries 554 ** to bypass PCI services and look at the card themselves. 555 */ 556 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 557 } 558 559 /* The alignment contraints for PCI bridges under dino */ 560 #define DINO_BRIDGE_ALIGN 0x100000 561 562 563 static void __init 564 dino_fixup_bus(struct pci_bus *bus) 565 { 566 struct list_head *ln; 567 struct pci_dev *dev; 568 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 569 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num); 570 571 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 572 __FUNCTION__, bus, bus->secondary, 573 bus->bridge->platform_data); 574 575 /* Firmware doesn't set up card-mode dino, so we have to */ 576 if (is_card_dino(&dino_dev->hba.dev->id)) { 577 dino_card_setup(bus, dino_dev->hba.base_addr); 578 } else if(bus->parent == NULL) { 579 /* must have a dino above it, reparent the resources 580 * into the dino window */ 581 int i; 582 struct resource *res = &dino_dev->hba.lmmio_space; 583 584 bus->resource[0] = &(dino_dev->hba.io_space); 585 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 586 if(res[i].flags == 0) 587 break; 588 bus->resource[i+1] = &res[i]; 589 } 590 591 } else if(bus->self) { 592 int i; 593 594 pci_read_bridge_bases(bus); 595 596 597 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 598 if((bus->self->resource[i].flags & 599 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 600 continue; 601 602 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 603 /* There's a quirk to alignment of 604 * bridge memory resources: the start 605 * is the alignment and start-end is 606 * the size. However, firmware will 607 * have assigned start and end, so we 608 * need to take this into account */ 609 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 610 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 611 612 } 613 614 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", 615 bus->self->dev.bus_id, i, 616 bus->self->resource[i].start, 617 bus->self->resource[i].end); 618 pci_assign_resource(bus->self, i); 619 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", 620 bus->self->dev.bus_id, i, 621 bus->self->resource[i].start, 622 bus->self->resource[i].end); 623 } 624 } 625 626 627 list_for_each(ln, &bus->devices) { 628 int i; 629 630 dev = pci_dev_b(ln); 631 if (is_card_dino(&dino_dev->hba.dev->id)) 632 dino_card_fixup(dev); 633 634 /* 635 ** P2PB's only have 2 BARs, no IRQs. 636 ** I'd like to just ignore them for now. 637 */ 638 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 639 continue; 640 641 /* Adjust the I/O Port space addresses */ 642 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 643 struct resource *res = &dev->resource[i]; 644 if (res->flags & IORESOURCE_IO) { 645 res->start |= port_base; 646 res->end |= port_base; 647 } 648 #ifdef __LP64__ 649 /* Sign Extend MMIO addresses */ 650 else if (res->flags & IORESOURCE_MEM) { 651 res->start |= F_EXTEND(0UL); 652 res->end |= F_EXTEND(0UL); 653 } 654 #endif 655 } 656 /* null out the ROM resource if there is one (we don't 657 * care about an expansion rom on parisc, since it 658 * usually contains (x86) bios code) */ 659 dev->resource[PCI_ROM_RESOURCE].flags = 0; 660 661 if(dev->irq == 255) { 662 663 #define DINO_FIX_UNASSIGNED_INTERRUPTS 664 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 665 666 /* This code tries to assign an unassigned 667 * interrupt. Leave it disabled unless you 668 * *really* know what you're doing since the 669 * pin<->interrupt line mapping varies by bus 670 * and machine */ 671 672 u32 irq_pin; 673 674 dino_cfg_read(dev->bus, dev->devfn, 675 PCI_INTERRUPT_PIN, 1, &irq_pin); 676 irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 677 printk(KERN_WARNING "Device %s has undefined IRQ, " 678 "setting to %d\n", pci_name(dev), irq_pin); 679 dino_cfg_write(dev->bus, dev->devfn, 680 PCI_INTERRUPT_LINE, 1, irq_pin); 681 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 682 #else 683 dev->irq = 65535; 684 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 685 #endif 686 } else { 687 /* Adjust INT_LINE for that busses region */ 688 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 689 } 690 } 691 } 692 693 694 struct pci_bios_ops dino_bios_ops = { 695 .init = dino_bios_init, 696 .fixup_bus = dino_fixup_bus 697 }; 698 699 700 /* 701 * Initialise a DINO controller chip 702 */ 703 static void __init 704 dino_card_init(struct dino_device *dino_dev) 705 { 706 u32 brdg_feat = 0x00784e05; 707 unsigned long status; 708 709 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); 710 if (status & 0x0000ff80) { 711 __raw_writel(0x00000005, 712 dino_dev->hba.base_addr+DINO_IO_COMMAND); 713 udelay(1); 714 } 715 716 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 717 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 718 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 719 720 #if 1 721 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 722 /* 723 ** PCX-L processors don't support XQL like Dino wants it. 724 ** PCX-L2 ignore XQL signal and it doesn't matter. 725 */ 726 brdg_feat &= ~0x4; /* UXQL */ 727 #endif 728 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 729 730 /* 731 ** Don't enable address decoding until we know which I/O range 732 ** currently is available from the host. Only affects MMIO 733 ** and not I/O port space. 734 */ 735 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 736 737 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 738 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 739 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 740 741 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 742 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 743 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 744 745 /* Disable PAMR before writing PAPR */ 746 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 747 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 748 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 749 750 /* 751 ** Dino ERS encourages enabling FBB (0x6f). 752 ** We can't until we know *all* devices below us can support it. 753 ** (Something in device configuration header tells us). 754 */ 755 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 756 757 /* Somewhere, the PCI spec says give devices 1 second 758 ** to recover from the #RESET being de-asserted. 759 ** Experience shows most devices only need 10ms. 760 ** This short-cut speeds up booting significantly. 761 */ 762 mdelay(pci_post_reset_delay); 763 } 764 765 static int __init 766 dino_bridge_init(struct dino_device *dino_dev, const char *name) 767 { 768 unsigned long io_addr; 769 int result, i, count=0; 770 struct resource *res, *prevres = NULL; 771 /* 772 * Decoding IO_ADDR_EN only works for Built-in Dino 773 * since PDC has already initialized this. 774 */ 775 776 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 777 if (io_addr == 0) { 778 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 779 return -ENODEV; 780 } 781 782 res = &dino_dev->hba.lmmio_space; 783 for (i = 0; i < 32; i++) { 784 unsigned long start, end; 785 786 if((io_addr & (1 << i)) == 0) 787 continue; 788 789 start = F_EXTEND(0xf0000000UL) | (i << 23); 790 end = start + 8 * 1024 * 1024 - 1; 791 792 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 793 start, end); 794 795 if(prevres && prevres->end + 1 == start) { 796 prevres->end = end; 797 } else { 798 if(count >= DINO_MAX_LMMIO_RESOURCES) { 799 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 800 break; 801 } 802 prevres = res; 803 res->start = start; 804 res->end = end; 805 res->flags = IORESOURCE_MEM; 806 res->name = kmalloc(64, GFP_KERNEL); 807 if(res->name) 808 snprintf((char *)res->name, 64, "%s LMMIO %d", 809 name, count); 810 res++; 811 count++; 812 } 813 } 814 815 res = &dino_dev->hba.lmmio_space; 816 817 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 818 if(res[i].flags == 0) 819 break; 820 821 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 822 if (result < 0) { 823 printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end); 824 return result; 825 } 826 } 827 return 0; 828 } 829 830 static int __init dino_common_init(struct parisc_device *dev, 831 struct dino_device *dino_dev, const char *name) 832 { 833 int status; 834 u32 eim; 835 struct gsc_irq gsc_irq; 836 struct resource *res; 837 838 pcibios_register_hba(&dino_dev->hba); 839 840 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 841 pci_port = &dino_port_ops; 842 843 /* 844 ** Note: SMP systems can make use of IRR1/IAR1 registers 845 ** But it won't buy much performance except in very 846 ** specific applications/configurations. Note Dino 847 ** still only has 11 IRQ input lines - just map some of them 848 ** to a different processor. 849 */ 850 dev->irq = gsc_alloc_irq(&gsc_irq); 851 dino_dev->txn_addr = gsc_irq.txn_addr; 852 dino_dev->txn_data = gsc_irq.txn_data; 853 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 854 855 /* 856 ** Dino needs a PA "IRQ" to get a processor's attention. 857 ** arch/parisc/kernel/irq.c returns an EIRR bit. 858 */ 859 if (dev->irq < 0) { 860 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 861 return 1; 862 } 863 864 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 865 if (status) { 866 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 867 name, status); 868 return 1; 869 } 870 871 /* Support the serial port which is sometimes attached on built-in 872 * Dino / Cujo chips. 873 */ 874 875 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 876 877 /* 878 ** This enables DINO to generate interrupts when it sees 879 ** any of its inputs *change*. Just asserting an IRQ 880 ** before it's enabled (ie unmasked) isn't good enough. 881 */ 882 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 883 884 /* 885 ** Some platforms don't clear Dino's IRR0 register at boot time. 886 ** Reading will clear it now. 887 */ 888 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 889 890 /* allocate I/O Port resource region */ 891 res = &dino_dev->hba.io_space; 892 if (!is_cujo(&dev->id)) { 893 res->name = "Dino I/O Port"; 894 } else { 895 res->name = "Cujo I/O Port"; 896 } 897 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 898 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 899 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 900 if (request_resource(&ioport_resource, res) < 0) { 901 printk(KERN_ERR "%s: request I/O Port region failed " 902 "0x%lx/%lx (hpa 0x%p)\n", 903 name, res->start, res->end, dino_dev->hba.base_addr); 904 return 1; 905 } 906 907 return 0; 908 } 909 910 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 911 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 912 #define CUJO_RAVEN_BADPAGE 0x01003000UL 913 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL 914 915 static const char *dino_vers[] = { 916 "2.0", 917 "2.1", 918 "3.0", 919 "3.1" 920 }; 921 922 static const char *cujo_vers[] = { 923 "1.0", 924 "2.0" 925 }; 926 927 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 928 929 /* 930 ** Determine if dino should claim this chip (return 0) or not (return 1). 931 ** If so, initialize the chip appropriately (card-mode vs bridge mode). 932 ** Much of the initialization is common though. 933 */ 934 static int __init dino_probe(struct parisc_device *dev) 935 { 936 struct dino_device *dino_dev; // Dino specific control struct 937 const char *version = "unknown"; 938 char *name; 939 int is_cujo = 0; 940 struct pci_bus *bus; 941 unsigned long hpa = dev->hpa.start; 942 943 name = "Dino"; 944 if (is_card_dino(&dev->id)) { 945 version = "3.x (card mode)"; 946 } else { 947 if (!is_cujo(&dev->id)) { 948 if (dev->id.hversion_rev < 4) { 949 version = dino_vers[dev->id.hversion_rev]; 950 } 951 } else { 952 name = "Cujo"; 953 is_cujo = 1; 954 if (dev->id.hversion_rev < 2) { 955 version = cujo_vers[dev->id.hversion_rev]; 956 } 957 } 958 } 959 960 printk("%s version %s found at 0x%lx\n", name, version, hpa); 961 962 if (!request_mem_region(hpa, PAGE_SIZE, name)) { 963 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n", 964 hpa); 965 return 1; 966 } 967 968 /* Check for bugs */ 969 if (is_cujo && dev->id.hversion_rev == 1) { 970 #ifdef CONFIG_IOMMU_CCIO 971 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 972 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { 973 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 974 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 975 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 976 } else { 977 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); 978 } 979 #endif 980 } else if (!is_cujo && !is_card_dino(&dev->id) && 981 dev->id.hversion_rev < 3) { 982 printk(KERN_WARNING 983 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 984 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 985 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 986 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 987 dev->id.hversion_rev); 988 /* REVISIT: why are C200/C240 listed in the README table but not 989 ** "Models affected"? Could be an omission in the original literature. 990 */ 991 } 992 993 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); 994 if (!dino_dev) { 995 printk("dino_init_chip - couldn't alloc dino_device\n"); 996 return 1; 997 } 998 999 dino_dev->hba.dev = dev; 1000 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); 1001 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */ 1002 spin_lock_init(&dino_dev->dinosaur_pen); 1003 dino_dev->hba.iommu = ccio_get_iommu(dev); 1004 1005 if (is_card_dino(&dev->id)) { 1006 dino_card_init(dino_dev); 1007 } else { 1008 dino_bridge_init(dino_dev, name); 1009 } 1010 1011 if (dino_common_init(dev, dino_dev, name)) 1012 return 1; 1013 1014 dev->dev.platform_data = dino_dev; 1015 1016 /* 1017 ** It's not used to avoid chicken/egg problems 1018 ** with configuration accessor functions. 1019 */ 1020 bus = pci_scan_bus_parented(&dev->dev, dino_current_bus, 1021 &dino_cfg_ops, NULL); 1022 if(bus) { 1023 pci_bus_add_devices(bus); 1024 /* This code *depends* on scanning being single threaded 1025 * if it isn't, this global bus number count will fail 1026 */ 1027 dino_current_bus = bus->subordinate + 1; 1028 pci_bus_assign_resources(bus); 1029 } else { 1030 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus); 1031 /* increment the bus number in case of duplicates */ 1032 dino_current_bus++; 1033 } 1034 dino_dev->hba.hba_bus = bus; 1035 return 0; 1036 } 1037 1038 /* 1039 * Normally, we would just test sversion. But the Elroy PCI adapter has 1040 * the same sversion as Dino, so we have to check hversion as well. 1041 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1042 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1043 * For card-mode Dino, most machines report an sversion of 9D. But 715 1044 * and 725 firmware misreport it as 0x08080 for no adequately explained 1045 * reason. 1046 */ 1047 static struct parisc_device_id dino_tbl[] = { 1048 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1049 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ 1050 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1051 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1052 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1053 { 0, } 1054 }; 1055 1056 static struct parisc_driver dino_driver = { 1057 .name = "dino", 1058 .id_table = dino_tbl, 1059 .probe = dino_probe, 1060 }; 1061 1062 /* 1063 * One time initialization to let the world know Dino is here. 1064 * This is the only routine which is NOT static. 1065 * Must be called exactly once before pci_init(). 1066 */ 1067 int __init dino_init(void) 1068 { 1069 register_parisc_driver(&dino_driver); 1070 return 0; 1071 } 1072 1073