xref: /linux/drivers/parisc/dino.c (revision 507e190946297c34a27d9366b0661d5e506fdd03)
1 /*
2 **	DINO manager
3 **
4 **	(c) Copyright 1999 Red Hat Software
5 **	(c) Copyright 1999 SuSE GmbH
6 **	(c) Copyright 1999,2000 Hewlett-Packard Company
7 **	(c) Copyright 2000 Grant Grundler
8 **	(c) Copyright 2006 Helge Deller
9 **
10 **	This program is free software; you can redistribute it and/or modify
11 **	it under the terms of the GNU General Public License as published by
12 **      the Free Software Foundation; either version 2 of the License, or
13 **      (at your option) any later version.
14 **
15 **	This module provides access to Dino PCI bus (config/IOport spaces)
16 **	and helps manage Dino IRQ lines.
17 **
18 **	Dino interrupt handling is a bit complicated.
19 **	Dino always writes to the broadcast EIR via irr0 for now.
20 **	(BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
21 **	Only one processor interrupt is used for the 11 IRQ line
22 **	inputs to dino.
23 **
24 **	The different between Built-in Dino and Card-Mode
25 **	dino is in chip initialization and pci device initialization.
26 **
27 **	Linux drivers can only use Card-Mode Dino if pci devices I/O port
28 **	BARs are configured and used by the driver. Programming MMIO address
29 **	requires substantial knowledge of available Host I/O address ranges
30 **	is currently not supported.  Port/Config accessor functions are the
31 **	same. "BIOS" differences are handled within the existing routines.
32 */
33 
34 /*	Changes :
35 **	2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
36 **		- added support for the integrated RS232.
37 */
38 
39 /*
40 ** TODO: create a virtual address for each Dino HPA.
41 **       GSC code might be able to do this since IODC data tells us
42 **       how many pages are used. PCI subsystem could (must?) do this
43 **       for PCI drivers devices which implement/use MMIO registers.
44 */
45 
46 #include <linux/delay.h>
47 #include <linux/types.h>
48 #include <linux/kernel.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/ioport.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h>	/* for struct irqaction */
54 #include <linux/spinlock.h>	/* for spinlock_t and prototypes */
55 
56 #include <asm/pdc.h>
57 #include <asm/page.h>
58 #include <asm/io.h>
59 #include <asm/hardware.h>
60 
61 #include "gsc.h"
62 
63 #undef DINO_DEBUG
64 
65 #ifdef DINO_DEBUG
66 #define DBG(x...) printk(x)
67 #else
68 #define DBG(x...)
69 #endif
70 
71 /*
72 ** Config accessor functions only pass in the 8-bit bus number
73 ** and not the 8-bit "PCI Segment" number. Each Dino will be
74 ** assigned a PCI bus number based on "when" it's discovered.
75 **
76 ** The "secondary" bus number is set to this before calling
77 ** pci_scan_bus(). If any PPB's are present, the scan will
78 ** discover them and update the "secondary" and "subordinate"
79 ** fields in Dino's pci_bus structure.
80 **
81 ** Changes in the configuration *will* result in a different
82 ** bus number for each dino.
83 */
84 
85 #define is_card_dino(id)	((id)->hw_type == HPHW_A_DMA)
86 #define is_cujo(id)		((id)->hversion == 0x682)
87 
88 #define DINO_IAR0		0x004
89 #define DINO_IODC_ADDR		0x008
90 #define DINO_IODC_DATA_0	0x008
91 #define DINO_IODC_DATA_1	0x008
92 #define DINO_IRR0		0x00C
93 #define DINO_IAR1		0x010
94 #define DINO_IRR1		0x014
95 #define DINO_IMR		0x018
96 #define DINO_IPR		0x01C
97 #define DINO_TOC_ADDR		0x020
98 #define DINO_ICR		0x024
99 #define DINO_ILR		0x028
100 #define DINO_IO_COMMAND		0x030
101 #define DINO_IO_STATUS		0x034
102 #define DINO_IO_CONTROL		0x038
103 #define DINO_IO_GSC_ERR_RESP	0x040
104 #define DINO_IO_ERR_INFO	0x044
105 #define DINO_IO_PCI_ERR_RESP	0x048
106 #define DINO_IO_FBB_EN		0x05c
107 #define DINO_IO_ADDR_EN		0x060
108 #define DINO_PCI_ADDR		0x064
109 #define DINO_CONFIG_DATA	0x068
110 #define DINO_IO_DATA		0x06c
111 #define DINO_MEM_DATA		0x070	/* Dino 3.x only */
112 #define DINO_GSC2X_CONFIG	0x7b4
113 #define DINO_GMASK		0x800
114 #define DINO_PAMR		0x804
115 #define DINO_PAPR		0x808
116 #define DINO_DAMODE		0x80c
117 #define DINO_PCICMD		0x810
118 #define DINO_PCISTS		0x814
119 #define DINO_MLTIM		0x81c
120 #define DINO_BRDG_FEAT		0x820
121 #define DINO_PCIROR		0x824
122 #define DINO_PCIWOR		0x828
123 #define DINO_TLTIM		0x830
124 
125 #define DINO_IRQS 11		/* bits 0-10 are architected */
126 #define DINO_IRR_MASK	0x5ff	/* only 10 bits are implemented */
127 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
128 
129 #define DINO_MASK_IRQ(x)	(1<<(x))
130 
131 #define PCIINTA   0x001
132 #define PCIINTB   0x002
133 #define PCIINTC   0x004
134 #define PCIINTD   0x008
135 #define PCIINTE   0x010
136 #define PCIINTF   0x020
137 #define GSCEXTINT 0x040
138 /* #define xxx       0x080 - bit 7 is "default" */
139 /* #define xxx    0x100 - bit 8 not used */
140 /* #define xxx    0x200 - bit 9 not used */
141 #define RS232INT  0x400
142 
143 struct dino_device
144 {
145 	struct pci_hba_data	hba;	/* 'C' inheritance - must be first */
146 	spinlock_t		dinosaur_pen;
147 	unsigned long		txn_addr; /* EIR addr to generate interrupt */
148 	u32			txn_data; /* EIR data assign to each dino */
149 	u32 			imr;	  /* IRQ's which are enabled */
150 	int			global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
151 #ifdef DINO_DEBUG
152 	unsigned int		dino_irr0; /* save most recent IRQ line stat */
153 #endif
154 };
155 
156 /* Looks nice and keeps the compiler happy */
157 #define DINO_DEV(d) ({				\
158 	void *__pdata = d;			\
159 	BUG_ON(!__pdata);			\
160 	(struct dino_device *)__pdata; })
161 
162 
163 /*
164  * Dino Configuration Space Accessor Functions
165  */
166 
167 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
168 
169 /*
170  * keep the current highest bus count to assist in allocating busses.  This
171  * tries to keep a global bus count total so that when we discover an
172  * entirely new bus, it can be given a unique bus number.
173  */
174 static int dino_current_bus = 0;
175 
176 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
177 		int size, u32 *val)
178 {
179 	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
180 	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
181 	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
182 	void __iomem *base_addr = d->hba.base_addr;
183 	unsigned long flags;
184 
185 	DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
186 									size);
187 	spin_lock_irqsave(&d->dinosaur_pen, flags);
188 
189 	/* tell HW which CFG address */
190 	__raw_writel(v, base_addr + DINO_PCI_ADDR);
191 
192 	/* generate cfg read cycle */
193 	if (size == 1) {
194 		*val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
195 	} else if (size == 2) {
196 		*val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
197 	} else if (size == 4) {
198 		*val = readl(base_addr + DINO_CONFIG_DATA);
199 	}
200 
201 	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
202 	return 0;
203 }
204 
205 /*
206  * Dino address stepping "feature":
207  * When address stepping, Dino attempts to drive the bus one cycle too soon
208  * even though the type of cycle (config vs. MMIO) might be different.
209  * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
210  */
211 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
212 	int size, u32 val)
213 {
214 	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
215 	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
216 	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
217 	void __iomem *base_addr = d->hba.base_addr;
218 	unsigned long flags;
219 
220 	DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
221 									size);
222 	spin_lock_irqsave(&d->dinosaur_pen, flags);
223 
224 	/* avoid address stepping feature */
225 	__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
226 	__raw_readl(base_addr + DINO_CONFIG_DATA);
227 
228 	/* tell HW which CFG address */
229 	__raw_writel(v, base_addr + DINO_PCI_ADDR);
230 	/* generate cfg read cycle */
231 	if (size == 1) {
232 		writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
233 	} else if (size == 2) {
234 		writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
235 	} else if (size == 4) {
236 		writel(val, base_addr + DINO_CONFIG_DATA);
237 	}
238 
239 	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
240 	return 0;
241 }
242 
243 static struct pci_ops dino_cfg_ops = {
244 	.read =		dino_cfg_read,
245 	.write =	dino_cfg_write,
246 };
247 
248 
249 /*
250  * Dino "I/O Port" Space Accessor Functions
251  *
252  * Many PCI devices don't require use of I/O port space (eg Tulip,
253  * NCR720) since they export the same registers to both MMIO and
254  * I/O port space.  Performance is going to stink if drivers use
255  * I/O port instead of MMIO.
256  */
257 
258 #define DINO_PORT_IN(type, size, mask) \
259 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
260 { \
261 	u##size v; \
262 	unsigned long flags; \
263 	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
264 	/* tell HW which IO Port address */ \
265 	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
266 	/* generate I/O PORT read cycle */ \
267 	v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
268 	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
269 	return v; \
270 }
271 
272 DINO_PORT_IN(b,  8, 3)
273 DINO_PORT_IN(w, 16, 2)
274 DINO_PORT_IN(l, 32, 0)
275 
276 #define DINO_PORT_OUT(type, size, mask) \
277 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
278 { \
279 	unsigned long flags; \
280 	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
281 	/* tell HW which IO port address */ \
282 	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
283 	/* generate cfg write cycle */ \
284 	write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
285 	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
286 }
287 
288 DINO_PORT_OUT(b,  8, 3)
289 DINO_PORT_OUT(w, 16, 2)
290 DINO_PORT_OUT(l, 32, 0)
291 
292 static struct pci_port_ops dino_port_ops = {
293 	.inb	= dino_in8,
294 	.inw	= dino_in16,
295 	.inl	= dino_in32,
296 	.outb	= dino_out8,
297 	.outw	= dino_out16,
298 	.outl	= dino_out32
299 };
300 
301 static void dino_mask_irq(struct irq_data *d)
302 {
303 	struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
304 	int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
305 
306 	DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
307 
308 	/* Clear the matching bit in the IMR register */
309 	dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
310 	__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
311 }
312 
313 static void dino_unmask_irq(struct irq_data *d)
314 {
315 	struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
316 	int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
317 	u32 tmp;
318 
319 	DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
320 
321 	/*
322 	** clear pending IRQ bits
323 	**
324 	** This does NOT change ILR state!
325 	** See comment below for ILR usage.
326 	*/
327 	__raw_readl(dino_dev->hba.base_addr+DINO_IPR);
328 
329 	/* set the matching bit in the IMR register */
330 	dino_dev->imr |= DINO_MASK_IRQ(local_irq);	/* used in dino_isr() */
331 	__raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
332 
333 	/* Emulate "Level Triggered" Interrupt
334 	** Basically, a driver is blowing it if the IRQ line is asserted
335 	** while the IRQ is disabled.  But tulip.c seems to do that....
336 	** Give 'em a kluge award and a nice round of applause!
337 	**
338 	** The gsc_write will generate an interrupt which invokes dino_isr().
339 	** dino_isr() will read IPR and find nothing. But then catch this
340 	** when it also checks ILR.
341 	*/
342 	tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
343 	if (tmp & DINO_MASK_IRQ(local_irq)) {
344 		DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
345 				__func__, tmp);
346 		gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
347 	}
348 }
349 
350 static struct irq_chip dino_interrupt_type = {
351 	.name		= "GSC-PCI",
352 	.irq_unmask	= dino_unmask_irq,
353 	.irq_mask	= dino_mask_irq,
354 };
355 
356 
357 /*
358  * Handle a Processor interrupt generated by Dino.
359  *
360  * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
361  * wedging the CPU. Could be removed or made optional at some point.
362  */
363 static irqreturn_t dino_isr(int irq, void *intr_dev)
364 {
365 	struct dino_device *dino_dev = intr_dev;
366 	u32 mask;
367 	int ilr_loop = 100;
368 
369 	/* read and acknowledge pending interrupts */
370 #ifdef DINO_DEBUG
371 	dino_dev->dino_irr0 =
372 #endif
373 	mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
374 
375 	if (mask == 0)
376 		return IRQ_NONE;
377 
378 ilr_again:
379 	do {
380 		int local_irq = __ffs(mask);
381 		int irq = dino_dev->global_irq[local_irq];
382 		DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
383 			__func__, irq, intr_dev, mask);
384 		generic_handle_irq(irq);
385 		mask &= ~(1 << local_irq);
386 	} while (mask);
387 
388 	/* Support for level triggered IRQ lines.
389 	**
390 	** Dropping this support would make this routine *much* faster.
391 	** But since PCI requires level triggered IRQ line to share lines...
392 	** device drivers may assume lines are level triggered (and not
393 	** edge triggered like EISA/ISA can be).
394 	*/
395 	mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
396 	if (mask) {
397 		if (--ilr_loop > 0)
398 			goto ilr_again;
399 		printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n",
400 		       dino_dev->hba.base_addr, mask);
401 		return IRQ_NONE;
402 	}
403 	return IRQ_HANDLED;
404 }
405 
406 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
407 {
408 	int irq = gsc_assign_irq(&dino_interrupt_type, dino);
409 	if (irq == NO_IRQ)
410 		return;
411 
412 	*irqp = irq;
413 	dino->global_irq[local_irq] = irq;
414 }
415 
416 static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
417 {
418 	int irq;
419 	struct dino_device *dino = ctrl;
420 
421 	switch (dev->id.sversion) {
422 		case 0x00084:	irq =  8; break; /* PS/2 */
423 		case 0x0008c:	irq = 10; break; /* RS232 */
424 		case 0x00096:	irq =  8; break; /* PS/2 */
425 		default:	return;		 /* Unknown */
426 	}
427 
428 	dino_assign_irq(dino, irq, &dev->irq);
429 }
430 
431 
432 /*
433  * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
434  * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
435  */
436 static void quirk_cirrus_cardbus(struct pci_dev *dev)
437 {
438 	u8 new_irq = dev->irq - 1;
439 	printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
440 			pci_name(dev), dev->irq, new_irq);
441 	dev->irq = new_irq;
442 }
443 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
444 
445 
446 static void __init
447 dino_bios_init(void)
448 {
449 	DBG("dino_bios_init\n");
450 }
451 
452 /*
453  * dino_card_setup - Set up the memory space for a Dino in card mode.
454  * @bus: the bus under this dino
455  *
456  * Claim an 8MB chunk of unused IO space and call the generic PCI routines
457  * to set up the addresses of the devices on this bus.
458  */
459 #define _8MB 0x00800000UL
460 static void __init
461 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
462 {
463 	int i;
464 	struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
465 	struct resource *res;
466 	char name[128];
467 	int size;
468 
469 	res = &dino_dev->hba.lmmio_space;
470 	res->flags = IORESOURCE_MEM;
471 	size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
472 			 dev_name(bus->bridge));
473 	res->name = kmalloc(size+1, GFP_KERNEL);
474 	if(res->name)
475 		strcpy((char *)res->name, name);
476 	else
477 		res->name = dino_dev->hba.lmmio_space.name;
478 
479 
480 	if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
481 				F_EXTEND(0xf0000000UL) | _8MB,
482 				F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
483 		struct pci_dev *dev, *tmp;
484 
485 		printk(KERN_ERR "Dino: cannot attach bus %s\n",
486 		       dev_name(bus->bridge));
487 		/* kill the bus, we can't do anything with it */
488 		list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
489 			list_del(&dev->bus_list);
490 		}
491 
492 		return;
493 	}
494 	bus->resource[1] = res;
495 	bus->resource[0] = &(dino_dev->hba.io_space);
496 
497 	/* Now tell dino what range it has */
498 	for (i = 1; i < 31; i++) {
499 		if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
500 			break;
501 	}
502 	DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
503 	    i, res->start, base_addr + DINO_IO_ADDR_EN);
504 	__raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
505 }
506 
507 static void __init
508 dino_card_fixup(struct pci_dev *dev)
509 {
510 	u32 irq_pin;
511 
512 	/*
513 	** REVISIT: card-mode PCI-PCI expansion chassis do exist.
514 	**         Not sure they were ever productized.
515 	**         Die here since we'll die later in dino_inb() anyway.
516 	*/
517 	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
518 		panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
519 	}
520 
521 	/*
522 	** Set Latency Timer to 0xff (not a shared bus)
523 	** Set CACHELINE_SIZE.
524 	*/
525 	dino_cfg_write(dev->bus, dev->devfn,
526 		       PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
527 
528 	/*
529 	** Program INT_LINE for card-mode devices.
530 	** The cards are hardwired according to this algorithm.
531 	** And it doesn't matter if PPB's are present or not since
532 	** the IRQ lines bypass the PPB.
533 	**
534 	** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
535 	** The additional "-1" adjusts for skewing the IRQ<->slot.
536 	*/
537 	dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
538 	dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
539 
540 	/* Shouldn't really need to do this but it's in case someone tries
541 	** to bypass PCI services and look at the card themselves.
542 	*/
543 	dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
544 }
545 
546 /* The alignment contraints for PCI bridges under dino */
547 #define DINO_BRIDGE_ALIGN 0x100000
548 
549 
550 static void __init
551 dino_fixup_bus(struct pci_bus *bus)
552 {
553         struct pci_dev *dev;
554         struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
555 
556 	DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
557 	    __func__, bus, bus->busn_res.start,
558 	    bus->bridge->platform_data);
559 
560 	/* Firmware doesn't set up card-mode dino, so we have to */
561 	if (is_card_dino(&dino_dev->hba.dev->id)) {
562 		dino_card_setup(bus, dino_dev->hba.base_addr);
563 	} else if (bus->parent) {
564 		int i;
565 
566 		pci_read_bridge_bases(bus);
567 
568 
569 		for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
570 			if((bus->self->resource[i].flags &
571 			    (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
572 				continue;
573 
574 			if(bus->self->resource[i].flags & IORESOURCE_MEM) {
575 				/* There's a quirk to alignment of
576 				 * bridge memory resources: the start
577 				 * is the alignment and start-end is
578 				 * the size.  However, firmware will
579 				 * have assigned start and end, so we
580 				 * need to take this into account */
581 				bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
582 				bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
583 
584 			}
585 
586 			DBG("DEBUG %s assigning %d [%pR]\n",
587 			    dev_name(&bus->self->dev), i,
588 			    &bus->self->resource[i]);
589 			WARN_ON(pci_assign_resource(bus->self, i));
590 			DBG("DEBUG %s after assign %d [%pR]\n",
591 			    dev_name(&bus->self->dev), i,
592 			    &bus->self->resource[i]);
593 		}
594 	}
595 
596 
597 	list_for_each_entry(dev, &bus->devices, bus_list) {
598 		if (is_card_dino(&dino_dev->hba.dev->id))
599 			dino_card_fixup(dev);
600 
601 		/*
602 		** P2PB's only have 2 BARs, no IRQs.
603 		** I'd like to just ignore them for now.
604 		*/
605 		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)  {
606 			pcibios_init_bridge(dev);
607 			continue;
608 		}
609 
610 		/* null out the ROM resource if there is one (we don't
611 		 * care about an expansion rom on parisc, since it
612 		 * usually contains (x86) bios code) */
613 		dev->resource[PCI_ROM_RESOURCE].flags = 0;
614 
615 		if(dev->irq == 255) {
616 
617 #define DINO_FIX_UNASSIGNED_INTERRUPTS
618 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
619 
620 			/* This code tries to assign an unassigned
621 			 * interrupt.  Leave it disabled unless you
622 			 * *really* know what you're doing since the
623 			 * pin<->interrupt line mapping varies by bus
624 			 * and machine */
625 
626 			u32 irq_pin;
627 
628 			dino_cfg_read(dev->bus, dev->devfn,
629 				      PCI_INTERRUPT_PIN, 1, &irq_pin);
630 			irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
631 			printk(KERN_WARNING "Device %s has undefined IRQ, "
632 					"setting to %d\n", pci_name(dev), irq_pin);
633 			dino_cfg_write(dev->bus, dev->devfn,
634 				       PCI_INTERRUPT_LINE, 1, irq_pin);
635 			dino_assign_irq(dino_dev, irq_pin, &dev->irq);
636 #else
637 			dev->irq = 65535;
638 			printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
639 #endif
640 		} else {
641 			/* Adjust INT_LINE for that busses region */
642 			dino_assign_irq(dino_dev, dev->irq, &dev->irq);
643 		}
644 	}
645 }
646 
647 
648 static struct pci_bios_ops dino_bios_ops = {
649 	.init		= dino_bios_init,
650 	.fixup_bus	= dino_fixup_bus
651 };
652 
653 
654 /*
655  *	Initialise a DINO controller chip
656  */
657 static void __init
658 dino_card_init(struct dino_device *dino_dev)
659 {
660 	u32 brdg_feat = 0x00784e05;
661 	unsigned long status;
662 
663 	status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
664 	if (status & 0x0000ff80) {
665 		__raw_writel(0x00000005,
666 				dino_dev->hba.base_addr+DINO_IO_COMMAND);
667 		udelay(1);
668 	}
669 
670 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
671 	__raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
672 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
673 
674 #if 1
675 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
676 	/*
677 	** PCX-L processors don't support XQL like Dino wants it.
678 	** PCX-L2 ignore XQL signal and it doesn't matter.
679 	*/
680 	brdg_feat &= ~0x4;	/* UXQL */
681 #endif
682 	__raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
683 
684 	/*
685 	** Don't enable address decoding until we know which I/O range
686 	** currently is available from the host. Only affects MMIO
687 	** and not I/O port space.
688 	*/
689 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
690 
691 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
692 	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
693 	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
694 
695 	__raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
696 	__raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
697 	__raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
698 
699 	/* Disable PAMR before writing PAPR */
700 	__raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
701 	__raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
702 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
703 
704 	/*
705 	** Dino ERS encourages enabling FBB (0x6f).
706 	** We can't until we know *all* devices below us can support it.
707 	** (Something in device configuration header tells us).
708 	*/
709 	__raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
710 
711 	/* Somewhere, the PCI spec says give devices 1 second
712 	** to recover from the #RESET being de-asserted.
713 	** Experience shows most devices only need 10ms.
714 	** This short-cut speeds up booting significantly.
715 	*/
716 	mdelay(pci_post_reset_delay);
717 }
718 
719 static int __init
720 dino_bridge_init(struct dino_device *dino_dev, const char *name)
721 {
722 	unsigned long io_addr;
723 	int result, i, count=0;
724 	struct resource *res, *prevres = NULL;
725 	/*
726 	 * Decoding IO_ADDR_EN only works for Built-in Dino
727 	 * since PDC has already initialized this.
728 	 */
729 
730 	io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
731 	if (io_addr == 0) {
732 		printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
733 		return -ENODEV;
734 	}
735 
736 	res = &dino_dev->hba.lmmio_space;
737 	for (i = 0; i < 32; i++) {
738 		unsigned long start, end;
739 
740 		if((io_addr & (1 << i)) == 0)
741 			continue;
742 
743 		start = F_EXTEND(0xf0000000UL) | (i << 23);
744 		end = start + 8 * 1024 * 1024 - 1;
745 
746 		DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
747 		    start, end);
748 
749 		if(prevres && prevres->end + 1 == start) {
750 			prevres->end = end;
751 		} else {
752 			if(count >= DINO_MAX_LMMIO_RESOURCES) {
753 				printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
754 				break;
755 			}
756 			prevres = res;
757 			res->start = start;
758 			res->end = end;
759 			res->flags = IORESOURCE_MEM;
760 			res->name = kmalloc(64, GFP_KERNEL);
761 			if(res->name)
762 				snprintf((char *)res->name, 64, "%s LMMIO %d",
763 					 name, count);
764 			res++;
765 			count++;
766 		}
767 	}
768 
769 	res = &dino_dev->hba.lmmio_space;
770 
771 	for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
772 		if(res[i].flags == 0)
773 			break;
774 
775 		result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
776 		if (result < 0) {
777 			printk(KERN_ERR "%s: failed to claim PCI Bus address "
778 			       "space %d (%pR)!\n", name, i, &res[i]);
779 			return result;
780 		}
781 	}
782 	return 0;
783 }
784 
785 static int __init dino_common_init(struct parisc_device *dev,
786 		struct dino_device *dino_dev, const char *name)
787 {
788 	int status;
789 	u32 eim;
790 	struct gsc_irq gsc_irq;
791 	struct resource *res;
792 
793 	pcibios_register_hba(&dino_dev->hba);
794 
795 	pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
796 	pci_port = &dino_port_ops;
797 
798 	/*
799 	** Note: SMP systems can make use of IRR1/IAR1 registers
800 	**   But it won't buy much performance except in very
801 	**   specific applications/configurations. Note Dino
802 	**   still only has 11 IRQ input lines - just map some of them
803 	**   to a different processor.
804 	*/
805 	dev->irq = gsc_alloc_irq(&gsc_irq);
806 	dino_dev->txn_addr = gsc_irq.txn_addr;
807 	dino_dev->txn_data = gsc_irq.txn_data;
808 	eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
809 
810 	/*
811 	** Dino needs a PA "IRQ" to get a processor's attention.
812 	** arch/parisc/kernel/irq.c returns an EIRR bit.
813 	*/
814 	if (dev->irq < 0) {
815 		printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
816 		return 1;
817 	}
818 
819 	status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
820 	if (status) {
821 		printk(KERN_WARNING "%s: request_irq() failed with %d\n",
822 			name, status);
823 		return 1;
824 	}
825 
826 	/* Support the serial port which is sometimes attached on built-in
827 	 * Dino / Cujo chips.
828 	 */
829 
830 	gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
831 
832 	/*
833 	** This enables DINO to generate interrupts when it sees
834 	** any of its inputs *change*. Just asserting an IRQ
835 	** before it's enabled (ie unmasked) isn't good enough.
836 	*/
837 	__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
838 
839 	/*
840 	** Some platforms don't clear Dino's IRR0 register at boot time.
841 	** Reading will clear it now.
842 	*/
843 	__raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
844 
845 	/* allocate I/O Port resource region */
846 	res = &dino_dev->hba.io_space;
847 	if (!is_cujo(&dev->id)) {
848 		res->name = "Dino I/O Port";
849 	} else {
850 		res->name = "Cujo I/O Port";
851 	}
852 	res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
853 	res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
854 	res->flags = IORESOURCE_IO; /* do not mark it busy ! */
855 	if (request_resource(&ioport_resource, res) < 0) {
856 		printk(KERN_ERR "%s: request I/O Port region failed "
857 		       "0x%lx/%lx (hpa 0x%p)\n",
858 		       name, (unsigned long)res->start, (unsigned long)res->end,
859 		       dino_dev->hba.base_addr);
860 		return 1;
861 	}
862 
863 	return 0;
864 }
865 
866 #define CUJO_RAVEN_ADDR		F_EXTEND(0xf1000000UL)
867 #define CUJO_FIREHAWK_ADDR	F_EXTEND(0xf1604000UL)
868 #define CUJO_RAVEN_BADPAGE	0x01003000UL
869 #define CUJO_FIREHAWK_BADPAGE	0x01607000UL
870 
871 static const char *dino_vers[] = {
872 	"2.0",
873 	"2.1",
874 	"3.0",
875 	"3.1"
876 };
877 
878 static const char *cujo_vers[] = {
879 	"1.0",
880 	"2.0"
881 };
882 
883 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
884 
885 /*
886 ** Determine if dino should claim this chip (return 0) or not (return 1).
887 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
888 ** Much of the initialization is common though.
889 */
890 static int __init dino_probe(struct parisc_device *dev)
891 {
892 	struct dino_device *dino_dev;	// Dino specific control struct
893 	const char *version = "unknown";
894 	char *name;
895 	int is_cujo = 0;
896 	LIST_HEAD(resources);
897 	struct pci_bus *bus;
898 	unsigned long hpa = dev->hpa.start;
899 	int max;
900 
901 	name = "Dino";
902 	if (is_card_dino(&dev->id)) {
903 		version = "3.x (card mode)";
904 	} else {
905 		if (!is_cujo(&dev->id)) {
906 			if (dev->id.hversion_rev < 4) {
907 				version = dino_vers[dev->id.hversion_rev];
908 			}
909 		} else {
910 			name = "Cujo";
911 			is_cujo = 1;
912 			if (dev->id.hversion_rev < 2) {
913 				version = cujo_vers[dev->id.hversion_rev];
914 			}
915 		}
916 	}
917 
918 	printk("%s version %s found at 0x%lx\n", name, version, hpa);
919 
920 	if (!request_mem_region(hpa, PAGE_SIZE, name)) {
921 		printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
922 			hpa);
923 		return 1;
924 	}
925 
926 	/* Check for bugs */
927 	if (is_cujo && dev->id.hversion_rev == 1) {
928 #ifdef CONFIG_IOMMU_CCIO
929 		printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
930 		if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
931 			ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
932 		} else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
933 			ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
934 		} else {
935 			printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
936 		}
937 #endif
938 	} else if (!is_cujo && !is_card_dino(&dev->id) &&
939 			dev->id.hversion_rev < 3) {
940 		printk(KERN_WARNING
941 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
942 "data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
943 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
944 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
945 			dev->id.hversion_rev);
946 /* REVISIT: why are C200/C240 listed in the README table but not
947 **   "Models affected"? Could be an omission in the original literature.
948 */
949 	}
950 
951 	dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
952 	if (!dino_dev) {
953 		printk("dino_init_chip - couldn't alloc dino_device\n");
954 		return 1;
955 	}
956 
957 	dino_dev->hba.dev = dev;
958 	dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
959 	dino_dev->hba.lmmio_space_offset = 0;	/* CPU addrs == bus addrs */
960 	spin_lock_init(&dino_dev->dinosaur_pen);
961 	dino_dev->hba.iommu = ccio_get_iommu(dev);
962 
963 	if (is_card_dino(&dev->id)) {
964 		dino_card_init(dino_dev);
965 	} else {
966 		dino_bridge_init(dino_dev, name);
967 	}
968 
969 	if (dino_common_init(dev, dino_dev, name))
970 		return 1;
971 
972 	dev->dev.platform_data = dino_dev;
973 
974 	pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
975 				HBA_PORT_BASE(dino_dev->hba.hba_num));
976 	if (dino_dev->hba.lmmio_space.flags)
977 		pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
978 					dino_dev->hba.lmmio_space_offset);
979 	if (dino_dev->hba.elmmio_space.flags)
980 		pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
981 					dino_dev->hba.lmmio_space_offset);
982 	if (dino_dev->hba.gmmio_space.flags)
983 		pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
984 
985 	dino_dev->hba.bus_num.start = dino_current_bus;
986 	dino_dev->hba.bus_num.end = 255;
987 	dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
988 	pci_add_resource(&resources, &dino_dev->hba.bus_num);
989 	/*
990 	** It's not used to avoid chicken/egg problems
991 	** with configuration accessor functions.
992 	*/
993 	dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
994 			 dino_current_bus, &dino_cfg_ops, NULL, &resources);
995 	if (!bus) {
996 		printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
997 		       dev_name(&dev->dev), dino_current_bus);
998 		pci_free_resource_list(&resources);
999 		/* increment the bus number in case of duplicates */
1000 		dino_current_bus++;
1001 		return 0;
1002 	}
1003 
1004 	max = pci_scan_child_bus(bus);
1005 	pci_bus_update_busn_res_end(bus, max);
1006 
1007 	/* This code *depends* on scanning being single threaded
1008 	 * if it isn't, this global bus number count will fail
1009 	 */
1010 	dino_current_bus = max + 1;
1011 	pci_bus_assign_resources(bus);
1012 	pci_bus_add_devices(bus);
1013 	return 0;
1014 }
1015 
1016 /*
1017  * Normally, we would just test sversion.  But the Elroy PCI adapter has
1018  * the same sversion as Dino, so we have to check hversion as well.
1019  * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1020  * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1021  * For card-mode Dino, most machines report an sversion of 9D.  But 715
1022  * and 725 firmware misreport it as 0x08080 for no adequately explained
1023  * reason.
1024  */
1025 static struct parisc_device_id dino_tbl[] = {
1026 	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1027 	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1028 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1029 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1030 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1031 	{ 0, }
1032 };
1033 
1034 static struct parisc_driver dino_driver = {
1035 	.name =		"dino",
1036 	.id_table =	dino_tbl,
1037 	.probe =	dino_probe,
1038 };
1039 
1040 /*
1041  * One time initialization to let the world know Dino is here.
1042  * This is the only routine which is NOT static.
1043  * Must be called exactly once before pci_init().
1044  */
1045 int __init dino_init(void)
1046 {
1047 	register_parisc_driver(&dino_driver);
1048 	return 0;
1049 }
1050 
1051