1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * STM32 Factory-programmed memory read access driver 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/arm-smccc.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/nvmem-provider.h> 13 #include <linux/of_device.h> 14 15 /* BSEC secure service access from non-secure */ 16 #define STM32_SMC_BSEC 0x82001003 17 #define STM32_SMC_READ_SHADOW 0x01 18 #define STM32_SMC_PROG_OTP 0x02 19 #define STM32_SMC_WRITE_SHADOW 0x03 20 #define STM32_SMC_READ_OTP 0x04 21 22 /* shadow registers offset */ 23 #define STM32MP15_BSEC_DATA0 0x200 24 25 struct stm32_romem_cfg { 26 int size; 27 u8 lower; 28 }; 29 30 struct stm32_romem_priv { 31 void __iomem *base; 32 struct nvmem_config cfg; 33 u8 lower; 34 }; 35 36 static int stm32_romem_read(void *context, unsigned int offset, void *buf, 37 size_t bytes) 38 { 39 struct stm32_romem_priv *priv = context; 40 u8 *buf8 = buf; 41 int i; 42 43 for (i = offset; i < offset + bytes; i++) 44 *buf8++ = readb_relaxed(priv->base + i); 45 46 return 0; 47 } 48 49 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) 50 { 51 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) 52 struct arm_smccc_res res; 53 54 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); 55 if (res.a0) 56 return -EIO; 57 58 if (result) 59 *result = (u32)res.a1; 60 61 return 0; 62 #else 63 return -ENXIO; 64 #endif 65 } 66 67 static int stm32_bsec_read(void *context, unsigned int offset, void *buf, 68 size_t bytes) 69 { 70 struct stm32_romem_priv *priv = context; 71 struct device *dev = priv->cfg.dev; 72 u32 roffset, rbytes, val; 73 u8 *buf8 = buf, *val8 = (u8 *)&val; 74 int i, j = 0, ret, skip_bytes, size; 75 76 /* Round unaligned access to 32-bits */ 77 roffset = rounddown(offset, 4); 78 skip_bytes = offset & 0x3; 79 rbytes = roundup(bytes + skip_bytes, 4); 80 81 if (roffset + rbytes > priv->cfg.size) 82 return -EINVAL; 83 84 for (i = roffset; (i < roffset + rbytes); i += 4) { 85 u32 otp = i >> 2; 86 87 if (otp < priv->lower) { 88 /* read lower data from shadow registers */ 89 val = readl_relaxed( 90 priv->base + STM32MP15_BSEC_DATA0 + i); 91 } else { 92 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0, 93 &val); 94 if (ret) { 95 dev_err(dev, "Can't read data%d (%d)\n", otp, 96 ret); 97 return ret; 98 } 99 } 100 /* skip first bytes in case of unaligned read */ 101 if (skip_bytes) 102 size = min(bytes, (size_t)(4 - skip_bytes)); 103 else 104 size = min(bytes, (size_t)4); 105 memcpy(&buf8[j], &val8[skip_bytes], size); 106 bytes -= size; 107 j += size; 108 skip_bytes = 0; 109 } 110 111 return 0; 112 } 113 114 static int stm32_bsec_write(void *context, unsigned int offset, void *buf, 115 size_t bytes) 116 { 117 struct stm32_romem_priv *priv = context; 118 struct device *dev = priv->cfg.dev; 119 u32 *buf32 = buf; 120 int ret, i; 121 122 /* Allow only writing complete 32-bits aligned words */ 123 if ((bytes % 4) || (offset % 4)) 124 return -EINVAL; 125 126 for (i = offset; i < offset + bytes; i += 4) { 127 ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++, 128 NULL); 129 if (ret) { 130 dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret); 131 return ret; 132 } 133 } 134 135 if (offset + bytes >= priv->lower * 4) 136 dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n"); 137 138 return 0; 139 } 140 141 static int stm32_romem_probe(struct platform_device *pdev) 142 { 143 const struct stm32_romem_cfg *cfg; 144 struct device *dev = &pdev->dev; 145 struct stm32_romem_priv *priv; 146 struct resource *res; 147 148 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 149 if (!priv) 150 return -ENOMEM; 151 152 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 153 priv->base = devm_ioremap_resource(dev, res); 154 if (IS_ERR(priv->base)) 155 return PTR_ERR(priv->base); 156 157 priv->cfg.name = "stm32-romem"; 158 priv->cfg.word_size = 1; 159 priv->cfg.stride = 1; 160 priv->cfg.dev = dev; 161 priv->cfg.priv = priv; 162 priv->cfg.owner = THIS_MODULE; 163 priv->cfg.type = NVMEM_TYPE_OTP; 164 165 priv->lower = 0; 166 167 cfg = (const struct stm32_romem_cfg *) 168 of_match_device(dev->driver->of_match_table, dev)->data; 169 if (!cfg) { 170 priv->cfg.read_only = true; 171 priv->cfg.size = resource_size(res); 172 priv->cfg.reg_read = stm32_romem_read; 173 } else { 174 priv->cfg.size = cfg->size; 175 priv->lower = cfg->lower; 176 priv->cfg.reg_read = stm32_bsec_read; 177 priv->cfg.reg_write = stm32_bsec_write; 178 } 179 180 return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg)); 181 } 182 183 /* 184 * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) 185 * => 96 x 32-bits data words 186 * - Lower: 1K bits, 2:1 redundancy, incremental bit programming 187 * => 32 (x 32-bits) lower shadow registers = words 0 to 31 188 * - Upper: 2K bits, ECC protection, word programming only 189 * => 64 (x 32-bits) = words 32 to 95 190 */ 191 static const struct stm32_romem_cfg stm32mp15_bsec_cfg = { 192 .size = 384, 193 .lower = 32, 194 }; 195 196 static const struct of_device_id stm32_romem_of_match[] = { 197 { .compatible = "st,stm32f4-otp", }, { 198 .compatible = "st,stm32mp15-bsec", 199 .data = (void *)&stm32mp15_bsec_cfg, 200 }, { 201 }, 202 }; 203 MODULE_DEVICE_TABLE(of, stm32_romem_of_match); 204 205 static struct platform_driver stm32_romem_driver = { 206 .probe = stm32_romem_probe, 207 .driver = { 208 .name = "stm32-romem", 209 .of_match_table = of_match_ptr(stm32_romem_of_match), 210 }, 211 }; 212 module_platform_driver(stm32_romem_driver); 213 214 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 215 MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM"); 216 MODULE_ALIAS("platform:nvmem-stm32-romem"); 217 MODULE_LICENSE("GPL v2"); 218