1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/device.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/nvmem-provider.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 19 /* Blow timer clock frequency in Mhz */ 20 #define QFPROM_BLOW_TIMER_OFFSET 0x03c 21 22 /* Amount of time required to hold charge to blow fuse in micro-seconds */ 23 #define QFPROM_FUSE_BLOW_POLL_US 100 24 #define QFPROM_FUSE_BLOW_TIMEOUT_US 10000 25 26 #define QFPROM_BLOW_STATUS_OFFSET 0x048 27 #define QFPROM_BLOW_STATUS_BUSY 0x1 28 #define QFPROM_BLOW_STATUS_READY 0x0 29 30 #define QFPROM_ACCEL_OFFSET 0x044 31 32 #define QFPROM_VERSION_OFFSET 0x0 33 #define QFPROM_MAJOR_VERSION_SHIFT 28 34 #define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT) 35 #define QFPROM_MINOR_VERSION_SHIFT 16 36 #define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT) 37 38 static bool read_raw_data; 39 module_param(read_raw_data, bool, 0644); 40 MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data"); 41 42 /** 43 * struct qfprom_soc_data - config that varies from SoC to SoC. 44 * 45 * @accel_value: Should contain qfprom accel value. 46 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow. 47 * @qfprom_blow_set_freq: The frequency required to set when we start the 48 * fuse blowing. 49 * @qfprom_blow_uV: LDO voltage to be set when doing efuse blow 50 */ 51 struct qfprom_soc_data { 52 u32 accel_value; 53 u32 qfprom_blow_timer_value; 54 u32 qfprom_blow_set_freq; 55 int qfprom_blow_uV; 56 }; 57 58 /** 59 * struct qfprom_priv - structure holding qfprom attributes 60 * 61 * @qfpraw: iomapped memory space for qfprom-efuse raw address space. 62 * @qfpconf: iomapped memory space for qfprom-efuse configuration address 63 * space. 64 * @qfpcorrected: iomapped memory space for qfprom corrected address space. 65 * @qfpsecurity: iomapped memory space for qfprom security control space. 66 * @dev: qfprom device structure. 67 * @secclk: Clock supply. 68 * @vcc: Regulator supply. 69 * @soc_data: Data that for things that varies from SoC to SoC. 70 */ 71 struct qfprom_priv { 72 void __iomem *qfpraw; 73 void __iomem *qfpconf; 74 void __iomem *qfpcorrected; 75 void __iomem *qfpsecurity; 76 struct device *dev; 77 struct clk *secclk; 78 struct regulator *vcc; 79 const struct qfprom_soc_data *soc_data; 80 }; 81 82 /** 83 * struct qfprom_touched_values - saved values to restore after blowing 84 * 85 * @clk_rate: The rate the clock was at before blowing. 86 * @accel_val: The value of the accel reg before blowing. 87 * @timer_val: The value of the timer before blowing. 88 */ 89 struct qfprom_touched_values { 90 unsigned long clk_rate; 91 u32 accel_val; 92 u32 timer_val; 93 }; 94 95 /** 96 * struct qfprom_soc_compatible_data - Data matched against the SoC 97 * compatible string. 98 * 99 * @keepout: Array of keepout regions for this SoC. 100 * @nkeepout: Number of elements in the keepout array. 101 */ 102 struct qfprom_soc_compatible_data { 103 const struct nvmem_keepout *keepout; 104 unsigned int nkeepout; 105 }; 106 107 static const struct nvmem_keepout sc7180_qfprom_keepout[] = { 108 {.start = 0x128, .end = 0x148}, 109 {.start = 0x220, .end = 0x228} 110 }; 111 112 static const struct qfprom_soc_compatible_data sc7180_qfprom = { 113 .keepout = sc7180_qfprom_keepout, 114 .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout) 115 }; 116 117 static const struct nvmem_keepout sc7280_qfprom_keepout[] = { 118 {.start = 0x128, .end = 0x148}, 119 {.start = 0x238, .end = 0x248} 120 }; 121 122 static const struct qfprom_soc_compatible_data sc7280_qfprom = { 123 .keepout = sc7280_qfprom_keepout, 124 .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout) 125 }; 126 127 /** 128 * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing. 129 * @priv: Our driver data. 130 * @old: The data that was stashed from before fuse blowing. 131 * 132 * Resets the value of the blow timer, accel register and the clock 133 * and voltage settings. 134 * 135 * Prints messages if there are errors but doesn't return an error code 136 * since there's not much we can do upon failure. 137 */ 138 static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv, 139 const struct qfprom_touched_values *old) 140 { 141 int ret; 142 143 writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 144 writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET); 145 146 dev_pm_genpd_set_performance_state(priv->dev, 0); 147 pm_runtime_put(priv->dev); 148 149 /* 150 * This may be a shared rail and may be able to run at a lower rate 151 * when we're not blowing fuses. At the moment, the regulator framework 152 * applies voltage constraints even on disabled rails, so remove our 153 * constraints and allow the rail to be adjusted by other users. 154 */ 155 ret = regulator_set_voltage(priv->vcc, 0, INT_MAX); 156 if (ret) 157 dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n"); 158 159 ret = regulator_disable(priv->vcc); 160 if (ret) 161 dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n"); 162 163 ret = clk_set_rate(priv->secclk, old->clk_rate); 164 if (ret) 165 dev_warn(priv->dev, 166 "Failed to set clock rate for disable (ignoring)\n"); 167 168 clk_disable_unprepare(priv->secclk); 169 } 170 171 /** 172 * qfprom_enable_fuse_blowing() - Enable fuse blowing. 173 * @priv: Our driver data. 174 * @old: We'll stash stuff here to use when disabling. 175 * 176 * Sets the value of the blow timer, accel register and the clock 177 * and voltage settings. 178 * 179 * Prints messages if there are errors so caller doesn't need to. 180 * 181 * Return: 0 or -err. 182 */ 183 static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv, 184 struct qfprom_touched_values *old) 185 { 186 int ret; 187 int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV; 188 189 ret = clk_prepare_enable(priv->secclk); 190 if (ret) { 191 dev_err(priv->dev, "Failed to enable clock\n"); 192 return ret; 193 } 194 195 old->clk_rate = clk_get_rate(priv->secclk); 196 ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq); 197 if (ret) { 198 dev_err(priv->dev, "Failed to set clock rate for enable\n"); 199 goto err_clk_prepared; 200 } 201 202 /* 203 * Hardware requires a minimum voltage for fuse blowing. 204 * This may be a shared rail so don't specify a maximum. 205 * Regulator constraints will cap to the actual maximum. 206 */ 207 ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX); 208 if (ret) { 209 dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV); 210 goto err_clk_rate_set; 211 } 212 213 ret = regulator_enable(priv->vcc); 214 if (ret) { 215 dev_err(priv->dev, "Failed to enable regulator\n"); 216 goto err_clk_rate_set; 217 } 218 219 ret = pm_runtime_resume_and_get(priv->dev); 220 if (ret < 0) { 221 dev_err(priv->dev, "Failed to enable power-domain\n"); 222 goto err_reg_enable; 223 } 224 dev_pm_genpd_set_performance_state(priv->dev, INT_MAX); 225 226 old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 227 old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET); 228 writel(priv->soc_data->qfprom_blow_timer_value, 229 priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 230 writel(priv->soc_data->accel_value, 231 priv->qfpconf + QFPROM_ACCEL_OFFSET); 232 233 return 0; 234 235 err_reg_enable: 236 regulator_disable(priv->vcc); 237 err_clk_rate_set: 238 clk_set_rate(priv->secclk, old->clk_rate); 239 err_clk_prepared: 240 clk_disable_unprepare(priv->secclk); 241 return ret; 242 } 243 244 /** 245 * qfprom_reg_write() - Write to fuses. 246 * @context: Our driver data. 247 * @reg: The offset to write at. 248 * @_val: Pointer to data to write. 249 * @bytes: The number of bytes to write. 250 * 251 * Writes to fuses. WARNING: THIS IS PERMANENT. 252 * 253 * Return: 0 or -err. 254 */ 255 static int qfprom_reg_write(void *context, unsigned int reg, void *_val, 256 size_t bytes) 257 { 258 struct qfprom_priv *priv = context; 259 struct qfprom_touched_values old; 260 int words = bytes / 4; 261 u32 *value = _val; 262 u32 blow_status; 263 int ret; 264 int i; 265 266 dev_dbg(priv->dev, 267 "Writing to raw qfprom region : %#010x of size: %zu\n", 268 reg, bytes); 269 270 /* 271 * The hardware only allows us to write word at a time, but we can 272 * read byte at a time. Until the nvmem framework allows a separate 273 * word_size and stride for reading vs. writing, we'll enforce here. 274 */ 275 if (bytes % 4) { 276 dev_err(priv->dev, 277 "%zu is not an integral number of words\n", bytes); 278 return -EINVAL; 279 } 280 if (reg % 4) { 281 dev_err(priv->dev, 282 "Invalid offset: %#x. Must be word aligned\n", reg); 283 return -EINVAL; 284 } 285 286 ret = qfprom_enable_fuse_blowing(priv, &old); 287 if (ret) 288 return ret; 289 290 ret = readl_relaxed_poll_timeout( 291 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET, 292 blow_status, blow_status == QFPROM_BLOW_STATUS_READY, 293 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US); 294 295 if (ret) { 296 dev_err(priv->dev, 297 "Timeout waiting for initial ready; aborting.\n"); 298 goto exit_enabled_fuse_blowing; 299 } 300 301 for (i = 0; i < words; i++) 302 writel(value[i], priv->qfpraw + reg + (i * 4)); 303 304 ret = readl_relaxed_poll_timeout( 305 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET, 306 blow_status, blow_status == QFPROM_BLOW_STATUS_READY, 307 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US); 308 309 /* Give an error, but not much we can do in this case */ 310 if (ret) 311 dev_err(priv->dev, "Timeout waiting for finish.\n"); 312 313 exit_enabled_fuse_blowing: 314 qfprom_disable_fuse_blowing(priv, &old); 315 316 return ret; 317 } 318 319 static int qfprom_reg_read(void *context, 320 unsigned int reg, void *_val, size_t bytes) 321 { 322 struct qfprom_priv *priv = context; 323 u32 *val = _val; 324 void __iomem *base = priv->qfpcorrected; 325 int words = DIV_ROUND_UP(bytes, sizeof(u32)); 326 int i; 327 328 if (read_raw_data && priv->qfpraw) 329 base = priv->qfpraw; 330 331 for (i = 0; i < words; i++) 332 *val++ = readl(base + reg + i * sizeof(u32)); 333 334 return 0; 335 } 336 337 /* Align reads to word boundary */ 338 static void qfprom_fixup_dt_cell_info(struct nvmem_device *nvmem, 339 struct nvmem_cell_info *cell) 340 { 341 unsigned int byte_offset = cell->offset % sizeof(u32); 342 343 cell->bit_offset += byte_offset * BITS_PER_BYTE; 344 cell->offset -= byte_offset; 345 if (byte_offset && !cell->nbits) 346 cell->nbits = cell->bytes * BITS_PER_BYTE; 347 } 348 349 static void qfprom_runtime_disable(void *data) 350 { 351 pm_runtime_disable(data); 352 } 353 354 static const struct qfprom_soc_data qfprom_7_8_data = { 355 .accel_value = 0xD10, 356 .qfprom_blow_timer_value = 25, 357 .qfprom_blow_set_freq = 4800000, 358 .qfprom_blow_uV = 1800000, 359 }; 360 361 static const struct qfprom_soc_data qfprom_7_15_data = { 362 .accel_value = 0xD08, 363 .qfprom_blow_timer_value = 24, 364 .qfprom_blow_set_freq = 4800000, 365 .qfprom_blow_uV = 1900000, 366 }; 367 368 static int qfprom_probe(struct platform_device *pdev) 369 { 370 struct nvmem_config econfig = { 371 .name = "qfprom", 372 .add_legacy_fixed_of_cells = true, 373 .stride = 4, 374 .word_size = 4, 375 .id = NVMEM_DEVID_AUTO, 376 .reg_read = qfprom_reg_read, 377 .fixup_dt_cell_info = qfprom_fixup_dt_cell_info, 378 }; 379 struct device *dev = &pdev->dev; 380 struct resource *res; 381 struct nvmem_device *nvmem; 382 const struct qfprom_soc_compatible_data *soc_data; 383 struct qfprom_priv *priv; 384 int ret; 385 386 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 387 if (!priv) 388 return -ENOMEM; 389 390 /* The corrected section is always provided */ 391 priv->qfpcorrected = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 392 if (IS_ERR(priv->qfpcorrected)) 393 return PTR_ERR(priv->qfpcorrected); 394 395 econfig.size = resource_size(res); 396 econfig.dev = dev; 397 econfig.priv = priv; 398 399 priv->dev = dev; 400 soc_data = device_get_match_data(dev); 401 if (soc_data) { 402 econfig.keepout = soc_data->keepout; 403 econfig.nkeepout = soc_data->nkeepout; 404 } 405 406 /* 407 * If more than one region is provided then the OS has the ability 408 * to write. 409 */ 410 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 411 if (res) { 412 u32 version; 413 int major_version, minor_version; 414 415 priv->qfpraw = devm_ioremap_resource(dev, res); 416 if (IS_ERR(priv->qfpraw)) 417 return PTR_ERR(priv->qfpraw); 418 priv->qfpconf = devm_platform_ioremap_resource(pdev, 2); 419 if (IS_ERR(priv->qfpconf)) 420 return PTR_ERR(priv->qfpconf); 421 priv->qfpsecurity = devm_platform_ioremap_resource(pdev, 3); 422 if (IS_ERR(priv->qfpsecurity)) 423 return PTR_ERR(priv->qfpsecurity); 424 425 version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET); 426 major_version = (version & QFPROM_MAJOR_VERSION_MASK) >> 427 QFPROM_MAJOR_VERSION_SHIFT; 428 minor_version = (version & QFPROM_MINOR_VERSION_MASK) >> 429 QFPROM_MINOR_VERSION_SHIFT; 430 431 if (major_version == 7 && minor_version == 8) 432 priv->soc_data = &qfprom_7_8_data; 433 else if (major_version == 7 && minor_version == 15) 434 priv->soc_data = &qfprom_7_15_data; 435 436 priv->vcc = devm_regulator_get(&pdev->dev, "vcc"); 437 if (IS_ERR(priv->vcc)) 438 return PTR_ERR(priv->vcc); 439 440 priv->secclk = devm_clk_get_optional(dev, "core"); 441 if (IS_ERR(priv->secclk)) 442 return dev_err_probe(dev, PTR_ERR(priv->secclk), "Error getting clock\n"); 443 444 /* Only enable writing if we have SoC data and a valid clock */ 445 if (priv->soc_data && priv->secclk) 446 econfig.reg_write = qfprom_reg_write; 447 } 448 449 pm_runtime_enable(dev); 450 ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev); 451 if (ret) 452 return ret; 453 454 nvmem = devm_nvmem_register(dev, &econfig); 455 456 return PTR_ERR_OR_ZERO(nvmem); 457 } 458 459 static const struct of_device_id qfprom_of_match[] = { 460 { .compatible = "qcom,qfprom",}, 461 { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom}, 462 { .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom}, 463 {/* sentinel */}, 464 }; 465 MODULE_DEVICE_TABLE(of, qfprom_of_match); 466 467 static struct platform_driver qfprom_driver = { 468 .probe = qfprom_probe, 469 .driver = { 470 .name = "qcom,qfprom", 471 .of_match_table = qfprom_of_match, 472 }, 473 }; 474 module_platform_driver(qfprom_driver); 475 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 476 MODULE_DESCRIPTION("Qualcomm QFPROM driver"); 477 MODULE_LICENSE("GPL v2"); 478