1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com> 5 */ 6 7 #include <linux/device.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/io.h> 11 #include <linux/nvmem-provider.h> 12 #include <linux/platform_device.h> 13 #include <linux/property.h> 14 15 struct mtk_efuse_pdata { 16 bool uses_post_processing; 17 }; 18 19 struct mtk_efuse_priv { 20 void __iomem *base; 21 }; 22 23 static int mtk_reg_read(void *context, 24 unsigned int reg, void *_val, size_t bytes) 25 { 26 struct mtk_efuse_priv *priv = context; 27 void __iomem *addr = priv->base + reg; 28 u8 *val = _val; 29 int i; 30 31 for (i = 0; i < bytes; i++, val++) 32 *val = readb(addr + i); 33 34 return 0; 35 } 36 37 static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index, 38 unsigned int offset, void *data, size_t bytes) 39 { 40 u8 *val = data; 41 42 if (val[0] < 8) 43 val[0] = BIT(val[0]); 44 45 return 0; 46 } 47 48 static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem, 49 struct nvmem_layout *layout, 50 struct nvmem_cell_info *cell) 51 { 52 size_t sz = strlen(cell->name); 53 54 /* 55 * On some SoCs, the GPU speedbin is not read as bitmask but as 56 * a number with range [0-7] (max 3 bits): post process to use 57 * it in OPP tables to describe supported-hw. 58 */ 59 if (cell->nbits <= 3 && 60 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) 61 cell->read_post_process = mtk_efuse_gpu_speedbin_pp; 62 } 63 64 static struct nvmem_layout mtk_efuse_layout = { 65 .fixup_cell_info = mtk_efuse_fixup_cell_info, 66 }; 67 68 static int mtk_efuse_probe(struct platform_device *pdev) 69 { 70 struct device *dev = &pdev->dev; 71 struct resource *res; 72 struct nvmem_device *nvmem; 73 struct nvmem_config econfig = {}; 74 struct mtk_efuse_priv *priv; 75 const struct mtk_efuse_pdata *pdata; 76 77 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 78 if (!priv) 79 return -ENOMEM; 80 81 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 82 if (IS_ERR(priv->base)) 83 return PTR_ERR(priv->base); 84 85 pdata = device_get_match_data(dev); 86 econfig.stride = 1; 87 econfig.word_size = 1; 88 econfig.reg_read = mtk_reg_read; 89 econfig.size = resource_size(res); 90 econfig.priv = priv; 91 econfig.dev = dev; 92 if (pdata->uses_post_processing) 93 econfig.layout = &mtk_efuse_layout; 94 nvmem = devm_nvmem_register(dev, &econfig); 95 96 return PTR_ERR_OR_ZERO(nvmem); 97 } 98 99 static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = { 100 .uses_post_processing = true, 101 }; 102 103 static const struct mtk_efuse_pdata mtk_efuse_pdata = { 104 .uses_post_processing = false, 105 }; 106 107 static const struct of_device_id mtk_efuse_of_match[] = { 108 { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata }, 109 { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata }, 110 { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata }, 111 {/* sentinel */}, 112 }; 113 MODULE_DEVICE_TABLE(of, mtk_efuse_of_match); 114 115 static struct platform_driver mtk_efuse_driver = { 116 .probe = mtk_efuse_probe, 117 .driver = { 118 .name = "mediatek,efuse", 119 .of_match_table = mtk_efuse_of_match, 120 }, 121 }; 122 123 static int __init mtk_efuse_init(void) 124 { 125 int ret; 126 127 ret = platform_driver_register(&mtk_efuse_driver); 128 if (ret) { 129 pr_err("Failed to register efuse driver\n"); 130 return ret; 131 } 132 133 return 0; 134 } 135 136 static void __exit mtk_efuse_exit(void) 137 { 138 return platform_driver_unregister(&mtk_efuse_driver); 139 } 140 141 subsys_initcall(mtk_efuse_init); 142 module_exit(mtk_efuse_exit); 143 144 MODULE_AUTHOR("Andrew-CT Chen <andrew-ct.chen@mediatek.com>"); 145 MODULE_DESCRIPTION("Mediatek EFUSE driver"); 146 MODULE_LICENSE("GPL v2"); 147