1 /* 2 * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver 3 * 4 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/nvmem-provider.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 21 /* Registers */ 22 #define LPC18XX_EEPROM_AUTOPROG 0x00c 23 #define LPC18XX_EEPROM_AUTOPROG_WORD 0x1 24 25 #define LPC18XX_EEPROM_CLKDIV 0x014 26 27 #define LPC18XX_EEPROM_PWRDWN 0x018 28 #define LPC18XX_EEPROM_PWRDWN_NO 0x0 29 #define LPC18XX_EEPROM_PWRDWN_YES 0x1 30 31 #define LPC18XX_EEPROM_INTSTAT 0xfe0 32 #define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2) 33 34 #define LPC18XX_EEPROM_INTSTATCLR 0xfe8 35 #define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2) 36 37 /* Fixed page size (bytes) */ 38 #define LPC18XX_EEPROM_PAGE_SIZE 0x80 39 40 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */ 41 #define LPC18XX_EEPROM_CLOCK_HZ 1500000 42 43 /* EEPROM requires 3 ms of erase/program time between each writing */ 44 #define LPC18XX_EEPROM_PROGRAM_TIME 3 45 46 struct lpc18xx_eeprom_dev { 47 struct clk *clk; 48 void __iomem *reg_base; 49 void __iomem *mem_base; 50 struct nvmem_device *nvmem; 51 unsigned reg_bytes; 52 unsigned val_bytes; 53 int size; 54 }; 55 56 static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom, 57 u32 reg, u32 val) 58 { 59 writel(val, eeprom->reg_base + reg); 60 } 61 62 static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom, 63 u32 reg) 64 { 65 return readl(eeprom->reg_base + reg); 66 } 67 68 static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom) 69 { 70 unsigned long end; 71 u32 val; 72 73 /* Wait until EEPROM program operation has finished */ 74 end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10); 75 76 while (time_is_after_jiffies(end)) { 77 val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT); 78 79 if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) { 80 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR, 81 LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST); 82 return 0; 83 } 84 85 usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC, 86 (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC); 87 } 88 89 return -ETIMEDOUT; 90 } 91 92 static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg, 93 void *val, size_t bytes) 94 { 95 struct lpc18xx_eeprom_dev *eeprom = context; 96 unsigned int offset = reg; 97 int ret; 98 99 /* 100 * The last page contains the EEPROM initialization data and is not 101 * writable. 102 */ 103 if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) || 104 (reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE)) 105 return -EINVAL; 106 107 108 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 109 LPC18XX_EEPROM_PWRDWN_NO); 110 111 /* Wait 100 us while the EEPROM wakes up */ 112 usleep_range(100, 200); 113 114 while (bytes) { 115 writel(*(u32 *)val, eeprom->mem_base + offset); 116 ret = lpc18xx_eeprom_busywait_until_prog(eeprom); 117 if (ret < 0) 118 return ret; 119 120 bytes -= eeprom->val_bytes; 121 val += eeprom->val_bytes; 122 offset += eeprom->val_bytes; 123 } 124 125 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 126 LPC18XX_EEPROM_PWRDWN_YES); 127 128 return 0; 129 } 130 131 static int lpc18xx_eeprom_read(void *context, unsigned int offset, 132 void *val, size_t bytes) 133 { 134 struct lpc18xx_eeprom_dev *eeprom = context; 135 136 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 137 LPC18XX_EEPROM_PWRDWN_NO); 138 139 /* Wait 100 us while the EEPROM wakes up */ 140 usleep_range(100, 200); 141 142 while (bytes) { 143 *(u32 *)val = readl(eeprom->mem_base + offset); 144 bytes -= eeprom->val_bytes; 145 val += eeprom->val_bytes; 146 offset += eeprom->val_bytes; 147 } 148 149 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 150 LPC18XX_EEPROM_PWRDWN_YES); 151 152 return 0; 153 } 154 155 156 static struct nvmem_config lpc18xx_nvmem_config = { 157 .name = "lpc18xx-eeprom", 158 .stride = 4, 159 .word_size = 4, 160 .reg_read = lpc18xx_eeprom_read, 161 .reg_write = lpc18xx_eeprom_gather_write, 162 }; 163 164 static int lpc18xx_eeprom_probe(struct platform_device *pdev) 165 { 166 struct lpc18xx_eeprom_dev *eeprom; 167 struct device *dev = &pdev->dev; 168 struct reset_control *rst; 169 unsigned long clk_rate; 170 struct resource *res; 171 int ret; 172 173 eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL); 174 if (!eeprom) 175 return -ENOMEM; 176 177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); 178 eeprom->reg_base = devm_ioremap_resource(dev, res); 179 if (IS_ERR(eeprom->reg_base)) 180 return PTR_ERR(eeprom->reg_base); 181 182 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); 183 eeprom->mem_base = devm_ioremap_resource(dev, res); 184 if (IS_ERR(eeprom->mem_base)) 185 return PTR_ERR(eeprom->mem_base); 186 187 eeprom->clk = devm_clk_get(&pdev->dev, "eeprom"); 188 if (IS_ERR(eeprom->clk)) { 189 dev_err(&pdev->dev, "failed to get eeprom clock\n"); 190 return PTR_ERR(eeprom->clk); 191 } 192 193 ret = clk_prepare_enable(eeprom->clk); 194 if (ret < 0) { 195 dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret); 196 return ret; 197 } 198 199 rst = devm_reset_control_get_exclusive(dev, NULL); 200 if (IS_ERR(rst)) { 201 dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst)); 202 ret = PTR_ERR(rst); 203 goto err_clk; 204 } 205 206 ret = reset_control_assert(rst); 207 if (ret < 0) { 208 dev_err(dev, "failed to assert reset: %d\n", ret); 209 goto err_clk; 210 } 211 212 eeprom->val_bytes = 4; 213 eeprom->reg_bytes = 4; 214 215 /* 216 * Clock rate is generated by dividing the system bus clock by the 217 * division factor, contained in the divider register (minus 1 encoded). 218 */ 219 clk_rate = clk_get_rate(eeprom->clk); 220 clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1; 221 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate); 222 223 /* 224 * Writing a single word to the page will start the erase/program cycle 225 * automatically 226 */ 227 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG, 228 LPC18XX_EEPROM_AUTOPROG_WORD); 229 230 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 231 LPC18XX_EEPROM_PWRDWN_YES); 232 233 eeprom->size = resource_size(res); 234 lpc18xx_nvmem_config.size = resource_size(res); 235 lpc18xx_nvmem_config.dev = dev; 236 lpc18xx_nvmem_config.priv = eeprom; 237 238 eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config); 239 if (IS_ERR(eeprom->nvmem)) { 240 ret = PTR_ERR(eeprom->nvmem); 241 goto err_clk; 242 } 243 244 platform_set_drvdata(pdev, eeprom); 245 246 return 0; 247 248 err_clk: 249 clk_disable_unprepare(eeprom->clk); 250 251 return ret; 252 } 253 254 static int lpc18xx_eeprom_remove(struct platform_device *pdev) 255 { 256 struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev); 257 int ret; 258 259 ret = nvmem_unregister(eeprom->nvmem); 260 if (ret < 0) 261 return ret; 262 263 clk_disable_unprepare(eeprom->clk); 264 265 return 0; 266 } 267 268 static const struct of_device_id lpc18xx_eeprom_of_match[] = { 269 { .compatible = "nxp,lpc1857-eeprom" }, 270 { }, 271 }; 272 MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match); 273 274 static struct platform_driver lpc18xx_eeprom_driver = { 275 .probe = lpc18xx_eeprom_probe, 276 .remove = lpc18xx_eeprom_remove, 277 .driver = { 278 .name = "lpc18xx-eeprom", 279 .of_match_table = lpc18xx_eeprom_of_match, 280 }, 281 }; 282 283 module_platform_driver(lpc18xx_eeprom_driver); 284 285 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); 286 MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver"); 287 MODULE_LICENSE("GPL v2"); 288