1 /* 2 * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver 3 * 4 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/nvmem-provider.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 22 /* Registers */ 23 #define LPC18XX_EEPROM_AUTOPROG 0x00c 24 #define LPC18XX_EEPROM_AUTOPROG_WORD 0x1 25 26 #define LPC18XX_EEPROM_CLKDIV 0x014 27 28 #define LPC18XX_EEPROM_PWRDWN 0x018 29 #define LPC18XX_EEPROM_PWRDWN_NO 0x0 30 #define LPC18XX_EEPROM_PWRDWN_YES 0x1 31 32 #define LPC18XX_EEPROM_INTSTAT 0xfe0 33 #define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2) 34 35 #define LPC18XX_EEPROM_INTSTATCLR 0xfe8 36 #define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2) 37 38 /* Fixed page size (bytes) */ 39 #define LPC18XX_EEPROM_PAGE_SIZE 0x80 40 41 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */ 42 #define LPC18XX_EEPROM_CLOCK_HZ 1500000 43 44 /* EEPROM requires 3 ms of erase/program time between each writing */ 45 #define LPC18XX_EEPROM_PROGRAM_TIME 3 46 47 struct lpc18xx_eeprom_dev { 48 struct clk *clk; 49 void __iomem *reg_base; 50 void __iomem *mem_base; 51 struct nvmem_device *nvmem; 52 unsigned reg_bytes; 53 unsigned val_bytes; 54 int size; 55 }; 56 57 static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom, 58 u32 reg, u32 val) 59 { 60 writel(val, eeprom->reg_base + reg); 61 } 62 63 static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom, 64 u32 reg) 65 { 66 return readl(eeprom->reg_base + reg); 67 } 68 69 static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom) 70 { 71 unsigned long end; 72 u32 val; 73 74 /* Wait until EEPROM program operation has finished */ 75 end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10); 76 77 while (time_is_after_jiffies(end)) { 78 val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT); 79 80 if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) { 81 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR, 82 LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST); 83 return 0; 84 } 85 86 usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC, 87 (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC); 88 } 89 90 return -ETIMEDOUT; 91 } 92 93 static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg, 94 void *val, size_t bytes) 95 { 96 struct lpc18xx_eeprom_dev *eeprom = context; 97 unsigned int offset = reg; 98 int ret; 99 100 /* 101 * The last page contains the EEPROM initialization data and is not 102 * writable. 103 */ 104 if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) || 105 (reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE)) 106 return -EINVAL; 107 108 109 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 110 LPC18XX_EEPROM_PWRDWN_NO); 111 112 /* Wait 100 us while the EEPROM wakes up */ 113 usleep_range(100, 200); 114 115 while (bytes) { 116 writel(*(u32 *)val, eeprom->mem_base + offset); 117 ret = lpc18xx_eeprom_busywait_until_prog(eeprom); 118 if (ret < 0) 119 return ret; 120 121 bytes -= eeprom->val_bytes; 122 val += eeprom->val_bytes; 123 offset += eeprom->val_bytes; 124 } 125 126 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 127 LPC18XX_EEPROM_PWRDWN_YES); 128 129 return 0; 130 } 131 132 static int lpc18xx_eeprom_read(void *context, unsigned int offset, 133 void *val, size_t bytes) 134 { 135 struct lpc18xx_eeprom_dev *eeprom = context; 136 137 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 138 LPC18XX_EEPROM_PWRDWN_NO); 139 140 /* Wait 100 us while the EEPROM wakes up */ 141 usleep_range(100, 200); 142 143 while (bytes) { 144 *(u32 *)val = readl(eeprom->mem_base + offset); 145 bytes -= eeprom->val_bytes; 146 val += eeprom->val_bytes; 147 offset += eeprom->val_bytes; 148 } 149 150 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 151 LPC18XX_EEPROM_PWRDWN_YES); 152 153 return 0; 154 } 155 156 157 static struct nvmem_config lpc18xx_nvmem_config = { 158 .name = "lpc18xx-eeprom", 159 .stride = 4, 160 .word_size = 4, 161 .reg_read = lpc18xx_eeprom_read, 162 .reg_write = lpc18xx_eeprom_gather_write, 163 }; 164 165 static int lpc18xx_eeprom_probe(struct platform_device *pdev) 166 { 167 struct lpc18xx_eeprom_dev *eeprom; 168 struct device *dev = &pdev->dev; 169 struct reset_control *rst; 170 unsigned long clk_rate; 171 struct resource *res; 172 int ret; 173 174 eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL); 175 if (!eeprom) 176 return -ENOMEM; 177 178 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); 179 eeprom->reg_base = devm_ioremap_resource(dev, res); 180 if (IS_ERR(eeprom->reg_base)) 181 return PTR_ERR(eeprom->reg_base); 182 183 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); 184 eeprom->mem_base = devm_ioremap_resource(dev, res); 185 if (IS_ERR(eeprom->mem_base)) 186 return PTR_ERR(eeprom->mem_base); 187 188 eeprom->clk = devm_clk_get(&pdev->dev, "eeprom"); 189 if (IS_ERR(eeprom->clk)) { 190 dev_err(&pdev->dev, "failed to get eeprom clock\n"); 191 return PTR_ERR(eeprom->clk); 192 } 193 194 ret = clk_prepare_enable(eeprom->clk); 195 if (ret < 0) { 196 dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret); 197 return ret; 198 } 199 200 rst = devm_reset_control_get_exclusive(dev, NULL); 201 if (IS_ERR(rst)) { 202 dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst)); 203 ret = PTR_ERR(rst); 204 goto err_clk; 205 } 206 207 ret = reset_control_assert(rst); 208 if (ret < 0) { 209 dev_err(dev, "failed to assert reset: %d\n", ret); 210 goto err_clk; 211 } 212 213 eeprom->val_bytes = 4; 214 eeprom->reg_bytes = 4; 215 216 /* 217 * Clock rate is generated by dividing the system bus clock by the 218 * division factor, contained in the divider register (minus 1 encoded). 219 */ 220 clk_rate = clk_get_rate(eeprom->clk); 221 clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1; 222 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate); 223 224 /* 225 * Writing a single word to the page will start the erase/program cycle 226 * automatically 227 */ 228 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG, 229 LPC18XX_EEPROM_AUTOPROG_WORD); 230 231 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, 232 LPC18XX_EEPROM_PWRDWN_YES); 233 234 eeprom->size = resource_size(res); 235 lpc18xx_nvmem_config.size = resource_size(res); 236 lpc18xx_nvmem_config.dev = dev; 237 lpc18xx_nvmem_config.priv = eeprom; 238 239 eeprom->nvmem = devm_nvmem_register(dev, &lpc18xx_nvmem_config); 240 if (IS_ERR(eeprom->nvmem)) { 241 ret = PTR_ERR(eeprom->nvmem); 242 goto err_clk; 243 } 244 245 platform_set_drvdata(pdev, eeprom); 246 247 return 0; 248 249 err_clk: 250 clk_disable_unprepare(eeprom->clk); 251 252 return ret; 253 } 254 255 static int lpc18xx_eeprom_remove(struct platform_device *pdev) 256 { 257 struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev); 258 259 clk_disable_unprepare(eeprom->clk); 260 261 return 0; 262 } 263 264 static const struct of_device_id lpc18xx_eeprom_of_match[] = { 265 { .compatible = "nxp,lpc1857-eeprom" }, 266 { }, 267 }; 268 MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match); 269 270 static struct platform_driver lpc18xx_eeprom_driver = { 271 .probe = lpc18xx_eeprom_probe, 272 .remove = lpc18xx_eeprom_remove, 273 .driver = { 274 .name = "lpc18xx-eeprom", 275 .of_match_table = lpc18xx_eeprom_of_match, 276 }, 277 }; 278 279 module_platform_driver(lpc18xx_eeprom_driver); 280 281 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); 282 MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver"); 283 MODULE_LICENSE("GPL v2"); 284