1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i.MX6 OCOTP fusebox driver 4 * 5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 6 * 7 * Based on the barebox ocotp driver, 8 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, 9 * Orex Computed Radiography 10 * 11 * Write support based on the fsl_otp driver, 12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/nvmem-provider.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/delay.h> 25 26 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the 27 * OTP Bank0 Word0 28 */ 29 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr 30 * of two consecutive OTP words. 31 */ 32 33 #define IMX_OCOTP_ADDR_CTRL 0x0000 34 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 35 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 36 #define IMX_OCOTP_ADDR_TIMING 0x0010 37 #define IMX_OCOTP_ADDR_DATA0 0x0020 38 #define IMX_OCOTP_ADDR_DATA1 0x0030 39 #define IMX_OCOTP_ADDR_DATA2 0x0040 40 #define IMX_OCOTP_ADDR_DATA3 0x0050 41 42 #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F 43 #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 44 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 45 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 46 47 #define DEF_RELAX 20 /* > 16.5ns */ 48 #define DEF_FSOURCE 1001 /* > 1000 ns */ 49 #define DEF_STROBE_PROG 10000 /* IPG clocks */ 50 #define IMX_OCOTP_WR_UNLOCK 0x3E770000 51 #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA 52 53 static DEFINE_MUTEX(ocotp_mutex); 54 55 struct ocotp_priv { 56 struct device *dev; 57 struct clk *clk; 58 void __iomem *base; 59 const struct ocotp_params *params; 60 struct nvmem_config *config; 61 }; 62 63 struct ocotp_params { 64 unsigned int nregs; 65 unsigned int bank_address_words; 66 void (*set_timing)(struct ocotp_priv *priv); 67 }; 68 69 static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags) 70 { 71 int count; 72 u32 c, mask; 73 74 mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags; 75 76 for (count = 10000; count >= 0; count--) { 77 c = readl(base + IMX_OCOTP_ADDR_CTRL); 78 if (!(c & mask)) 79 break; 80 cpu_relax(); 81 } 82 83 if (count < 0) { 84 /* HW_OCOTP_CTRL[ERROR] will be set under the following 85 * conditions: 86 * - A write is performed to a shadow register during a shadow 87 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is 88 * set. In addition, the contents of the shadow register shall 89 * not be updated. 90 * - A write is performed to a shadow register which has been 91 * locked. 92 * - A read is performed to from a shadow register which has 93 * been read locked. 94 * - A program is performed to a fuse word which has been locked 95 * - A read is performed to from a fuse word which has been read 96 * locked. 97 */ 98 if (c & IMX_OCOTP_BM_CTRL_ERROR) 99 return -EPERM; 100 return -ETIMEDOUT; 101 } 102 103 return 0; 104 } 105 106 static void imx_ocotp_clr_err_if_set(void __iomem *base) 107 { 108 u32 c; 109 110 c = readl(base + IMX_OCOTP_ADDR_CTRL); 111 if (!(c & IMX_OCOTP_BM_CTRL_ERROR)) 112 return; 113 114 writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR); 115 } 116 117 static int imx_ocotp_read(void *context, unsigned int offset, 118 void *val, size_t bytes) 119 { 120 struct ocotp_priv *priv = context; 121 unsigned int count; 122 u32 *buf = val; 123 int i, ret; 124 u32 index; 125 126 index = offset >> 2; 127 count = bytes >> 2; 128 129 if (count > (priv->params->nregs - index)) 130 count = priv->params->nregs - index; 131 132 mutex_lock(&ocotp_mutex); 133 134 ret = clk_prepare_enable(priv->clk); 135 if (ret < 0) { 136 mutex_unlock(&ocotp_mutex); 137 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 138 return ret; 139 } 140 141 ret = imx_ocotp_wait_for_busy(priv->base, 0); 142 if (ret < 0) { 143 dev_err(priv->dev, "timeout during read setup\n"); 144 goto read_end; 145 } 146 147 for (i = index; i < (index + count); i++) { 148 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + 149 i * IMX_OCOTP_OFFSET_PER_WORD); 150 151 /* 47.3.1.2 152 * For "read locked" registers 0xBADABADA will be returned and 153 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by 154 * software before any new write, read or reload access can be 155 * issued 156 */ 157 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) 158 imx_ocotp_clr_err_if_set(priv->base); 159 } 160 ret = 0; 161 162 read_end: 163 clk_disable_unprepare(priv->clk); 164 mutex_unlock(&ocotp_mutex); 165 return ret; 166 } 167 168 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) 169 { 170 unsigned long clk_rate = 0; 171 unsigned long strobe_read, relax, strobe_prog; 172 u32 timing = 0; 173 174 /* 47.3.1.3.1 175 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] 176 * fields with timing values to match the current frequency of the 177 * ipg_clk. OTP writes will work at maximum bus frequencies as long 178 * as the HW_OCOTP_TIMING parameters are set correctly. 179 */ 180 clk_rate = clk_get_rate(priv->clk); 181 182 relax = clk_rate / (1000000000 / DEF_RELAX) - 1; 183 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; 184 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; 185 186 timing = strobe_prog & 0x00000FFF; 187 timing |= (relax << 12) & 0x0000F000; 188 timing |= (strobe_read << 16) & 0x003F0000; 189 190 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 191 } 192 193 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) 194 { 195 unsigned long clk_rate = 0; 196 u64 fsource, strobe_prog; 197 u32 timing = 0; 198 199 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 200 * 6.4.3.3 201 */ 202 clk_rate = clk_get_rate(priv->clk); 203 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, 204 NSEC_PER_SEC) + 1; 205 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, 206 NSEC_PER_SEC) + 1; 207 208 timing = strobe_prog & 0x00000FFF; 209 timing |= (fsource << 12) & 0x000FF000; 210 211 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 212 } 213 214 static int imx_ocotp_write(void *context, unsigned int offset, void *val, 215 size_t bytes) 216 { 217 struct ocotp_priv *priv = context; 218 u32 *buf = val; 219 int ret; 220 221 u32 ctrl; 222 u8 waddr; 223 u8 word = 0; 224 225 /* allow only writing one complete OTP word at a time */ 226 if ((bytes != priv->config->word_size) || 227 (offset % priv->config->word_size)) 228 return -EINVAL; 229 230 mutex_lock(&ocotp_mutex); 231 232 ret = clk_prepare_enable(priv->clk); 233 if (ret < 0) { 234 mutex_unlock(&ocotp_mutex); 235 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 236 return ret; 237 } 238 239 /* Setup the write timing values */ 240 priv->params->set_timing(priv); 241 242 /* 47.3.1.3.2 243 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. 244 * Overlapped accesses are not supported by the controller. Any pending 245 * write or reload must be completed before a write access can be 246 * requested. 247 */ 248 ret = imx_ocotp_wait_for_busy(priv->base, 0); 249 if (ret < 0) { 250 dev_err(priv->dev, "timeout during timing setup\n"); 251 goto write_end; 252 } 253 254 /* 47.3.1.3.3 255 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the 256 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed 257 * for each write access. The lock code is documented in the register 258 * description. Both the unlock code and address can be written in the 259 * same operation. 260 */ 261 if (priv->params->bank_address_words != 0) { 262 /* 263 * In banked/i.MX7 mode the OTP register bank goes into waddr 264 * see i.MX 7Solo Applications Processor Reference Manual, Rev. 265 * 0.1 section 6.4.3.1 266 */ 267 offset = offset / priv->config->word_size; 268 waddr = offset / priv->params->bank_address_words; 269 word = offset & (priv->params->bank_address_words - 1); 270 } else { 271 /* 272 * Non-banked i.MX6 mode. 273 * OTP write/read address specifies one of 128 word address 274 * locations 275 */ 276 waddr = offset / 4; 277 } 278 279 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); 280 ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR; 281 ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR; 282 ctrl |= IMX_OCOTP_WR_UNLOCK; 283 284 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); 285 286 /* 47.3.1.3.4 287 * Write the data to the HW_OCOTP_DATA register. This will automatically 288 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To 289 * protect programming same OTP bit twice, before program OCOTP will 290 * automatically read fuse value in OTP and use read value to mask 291 * program data. The controller will use masked program data to program 292 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit 293 * fields with 1's will result in that OTP bit being programmed. Bit 294 * fields with 0's will be ignored. At the same time that the write is 295 * accepted, the controller makes an internal copy of 296 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write 297 * sequence is initiated. This copy guarantees that erroneous writes to 298 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It 299 * should also be noted that during the programming HW_OCOTP_DATA will 300 * shift right (with zero fill). This shifting is required to program 301 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be 302 * modified. 303 * Note: on i.MX7 there are four data fields to write for banked write 304 * with the fuse blowing operation only taking place after data0 305 * has been written. This is why data0 must always be the last 306 * register written. 307 */ 308 if (priv->params->bank_address_words != 0) { 309 /* Banked/i.MX7 mode */ 310 switch (word) { 311 case 0: 312 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 313 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 314 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 315 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 316 break; 317 case 1: 318 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); 319 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 320 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 321 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 322 break; 323 case 2: 324 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 325 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); 326 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 327 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 328 break; 329 case 3: 330 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 331 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 332 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); 333 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 334 break; 335 } 336 } else { 337 /* Non-banked i.MX6 mode */ 338 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 339 } 340 341 /* 47.4.1.4.5 342 * Once complete, the controller will clear BUSY. A write request to a 343 * protected or locked region will result in no OTP access and no 344 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will 345 * be set. It must be cleared by software before any new write access 346 * can be issued. 347 */ 348 ret = imx_ocotp_wait_for_busy(priv->base, 0); 349 if (ret < 0) { 350 if (ret == -EPERM) { 351 dev_err(priv->dev, "failed write to locked region"); 352 imx_ocotp_clr_err_if_set(priv->base); 353 } else { 354 dev_err(priv->dev, "timeout during data write\n"); 355 } 356 goto write_end; 357 } 358 359 /* 47.3.1.4 360 * Write Postamble: Due to internal electrical characteristics of the 361 * OTP during writes, all OTP operations following a write must be 362 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following 363 * the write. 364 */ 365 udelay(2); 366 367 /* reload all shadow registers */ 368 writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS, 369 priv->base + IMX_OCOTP_ADDR_CTRL_SET); 370 ret = imx_ocotp_wait_for_busy(priv->base, 371 IMX_OCOTP_BM_CTRL_REL_SHADOWS); 372 if (ret < 0) { 373 dev_err(priv->dev, "timeout during shadow register reload\n"); 374 goto write_end; 375 } 376 377 write_end: 378 clk_disable_unprepare(priv->clk); 379 mutex_unlock(&ocotp_mutex); 380 if (ret < 0) 381 return ret; 382 return bytes; 383 } 384 385 static struct nvmem_config imx_ocotp_nvmem_config = { 386 .name = "imx-ocotp", 387 .read_only = false, 388 .word_size = 4, 389 .stride = 4, 390 .reg_read = imx_ocotp_read, 391 .reg_write = imx_ocotp_write, 392 }; 393 394 static const struct ocotp_params imx6q_params = { 395 .nregs = 128, 396 .bank_address_words = 0, 397 .set_timing = imx_ocotp_set_imx6_timing, 398 }; 399 400 static const struct ocotp_params imx6sl_params = { 401 .nregs = 64, 402 .bank_address_words = 0, 403 .set_timing = imx_ocotp_set_imx6_timing, 404 }; 405 406 static const struct ocotp_params imx6sll_params = { 407 .nregs = 128, 408 .bank_address_words = 0, 409 .set_timing = imx_ocotp_set_imx6_timing, 410 }; 411 412 static const struct ocotp_params imx6sx_params = { 413 .nregs = 128, 414 .bank_address_words = 0, 415 .set_timing = imx_ocotp_set_imx6_timing, 416 }; 417 418 static const struct ocotp_params imx6ul_params = { 419 .nregs = 128, 420 .bank_address_words = 0, 421 .set_timing = imx_ocotp_set_imx6_timing, 422 }; 423 424 static const struct ocotp_params imx6ull_params = { 425 .nregs = 64, 426 .bank_address_words = 0, 427 .set_timing = imx_ocotp_set_imx6_timing, 428 }; 429 430 static const struct ocotp_params imx7d_params = { 431 .nregs = 64, 432 .bank_address_words = 4, 433 .set_timing = imx_ocotp_set_imx7_timing, 434 }; 435 436 static const struct ocotp_params imx7ulp_params = { 437 .nregs = 256, 438 .bank_address_words = 0, 439 }; 440 441 static const struct ocotp_params imx8mq_params = { 442 .nregs = 256, 443 .bank_address_words = 4, 444 .set_timing = imx_ocotp_set_imx7_timing, 445 }; 446 447 static const struct of_device_id imx_ocotp_dt_ids[] = { 448 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, 449 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, 450 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params }, 451 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params }, 452 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params }, 453 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, 454 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, 455 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, 456 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, 457 { }, 458 }; 459 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); 460 461 static int imx_ocotp_probe(struct platform_device *pdev) 462 { 463 struct device *dev = &pdev->dev; 464 struct ocotp_priv *priv; 465 struct nvmem_device *nvmem; 466 467 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 468 if (!priv) 469 return -ENOMEM; 470 471 priv->dev = dev; 472 473 priv->base = devm_platform_ioremap_resource(pdev, 0); 474 if (IS_ERR(priv->base)) 475 return PTR_ERR(priv->base); 476 477 priv->clk = devm_clk_get(dev, NULL); 478 if (IS_ERR(priv->clk)) 479 return PTR_ERR(priv->clk); 480 481 priv->params = of_device_get_match_data(&pdev->dev); 482 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; 483 imx_ocotp_nvmem_config.dev = dev; 484 imx_ocotp_nvmem_config.priv = priv; 485 priv->config = &imx_ocotp_nvmem_config; 486 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); 487 488 489 return PTR_ERR_OR_ZERO(nvmem); 490 } 491 492 static struct platform_driver imx_ocotp_driver = { 493 .probe = imx_ocotp_probe, 494 .driver = { 495 .name = "imx_ocotp", 496 .of_match_table = imx_ocotp_dt_ids, 497 }, 498 }; 499 module_platform_driver(imx_ocotp_driver); 500 501 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); 502 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver"); 503 MODULE_LICENSE("GPL v2"); 504